1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. Reads from the 27 memory mapped view are unaffected by this control. 28 29- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 31 ``aarch64``. 32 33- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 34 one or more feature modifiers. This option has the form ``[no]feature+...`` 35 and defaults to ``none``. It translates into compiler option 36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 37 list of supported feature modifiers. 38 39- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 42 :ref:`Firmware Design`. 43 44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 47 48- ``BL2``: This is an optional build option which specifies the path to BL2 49 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 50 built. 51 52- ``BL2U``: This is an optional build option which specifies the path to 53 BL2U image. In this case, the BL2U in TF-A will not be built. 54 55- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 56 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 57 entrypoint) or 1 (CPU reset to BL2 entrypoint). 58 The default value is 0. 59 60- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 61 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 62 true in a 4-world system where RESET_TO_BL2 is 0. 63 64- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 65 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 66 67- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 68 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 69 the RW sections in RAM, while leaving the RO sections in place. This option 70 enable this use-case. For now, this option is only supported 71 when RESET_TO_BL2 is set to '1'. 72 73- ``BL31``: This is an optional build option which specifies the path to 74 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 75 be built. 76 77- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 78 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, 79 this file name will be used to save the key. 80 81- ``BL32``: This is an optional build option which specifies the path to 82 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 83 be built. 84 85- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 86 Trusted OS Extra1 image for the ``fip`` target. 87 88- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 89 Trusted OS Extra2 image for the ``fip`` target. 90 91- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 92 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, 93 this file name will be used to save the key. 94 95- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 96 ``fip`` target in case TF-A BL2 is used. 97 98- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 99 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, 100 this file name will be used to save the key. 101 102- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 103 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 104 If enabled, it is needed to use a compiler that supports the option 105 ``-mbranch-protection``. Selects the branch protection features to use: 106- 0: Default value turns off all types of branch protection 107- 1: Enables all types of branch protection features 108- 2: Return address signing to its standard level 109- 3: Extend the signing to include leaf functions 110- 4: Turn on branch target identification mechanism 111 112 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 113 and resulting PAuth/BTI features. 114 115 +-------+--------------+-------+-----+ 116 | Value | GCC option | PAuth | BTI | 117 +=======+==============+=======+=====+ 118 | 0 | none | N | N | 119 +-------+--------------+-------+-----+ 120 | 1 | standard | Y | Y | 121 +-------+--------------+-------+-----+ 122 | 2 | pac-ret | Y | N | 123 +-------+--------------+-------+-----+ 124 | 3 | pac-ret+leaf | Y | N | 125 +-------+--------------+-------+-----+ 126 | 4 | bti | N | Y | 127 +-------+--------------+-------+-----+ 128 129 This option defaults to 0. 130 Note that Pointer Authentication is enabled for Non-secure world 131 irrespective of the value of this option if the CPU supports it. 132 133- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 134 compilation of each build. It must be set to a C string (including quotes 135 where applicable). Defaults to a string that contains the time and date of 136 the compilation. 137 138- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 139 build to be uniquely identified. Defaults to the current git commit id. 140 141- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 142 143- ``CFLAGS``: Extra user options appended on the compiler's command line in 144 addition to the options set by the build system. 145 146- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 147 release several CPUs out of reset. It can take either 0 (several CPUs may be 148 brought up) or 1 (only one CPU will ever be brought up during cold reset). 149 Default is 0. If the platform always brings up a single CPU, there is no 150 need to distinguish between primary and secondary CPUs and the boot path can 151 be optimised. The ``plat_is_my_cpu_primary()`` and 152 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 153 to be implemented in this case. 154 155- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 156 Defaults to ``tbbr``. 157 158- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 159 register state when an unexpected exception occurs during execution of 160 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 161 this is only enabled for a debug build of the firmware. 162 163- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 164 certificate generation tool to create new keys in case no valid keys are 165 present or specified. Allowed options are '0' or '1'. Default is '1'. 166 167- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 168 the AArch32 system registers to be included when saving and restoring the 169 CPU context. The option must be set to 0 for AArch64-only platforms (that 170 is on hardware that does not implement AArch32, or at least not at EL1 and 171 higher ELs). Default value is 1. 172 173- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 174 registers to be included when saving and restoring the CPU context. Default 175 is 0. 176 177- ``CTX_INCLUDE_MTE_REGS``: Numeric value to include Memory Tagging Extension 178 registers in cpu context. This must be enabled, if the platform wants to use 179 this feature in the Secure world and MTE is enabled at ELX. This flag can 180 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 181 Default value is 0. 182 183- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 184 registers to be saved/restored when entering/exiting an EL2 execution 185 context. This flag can take values 0 to 2, to align with the 186 ``FEATURE_DETECTION`` mechanism. Default value is 0. 187 188- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 189 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 190 to be included when saving and restoring the CPU context as part of world 191 switch. This flag can take values 0 to 2, to align with ``FEATURE_DETECTION`` 192 mechanism. Default value is 0. 193 194 Note that Pointer Authentication is enabled for Non-secure world irrespective 195 of the value of this flag if the CPU supports it. 196 197- ``DEBUG``: Chooses between a debug and release build. It can take either 0 198 (release) or 1 (debug) as values. 0 is the default. 199 200- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 201 authenticated decryption algorithm to be used to decrypt firmware/s during 202 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 203 this flag is ``none`` to disable firmware decryption which is an optional 204 feature as per TBBR. 205 206- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 207 of the binary image. If set to 1, then only the ELF image is built. 208 0 is the default. 209 210- ``DISABLE_MTPMU``: Boolean option to disable FEAT_MTPMU if implemented 211 (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms 212 that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU, 213 check the latest Arm ARM. 214 215- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 216 Board Boot authentication at runtime. This option is meant to be enabled only 217 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 218 flag has to be enabled. 0 is the default. 219 220- ``E``: Boolean option to make warnings into errors. Default is 1. 221 222 When specifying higher warnings levels (``W=1`` and higher), this option 223 defaults to 0. This is done to encourage contributors to use them, as they 224 are expected to produce warnings that would otherwise fail the build. New 225 contributions are still expected to build with ``W=0`` and ``E=1`` (the 226 default). 227 228- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 229 the normal boot flow. It must specify the entry point address of the EL3 230 payload. Please refer to the "Booting an EL3 payload" section for more 231 details. 232 233- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 234 (also known as group 1 counters). These are implementation-defined counters, 235 and as such require additional platform configuration. Default is 0. 236 237- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which 238 allows platforms with auxiliary counters to describe them via the 239 ``HW_CONFIG`` device tree blob. Default is 0. 240 241- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 242 are compiled out. For debug builds, this option defaults to 1, and calls to 243 ``assert()`` are left in place. For release builds, this option defaults to 0 244 and calls to ``assert()`` function are compiled out. This option can be set 245 independently of ``DEBUG``. It can also be used to hide any auxiliary code 246 that is only required for the assertion and does not fit in the assertion 247 itself. 248 249- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 250 dumps or not. It is supported in both AArch64 and AArch32. However, in 251 AArch32 the format of the frame records are not defined in the AAPCS and they 252 are defined by the implementation. This implementation of backtrace only 253 supports the format used by GCC when T32 interworking is disabled. For this 254 reason enabling this option in AArch32 will force the compiler to only 255 generate A32 code. This option is enabled by default only in AArch64 debug 256 builds, but this behaviour can be overridden in each platform's Makefile or 257 in the build command line. 258 259- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 260 extensions. This flag can take the values 0 to 2, to align with the 261 ``FEATURE_DETECTION`` mechanism. This is an optional architectural feature 262 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 263 and this option can be used to enable this feature on those systems as well. 264 This flag can take the values 0 to 2, the default is 0. 265 266- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 267 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 268 onwards. This flag can take the values 0 to 2, to align with the 269 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 270 271- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 272 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 273 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 274 optional feature available on Arm v8.0 onwards. This flag can take values 275 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 276 Default value is ``0``. 277 278- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 279 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 280 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 281 and upwards. This flag can take the values 0 to 2, to align with the 282 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 283 284- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 285 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 286 Physical Offset register) during EL2 to EL3 context save/restore operations. 287 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 288 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 289 mechanism. Default value is ``0``. 290 291- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 292 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 293 Read Trap Register) during EL2 to EL3 context save/restore operations. 294 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 295 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 296 mechanism. Default value is ``0``. 297 298- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 299 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 300 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 301 mandatory architectural feature and is enabled from v8.7 and upwards. This 302 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 303 mechanism. Default value is ``0``. 304 305- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 306 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 307 permission fault for any privileged data access from EL1/EL2 to virtual 308 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 309 mandatory architectural feature and is enabled from v8.1 and upwards. This 310 flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 311 mechanism. Default value is ``0``. 312 313- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 314 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 315 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 316 mechanism. Default value is ``0``. 317 318- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 319 extension. This feature is only supported in AArch64 state. This flag can 320 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 321 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 322 Armv8.5 onwards. 323 324- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB`` 325 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 326 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 327 later CPUs. It is enabled from v8.5 and upwards and if needed can be 328 overidden from platforms explicitly. 329 330- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 331 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 332 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 333 mechanism. Default is ``0``. 334 335- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 336 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 337 available on Arm v8.6. This flag can take values 0 to 2, to align with the 338 ``FEATURE_DETECTION`` mechanism. Default is ``0``. 339 340 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 341 delayed by the amount of value in ``TWED_DELAY``. 342 343- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 344 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 345 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 346 architectural feature and is enabled from v8.1 and upwards. It can take 347 values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 348 Default value is ``0``. 349 350- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 351 allow access to TCR2_EL2 (extended translation control) from EL2 as 352 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 353 mandatory architectural feature and is enabled from v8.9 and upwards. This 354 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 355 mechanism. Default value is ``0``. 356 357- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 358 at EL2 and below, and context switch relevant registers. This flag 359 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 360 mechanism. Default value is ``0``. 361 362- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 363 at EL2 and below, and context switch relevant registers. This flag 364 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 365 mechanism. Default value is ``0``. 366 367- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 368 at EL2 and below, and context switch relevant registers. This flag 369 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 370 mechanism. Default value is ``0``. 371 372- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 373 at EL2 and below, and context switch relevant registers. This flag 374 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 375 mechanism. Default value is ``0``. 376 377- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to 378 allow use of Guarded Control Stack from EL2 as well as adding the GCS 379 registers to the EL2 context save/restore operations. This flag can take 380 the values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 381 Default value is ``0``. 382 383- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 384 support in GCC for TF-A. This option is currently only supported for 385 AArch64. Default is 0. 386 387- ``ENABLE_MPAM_FOR_LOWER_ELS``: Numeric value to enable lower ELs to use MPAM 388 feature. MPAM is an optional Armv8.4 extension that enables various memory 389 system components and resources to define partitions; software running at 390 various ELs can assign themselves to desired partition to control their 391 performance aspects. 392 393 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 394 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 395 access their own MPAM registers without trapping into EL3. This option 396 doesn't make use of partitioning in EL3, however. Platform initialisation 397 code should configure and use partitions in EL3 as required. This option 398 defaults to ``0``. 399 400- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 401 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 402 firmware to detect and limit high activity events to assist in SoC processor 403 power domain dynamic power budgeting and limit the triggering of whole-rail 404 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 405 406- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which 407 allows platforms with cores supporting MPMM to describe them via the 408 ``HW_CONFIG`` device tree blob. Default is 0. 409 410- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 411 support within generic code in TF-A. This option is currently only supported 412 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 413 in BL32 (SP_min) for AARCH32. Default is 0. 414 415- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 416 Measurement Framework(PMF). Default is 0. 417 418- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 419 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 420 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 421 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 422 software. 423 424- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 425 Management Extension. This flag can take the values 0 to 2, to align with 426 the ``FEATURE_DETECTION`` mechanism. Default value is 0. This is currently 427 an experimental feature. 428 429- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 430 instrumentation which injects timestamp collection points into TF-A to 431 allow runtime performance to be measured. Currently, only PSCI is 432 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 433 as well. Default is 0. 434 435- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 436 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 437 registers so are enabled together. Using this option without 438 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 439 world to trap to EL3. SME is an optional architectural feature for AArch64 440 and TF-A support is experimental. At this time, this build option cannot be 441 used on systems that have SPD=spmd/SPM_MM or ENABLE_RME, and attempting to 442 build with these options will fail. This flag can take the values 0 to 2, to 443 align with the ``FEATURE_DETECTION`` mechanism. Default is 0. 444 445- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 446 Extension for secure world use along with SVE and FPU/SIMD, ENABLE_SME_FOR_NS 447 must also be set to use this. If enabling this, the secure world MUST 448 handle context switching for SME, SVE, and FPU/SIMD registers to ensure that 449 no data is leaked to non-secure world. This is experimental. Default is 0. 450 451- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 452 extensions. This is an optional architectural feature for AArch64. 453 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 454 mechanism. The default is 2 but is automatically disabled when the target 455 architecture is AArch32. 456 457- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 458 (SVE) for the Non-secure world only. SVE is an optional architectural feature 459 for AArch64. Note that when SVE is enabled for the Non-secure world, access 460 to SIMD and floating-point functionality from the Secure world is disabled by 461 default and controlled with ENABLE_SVE_FOR_SWD. 462 This is to avoid corruption of the Non-secure world data in the Z-registers 463 which are aliased by the SIMD and FP registers. The build option is not 464 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 465 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` enabled. 466 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 467 mechanism. The default is 2 but is automatically disabled when 468 ENABLE_SME_FOR_NS is enabled ( set to 1 or 2) since SME encompasses SVE. 469 At this time, this build option cannot be used on systems that have SPM_MM 470 enabled. 471 472- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. 473 SVE is an optional architectural feature for AArch64. Note that this option 474 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it 475 is automatically disabled when the target architecture is AArch32. 476 477- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 478 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 479 default value is set to "none". "strong" is the recommended stack protection 480 level if this feature is desired. "none" disables the stack protection. For 481 all values other than "none", the ``plat_get_stack_protector_canary()`` 482 platform hook needs to be implemented. The value is passed as the last 483 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 484 485- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 486 flag depends on ``DECRYPTION_SUPPORT`` build flag. 487 488- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 489 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 490 491- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 492 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 493 on ``DECRYPTION_SUPPORT`` build flag. 494 495- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 496 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 497 build flag. 498 499- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 500 deprecated platform APIs, helper functions or drivers within Trusted 501 Firmware as error. It can take the value 1 (flag the use of deprecated 502 APIs as error) or 0. The default is 0. 503 504- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 505 targeted at EL3. When set ``0`` (default), no exceptions are expected or 506 handled at EL3, and a panic will result. The exception to this rule is when 507 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 508 occuring during normal world execution, are trapped to EL3. Any exception 509 trapped during secure world execution are trapped to the SPMC. This is 510 supported only for AArch64 builds. 511 512- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 513 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 514 Default value is 40 (LOG_LEVEL_INFO). 515 516- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 517 injection from lower ELs, and this build option enables lower ELs to use 518 Error Records accessed via System Registers to inject faults. This is 519 applicable only to AArch64 builds. 520 521 This feature is intended for testing purposes only, and is advisable to keep 522 disabled for production images. 523 524- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 525 detection mechanism. It detects whether the Architectural features enabled 526 through feature specific build flags are supported by the PE or not by 527 validating them either at boot phase or at runtime based on the value 528 possessed by the feature flag (0 to 2) and report error messages at an early 529 stage. 530 531 This prevents and benefits us from EL3 runtime exceptions during context save 532 and restore routines guarded by these build flags. Henceforth validating them 533 before their usage provides more control on the actions taken under them. 534 535 The mechanism permits the build flags to take values 0, 1 or 2 and 536 evaluates them accordingly. 537 538 Lets consider ``ENABLE_FEAT_HCX``, build flag for ``FEAT_HCX`` as an example: 539 540 :: 541 542 ENABLE_FEAT_HCX = 0: Feature disabled statically at compile time. 543 ENABLE_FEAT_HCX = 1: Feature Enabled and the flag is validated at boottime. 544 ENABLE_FEAT_HCX = 2: Feature Enabled and the flag is validated at runtime. 545 546 In the above example, if the feature build flag, ``ENABLE_FEAT_HCX`` set to 547 0, feature is disabled statically during compilation. If it is defined as 1, 548 feature is validated, wherein FEAT_HCX is detected at boot time. In case not 549 implemented by the PE, a hard panic is generated. Finally, if the flag is set 550 to 2, feature is validated at runtime. 551 552 Note that the entire implementation is divided into two phases, wherein as 553 as part of phase-1 we are supporting the values 0,1. Value 2 is currently not 554 supported and is planned to be handled explicilty in phase-2 implementation. 555 556 FEATURE_DETECTION macro is disabled by default, and is currently an 557 experimental procedure. Platforms can explicitly make use of this by 558 mechanism, by enabling it to validate whether they have set their build flags 559 properly at an early phase. 560 561- ``FIP_NAME``: This is an optional build option which specifies the FIP 562 filename for the ``fip`` target. Default is ``fip.bin``. 563 564- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 565 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 566 567- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 568 569 :: 570 571 0: Encryption is done with Secret Symmetric Key (SSK) which is common 572 for a class of devices. 573 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 574 unique per device. 575 576 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 577 578- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 579 tool to create certificates as per the Chain of Trust described in 580 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 581 include the certificates in the FIP and FWU_FIP. Default value is '0'. 582 583 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 584 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 585 the corresponding certificates, and to include those certificates in the 586 FIP and FWU_FIP. 587 588 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 589 images will not include support for Trusted Board Boot. The FIP will still 590 include the corresponding certificates. This FIP can be used to verify the 591 Chain of Trust on the host machine through other mechanisms. 592 593 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 594 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 595 will not include the corresponding certificates, causing a boot failure. 596 597- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 598 inherent support for specific EL3 type interrupts. Setting this build option 599 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 600 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 601 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 602 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 603 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 604 the Secure Payload interrupts needs to be synchronously handed over to Secure 605 EL1 for handling. The default value of this option is ``0``, which means the 606 Group 0 interrupts are assumed to be handled by Secure EL1. 607 608- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 609 Interrupts, resulting from errors in NS world, will be always trapped in 610 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 611 will be trapped in the current exception level (or in EL1 if the current 612 exception level is EL0). 613 614- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 615 software operations are required for CPUs to enter and exit coherency. 616 However, newer systems exist where CPUs' entry to and exit from coherency 617 is managed in hardware. Such systems require software to only initiate these 618 operations, and the rest is managed in hardware, minimizing active software 619 management. In such systems, this boolean option enables TF-A to carry out 620 build and run-time optimizations during boot and power management operations. 621 This option defaults to 0 and if it is enabled, then it implies 622 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 623 624 If this flag is disabled while the platform which TF-A is compiled for 625 includes cores that manage coherency in hardware, then a compilation error is 626 generated. This is based on the fact that a system cannot have, at the same 627 time, cores that manage coherency in hardware and cores that don't. In other 628 words, a platform cannot have, at the same time, cores that require 629 ``HW_ASSISTED_COHERENCY=1`` and cores that require 630 ``HW_ASSISTED_COHERENCY=0``. 631 632 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 633 translation library (xlat tables v2) must be used; version 1 of translation 634 library is not supported. 635 636- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 637 bottom, higher addresses at the top. This build flag can be set to '1' to 638 invert this behavior. Lower addresses will be printed at the top and higher 639 addresses at the bottom. 640 641- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 642 runtime software in AArch32 mode, which is required to run AArch32 on Juno. 643 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in 644 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable 645 images. 646 647- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 648 used for generating the PKCS keys and subsequent signing of the certificate. 649 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 650 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 651 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 652 compatibility. The default value of this flag is ``rsa`` which is the TBBR 653 compliant PKCS#1 RSA 2.1 scheme. 654 655- ``KEY_SIZE``: This build flag enables the user to select the key size for 656 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 657 depend on the chosen algorithm and the cryptographic module. 658 659 +---------------------------+------------------------------------+ 660 | KEY_ALG | Possible key sizes | 661 +===========================+====================================+ 662 | rsa | 1024 , 2048 (default), 3072, 4096* | 663 +---------------------------+------------------------------------+ 664 | ecdsa | unavailable | 665 +---------------------------+------------------------------------+ 666 | ecdsa-brainpool-regular | unavailable | 667 +---------------------------+------------------------------------+ 668 | ecdsa-brainpool-twisted | unavailable | 669 +---------------------------+------------------------------------+ 670 671 672 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. 673 Only 3072 bits size is available with CryptoCell 712 SBROM release 2. 674 675- ``HASH_ALG``: This build flag enables the user to select the secure hash 676 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 677 The default value of this flag is ``sha256``. 678 679- ``LDFLAGS``: Extra user options appended to the linkers' command line in 680 addition to the one set by the build system. 681 682- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 683 output compiled into the build. This should be one of the following: 684 685 :: 686 687 0 (LOG_LEVEL_NONE) 688 10 (LOG_LEVEL_ERROR) 689 20 (LOG_LEVEL_NOTICE) 690 30 (LOG_LEVEL_WARNING) 691 40 (LOG_LEVEL_INFO) 692 50 (LOG_LEVEL_VERBOSE) 693 694 All log output up to and including the selected log level is compiled into 695 the build. The default value is 40 in debug builds and 20 in release builds. 696 697- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 698 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 699 provide trust that the code taking the measurements and recording them has 700 not been tampered with. 701 702 This option defaults to 0. 703 704- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 705 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 706 the measurements and recording them as per `PSA DRTM specification`_. For 707 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 708 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 709 should have mechanism to authenticate BL31. This is an experimental feature. 710 711 This option defaults to 0. 712 713- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 714 specifies the file that contains the Non-Trusted World private key in PEM 715 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 716 717- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 718 optional. It is only needed if the platform makefile specifies that it 719 is required in order to build the ``fwu_fip`` target. 720 721- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 722 contents upon world switch. It can take either 0 (don't save and restore) or 723 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 724 wants the timer registers to be saved and restored. 725 726- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 727 for the BL image. It can be either 0 (include) or 1 (remove). The default 728 value is 0. 729 730- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 731 the underlying hardware is not a full PL011 UART but a minimally compliant 732 generic UART, which is a subset of the PL011. The driver will not access 733 any register that is not part of the SBSA generic UART specification. 734 Default value is 0 (a full PL011 compliant UART is present). 735 736- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 737 must be subdirectory of any depth under ``plat/``, and must contain a 738 platform makefile named ``platform.mk``. For example, to build TF-A for the 739 Arm Juno board, select PLAT=juno. 740 741- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 742 instead of the normal boot flow. When defined, it must specify the entry 743 point address for the preloaded BL33 image. This option is incompatible with 744 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 745 over ``PRELOADED_BL33_BASE``. 746 747- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 748 vector address can be programmed or is fixed on the platform. It can take 749 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 750 programmable reset address, it is expected that a CPU will start executing 751 code directly at the right address, both on a cold and warm reset. In this 752 case, there is no need to identify the entrypoint on boot and the boot path 753 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 754 does not need to be implemented in this case. 755 756- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 757 possible for the PSCI power-state parameter: original and extended State-ID 758 formats. This flag if set to 1, configures the generic PSCI layer to use the 759 extended format. The default value of this flag is 0, which means by default 760 the original power-state format is used by the PSCI implementation. This flag 761 should be specified by the platform makefile and it governs the return value 762 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 763 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 764 set to 1 as well. 765 766- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 767 OS-initiated mode. This option defaults to 0. 768 769- ``RAS_EXTENSION``: Numeric value to enable Armv8.2 RAS features. RAS features 770 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 771 or later CPUs. This flag can take the values 0 to 2, to align with the 772 ``FEATURE_DETECTION`` mechanism. 773 774 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST_NS`` must also be 775 set to ``1``. 776 777 This option is disabled by default. 778 779- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 780 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 781 entrypoint) or 1 (CPU reset to BL31 entrypoint). 782 The default value is 0. 783 784- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 785 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 786 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 787 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 788 789- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 790 file that contains the ROT private key in PEM format and enforces public key 791 hash generation. If ``SAVE_KEYS=1``, this 792 file name will be used to save the key. 793 794- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 795 certificate generation tool to save the keys used to establish the Chain of 796 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 797 798- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 799 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 800 target. 801 802- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 803 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, 804 this file name will be used to save the key. 805 806- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 807 optional. It is only needed if the platform makefile specifies that it 808 is required in order to build the ``fwu_fip`` target. 809 810- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 811 Delegated Exception Interface to BL31 image. This defaults to ``0``. 812 813 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 814 set to ``1``. 815 816- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 817 isolated on separate memory pages. This is a trade-off between security and 818 memory usage. See "Isolating code and read-only data on separate memory 819 pages" section in :ref:`Firmware Design`. This flag is disabled by default 820 and affects all BL images. 821 822- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 823 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 824 allocated in RAM discontiguous from the loaded firmware image. When set, the 825 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 826 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 827 sections are placed in RAM immediately following the loaded firmware image. 828 829- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 830 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 831 discontiguous from loaded firmware images. When set, the platform need to 832 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 833 flag is disabled by default and NOLOAD sections are placed in RAM immediately 834 following the loaded firmware image. 835 836- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 837 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 838 UEFI+ACPI this can provide a certain amount of OS forward compatibility 839 with newer platforms that aren't ECAM compliant. 840 841- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 842 This build option is only valid if ``ARCH=aarch64``. The value should be 843 the path to the directory containing the SPD source, relative to 844 ``services/spd/``; the directory is expected to contain a makefile called 845 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 846 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 847 cannot be enabled when the ``SPM_MM`` option is enabled. 848 849- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 850 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 851 execution in BL1 just before handing over to BL31. At this point, all 852 firmware images have been loaded in memory, and the MMU and caches are 853 turned off. Refer to the "Debugging options" section for more details. 854 855- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 856 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 857 component runs at the EL3 exception level. The default value is ``0`` ( 858 disabled). This configuration supports pre-Armv8.4 platforms (aka not 859 implementing the ``FEAT_SEL2`` extension). This is an experimental feature. 860 861- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 862 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 863 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 864 mechanism should be used. 865 866- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 867 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 868 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 869 extension. This is the default when enabling the SPM Dispatcher. When 870 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 871 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 872 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 873 extension). 874 875- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 876 Partition Manager (SPM) implementation. The default value is ``0`` 877 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 878 enabled (``SPD=spmd``). 879 880- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 881 description of secure partitions. The build system will parse this file and 882 package all secure partition blobs into the FIP. This file is not 883 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 884 885- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 886 secure interrupts (caught through the FIQ line). Platforms can enable 887 this directive if they need to handle such interruption. When enabled, 888 the FIQ are handled in monitor mode and non secure world is not allowed 889 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 890 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 891 892- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 893 Platforms can configure this if they need to lower the hardware 894 limit, for example due to asymmetric configuration or limitations of 895 software run at lower ELs. The default is the architectural maximum 896 of 2048 which should be suitable for most configurations, the 897 hardware will limit the effective VL to the maximum physically supported 898 VL. 899 900- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 901 Random Number Generator Interface to BL31 image. This defaults to ``0``. 902 903- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 904 Boot feature. When set to '1', BL1 and BL2 images include support to load 905 and verify the certificates and images in a FIP, and BL1 includes support 906 for the Firmware Update. The default value is '0'. Generation and inclusion 907 of certificates in the FIP and FWU_FIP depends upon the value of the 908 ``GENERATE_COT`` option. 909 910 .. warning:: 911 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 912 already exist in disk, they will be overwritten without further notice. 913 914- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 915 specifies the file that contains the Trusted World private key in PEM 916 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 917 918- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 919 synchronous, (see "Initializing a BL32 Image" section in 920 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 921 synchronous method) or 1 (BL32 is initialized using asynchronous method). 922 Default is 0. 923 924- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 925 routing model which routes non-secure interrupts asynchronously from TSP 926 to EL3 causing immediate preemption of TSP. The EL3 is responsible 927 for saving and restoring the TSP context in this routing model. The 928 default routing model (when the value is 0) is to route non-secure 929 interrupts to TSP allowing it to save its context and hand over 930 synchronously to EL3 via an SMC. 931 932 .. note:: 933 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 934 must also be set to ``1``. 935 936- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 937 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 938 this delay. It can take values in the range (0-15). Default value is ``0`` 939 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 940 Platforms need to explicitly update this value based on their requirements. 941 942- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 943 linker. When the ``LINKER`` build variable points to the armlink linker, 944 this flag is enabled automatically. To enable support for armlink, platforms 945 will have to provide a scatter file for the BL image. Currently, Tegra 946 platforms use the armlink support to compile BL3-1 images. 947 948- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 949 memory region in the BL memory map or not (see "Use of Coherent memory in 950 TF-A" section in :ref:`Firmware Design`). It can take the value 1 951 (Coherent memory region is included) or 0 (Coherent memory region is 952 excluded). Default is 1. 953 954- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature 955 exposing a virtual filesystem interface through BL31 as a SiP SMC function. 956 Default is 0. 957 958- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 959 firmware configuration framework. This will move the io_policies into a 960 configuration device tree, instead of static structure in the code base. 961 962- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 963 at runtime using fconf. If this flag is enabled, COT descriptors are 964 statically captured in tb_fw_config file in the form of device tree nodes 965 and properties. Currently, COT descriptors used by BL2 are moved to the 966 device tree and COT descriptors used by BL1 are retained in the code 967 base statically. 968 969- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 970 runtime using firmware configuration framework. The platform specific SDEI 971 shared and private events configuration is retrieved from device tree rather 972 than static C structures at compile time. This is only supported if 973 SDEI_SUPPORT build flag is enabled. 974 975- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 976 and Group1 secure interrupts using the firmware configuration framework. The 977 platform specific secure interrupt property descriptor is retrieved from 978 device tree in runtime rather than depending on static C structure at compile 979 time. 980 981- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 982 This feature creates a library of functions to be placed in ROM and thus 983 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 984 is 0. 985 986- ``V``: Verbose build. If assigned anything other than 0, the build commands 987 are printed. Default is 0. 988 989- ``VERSION_STRING``: String used in the log output for each TF-A image. 990 Defaults to a string formed by concatenating the version number, build type 991 and build string. 992 993- ``W``: Warning level. Some compiler warning options of interest have been 994 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 995 each level enabling more warning options. Default is 0. 996 997 This option is closely related to the ``E`` option, which enables 998 ``-Werror``. 999 1000 - ``W=0`` (default) 1001 1002 Enables a wide assortment of warnings, most notably ``-Wall`` and 1003 ``-Wextra``, as well as various bad practices and things that are likely to 1004 result in errors. Includes some compiler specific flags. No warnings are 1005 expected at this level for any build. 1006 1007 - ``W=1`` 1008 1009 Enables warnings we want the generic build to include but are too time 1010 consuming to fix at the moment. It re-enables warnings taken out for 1011 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1012 to eventually be merged into ``W=0``. Some warnings are expected on some 1013 builds, but new contributions should not introduce new ones. 1014 1015 - ``W=2`` (recommended) 1016 1017 Enables warnings we want the generic build to include but cannot be enabled 1018 due to external libraries. This level is expected to eventually be merged 1019 into ``W=0``. Lots of warnings are expected, primarily from external 1020 libraries like zlib and compiler-rt, but new controbutions should not 1021 introduce new ones. 1022 1023 - ``W=3`` 1024 1025 Enables warnings that are informative but not necessary and generally too 1026 verbose and frequently ignored. A very large number of warnings are 1027 expected. 1028 1029 The exact set of warning flags depends on the compiler and TF-A warning 1030 level, however they are all succinctly set in the top-level Makefile. Please 1031 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1032 individual flags. 1033 1034- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1035 the CPU after warm boot. This is applicable for platforms which do not 1036 require interconnect programming to enable cache coherency (eg: single 1037 cluster platforms). If this option is enabled, then warm boot path 1038 enables D-caches immediately after enabling MMU. This option defaults to 0. 1039 1040- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 1041 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 1042 default value of this flag is ``no``. Note this option must be enabled only 1043 for ARM architecture greater than Armv8.5-A. 1044 1045- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1046 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1047 The default value of this flag is ``0``. 1048 1049 ``AT`` speculative errata workaround disables stage1 page table walk for 1050 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1051 produces either the correct result or failure without TLB allocation. 1052 1053 This boolean option enables errata for all below CPUs. 1054 1055 +---------+--------------+-------------------------+ 1056 | Errata | CPU | Workaround Define | 1057 +=========+==============+=========================+ 1058 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1059 +---------+--------------+-------------------------+ 1060 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1061 +---------+--------------+-------------------------+ 1062 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1063 +---------+--------------+-------------------------+ 1064 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1065 +---------+--------------+-------------------------+ 1066 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1067 +---------+--------------+-------------------------+ 1068 1069 .. note:: 1070 This option is enabled by build only if platform sets any of above defines 1071 mentioned in ’Workaround Define' column in the table. 1072 If this option is enabled for the EL3 software then EL2 software also must 1073 implement this workaround due to the behaviour of the errata mentioned 1074 in new SDEN document which will get published soon. 1075 1076- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1077 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1078 This flag is disabled by default. 1079 1080- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1081 host machine where a custom installation of OpenSSL is located, which is used 1082 to build the certificate generation, firmware encryption and FIP tools. If 1083 this option is not set, the default OS installation will be used. 1084 1085- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1086 functions that wait for an arbitrary time length (udelay and mdelay). The 1087 default value is 0. 1088 1089- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1090 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1091 optional architectural feature for AArch64. This flag can take the values 1092 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0 1093 and it is automatically disabled when the target architecture is AArch32. 1094 1095- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1096 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1097 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1098 feature for AArch64. This flag can take the values 0 to 2, to align with the 1099 ``FEATURE_DETECTION`` mechanism. The default is 0 and it is automatically 1100 disabled when the target architecture is AArch32. 1101 1102- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1103 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1104 but unused). This feature is available if trace unit such as ETMv4.x, and 1105 ETE(extending ETM feature) is implemented. This flag can take the values 1106 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0. 1107 1108- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1109 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1110 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1111 with the ``FEATURE_DETECTION`` mechanism. This flag is disabled by default. 1112 1113- ``PLAT_RSS_NOT_SUPPORTED``: Boolean option to enable the usage of the PSA 1114 APIs on platforms that doesn't support RSS (providing Arm CCA HES 1115 functionalities). When enabled (``1``), a mocked version of the APIs are used. 1116 The default value is 0. 1117 1118- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1119 ``plat_can_cmo`` which will return zero if cache management operations should 1120 be skipped and non-zero otherwise. By default, this option is disabled which 1121 means platform hook won't be checked and CMOs will always be performed when 1122 related functions are called. 1123 1124GICv3 driver options 1125-------------------- 1126 1127GICv3 driver files are included using directive: 1128 1129``include drivers/arm/gic/v3/gicv3.mk`` 1130 1131The driver can be configured with the following options set in the platform 1132makefile: 1133 1134- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1135 Enabling this option will add runtime detection support for the 1136 GIC-600, so is safe to select even for a GIC500 implementation. 1137 This option defaults to 0. 1138 1139- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1140 for GIC-600 AE. Enabling this option will introduce support to initialize 1141 the FMU. Platforms should call the init function during boot to enable the 1142 FMU and its safety mechanisms. This option defaults to 0. 1143 1144- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1145 functionality. This option defaults to 0 1146 1147- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1148 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1149 functions. This is required for FVP platform which need to simulate GIC save 1150 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1151 1152- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1153 This option defaults to 0. 1154 1155- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1156 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1157 1158Debugging options 1159----------------- 1160 1161To compile a debug version and make the build more verbose use 1162 1163.. code:: shell 1164 1165 make PLAT=<platform> DEBUG=1 V=1 all 1166 1167AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1168(for example Arm-DS) might not support this and may need an older version of 1169DWARF symbols to be emitted by GCC. This can be achieved by using the 1170``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1171the version to 4 is recommended for Arm-DS. 1172 1173When debugging logic problems it might also be useful to disable all compiler 1174optimizations by using ``-O0``. 1175 1176.. warning:: 1177 Using ``-O0`` could cause output images to be larger and base addresses 1178 might need to be recalculated (see the **Memory layout on Arm development 1179 platforms** section in the :ref:`Firmware Design`). 1180 1181Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1182``LDFLAGS``: 1183 1184.. code:: shell 1185 1186 CFLAGS='-O0 -gdwarf-2' \ 1187 make PLAT=<platform> DEBUG=1 V=1 all 1188 1189Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1190ignored as the linker is called directly. 1191 1192It is also possible to introduce an infinite loop to help in debugging the 1193post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1194``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1195section. In this case, the developer may take control of the target using a 1196debugger when indicated by the console output. When using Arm-DS, the following 1197commands can be used: 1198 1199:: 1200 1201 # Stop target execution 1202 interrupt 1203 1204 # 1205 # Prepare your debugging environment, e.g. set breakpoints 1206 # 1207 1208 # Jump over the debug loop 1209 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1210 1211 # Resume execution 1212 continue 1213 1214Firmware update options 1215----------------------- 1216 1217- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1218 in defining the firmware update metadata structure. This flag is by default 1219 set to '2'. 1220 1221- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1222 firmware bank. Each firmware bank must have the same number of images as per 1223 the `PSA FW update specification`_. 1224 This flag is used in defining the firmware update metadata structure. This 1225 flag is by default set to '1'. 1226 1227- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1228 `PSA FW update specification`_. The default value is 0, and this is an 1229 experimental feature. 1230 PSA firmware update implementation has some limitations, such as BL2 is 1231 not part of the protocol-updatable images, if BL2 needs to be updated, then 1232 it should be done through another platform-defined mechanism, and it assumes 1233 that the platform's hardware supports CRC32 instructions. 1234 1235-------------- 1236 1237*Copyright (c) 2019-2023, Arm Limited. All rights reserved.* 1238 1239.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1240.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/ 1241.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1242.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1243.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1244