1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. External 27 memory-mapped debug accesses are unaffected by this control. 28 The default value is 1 for all platforms. 29 30- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 31 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 32 ``aarch64``. 33 34- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 35 one or more feature modifiers. This option has the form ``[no]feature+...`` 36 and defaults to ``none``. It translates into compiler option 37 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 38 list of supported feature modifiers. 39 40- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 41 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 42 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 43 :ref:`Firmware Design`. 44 45- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 46 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 47 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 48 49- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded 50 SP nodes in tb_fw_config. 51 52- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the 53 SPMC Core manifest. Valid when ``SPD=spmd`` is selected. 54 55- ``BL2``: This is an optional build option which specifies the path to BL2 56 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 57 built. 58 59- ``BL2U``: This is an optional build option which specifies the path to 60 BL2U image. In this case, the BL2U in TF-A will not be built. 61 62- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 63 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 64 entrypoint) or 1 (CPU reset to BL2 entrypoint). 65 The default value is 0. 66 67- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 68 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 69 true in a 4-world system where RESET_TO_BL2 is 0. 70 71- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 72 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 73 74- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 75 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 76 the RW sections in RAM, while leaving the RO sections in place. This option 77 enable this use-case. For now, this option is only supported 78 when RESET_TO_BL2 is set to '1'. 79 80- ``BL31``: This is an optional build option which specifies the path to 81 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 82 be built. 83 84- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 85 file that contains the BL31 private key in PEM format or a PKCS11 URI. If 86 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 87 88- ``BL32``: This is an optional build option which specifies the path to 89 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 90 be built. 91 92- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 93 Trusted OS Extra1 image for the ``fip`` target. 94 95- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 96 Trusted OS Extra2 image for the ``fip`` target. 97 98- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 99 file that contains the BL32 private key in PEM format or a PKCS11 URI. If 100 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 101 102- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 103 ``fip`` target in case TF-A BL2 is used. 104 105- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 106 file that contains the BL33 private key in PEM format or a PKCS11 URI. If 107 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 108 109- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 110 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 111 If enabled, it is needed to use a compiler that supports the option 112 ``-mbranch-protection``. Selects the branch protection features to use: 113- 0: Default value turns off all types of branch protection 114- 1: Enables all types of branch protection features 115- 2: Return address signing to its standard level 116- 3: Extend the signing to include leaf functions 117- 4: Turn on branch target identification mechanism 118 119 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 120 and resulting PAuth/BTI features. 121 122 +-------+--------------+-------+-----+ 123 | Value | GCC option | PAuth | BTI | 124 +=======+==============+=======+=====+ 125 | 0 | none | N | N | 126 +-------+--------------+-------+-----+ 127 | 1 | standard | Y | Y | 128 +-------+--------------+-------+-----+ 129 | 2 | pac-ret | Y | N | 130 +-------+--------------+-------+-----+ 131 | 3 | pac-ret+leaf | Y | N | 132 +-------+--------------+-------+-----+ 133 | 4 | bti | N | Y | 134 +-------+--------------+-------+-----+ 135 136 This option defaults to 0. 137 Note that Pointer Authentication is enabled for Non-secure world 138 irrespective of the value of this option if the CPU supports it. 139 140- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 141 compilation of each build. It must be set to a C string (including quotes 142 where applicable). Defaults to a string that contains the time and date of 143 the compilation. 144 145- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 146 build to be uniquely identified. Defaults to the current git commit id. 147 148- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 149 150- ``CFLAGS``: Extra user options appended on the compiler's command line in 151 addition to the options set by the build system. 152 153- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 154 release several CPUs out of reset. It can take either 0 (several CPUs may be 155 brought up) or 1 (only one CPU will ever be brought up during cold reset). 156 Default is 0. If the platform always brings up a single CPU, there is no 157 need to distinguish between primary and secondary CPUs and the boot path can 158 be optimised. The ``plat_is_my_cpu_primary()`` and 159 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 160 to be implemented in this case. 161 162- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 163 Defaults to ``tbbr``. 164 165- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 166 register state when an unexpected exception occurs during execution of 167 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 168 this is only enabled for a debug build of the firmware. 169 170- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 171 certificate generation tool to create new keys in case no valid keys are 172 present or specified. Allowed options are '0' or '1'. Default is '1'. 173 174- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 175 the AArch32 system registers to be included when saving and restoring the 176 CPU context. The option must be set to 0 for AArch64-only platforms (that 177 is on hardware that does not implement AArch32, or at least not at EL1 and 178 higher ELs). Default value is 1. 179 180- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 181 registers to be included when saving and restoring the CPU context. Default 182 is 0. 183 184- ``CTX_INCLUDE_MPAM_REGS``: Boolean option that, when set to 1, will cause the 185 Memory System Resource Partitioning and Monitoring (MPAM) 186 registers to be included when saving and restoring the CPU context. 187 Default is '0'. 188 189- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 190 registers to be saved/restored when entering/exiting an EL2 execution 191 context. This flag can take values 0 to 2, to align with the 192 ``ENABLE_FEAT`` mechanism. Default value is 0. 193 194- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 195 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 196 to be included when saving and restoring the CPU context as part of world 197 switch. This flag can take values 0 to 2, to align with ``ENABLE_FEAT`` 198 mechanism. Default value is 0. 199 200 Note that Pointer Authentication is enabled for Non-secure world irrespective 201 of the value of this flag if the CPU supports it. 202 203- ``DEBUG``: Chooses between a debug and release build. It can take either 0 204 (release) or 1 (debug) as values. 0 is the default. 205 206- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 207 authenticated decryption algorithm to be used to decrypt firmware/s during 208 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 209 this flag is ``none`` to disable firmware decryption which is an optional 210 feature as per TBBR. 211 212- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 213 of the binary image. If set to 1, then only the ELF image is built. 214 0 is the default. 215 216- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded 217 PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards. 218 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 219 mechanism. Default is ``0``. 220 221- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 222 Board Boot authentication at runtime. This option is meant to be enabled only 223 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 224 flag has to be enabled. 0 is the default. 225 226- ``E``: Boolean option to make warnings into errors. Default is 1. 227 228 When specifying higher warnings levels (``W=1`` and higher), this option 229 defaults to 0. This is done to encourage contributors to use them, as they 230 are expected to produce warnings that would otherwise fail the build. New 231 contributions are still expected to build with ``W=0`` and ``E=1`` (the 232 default). 233 234- ``EARLY_CONSOLE``: This option is used to enable early traces before default 235 console is properly setup. It introduces EARLY_* traces macros, that will 236 use the non-EARLY traces macros if the flag is enabled, or do nothing 237 otherwise. To use this feature, platforms will have to create the function 238 plat_setup_early_console(). 239 Default is 0 (disabled) 240 241- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 242 the normal boot flow. It must specify the entry point address of the EL3 243 payload. Please refer to the "Booting an EL3 payload" section for more 244 details. 245 246- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 247 (also known as group 1 counters). These are implementation-defined counters, 248 and as such require additional platform configuration. Default is 0. 249 250- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which 251 allows platforms with auxiliary counters to describe them via the 252 ``HW_CONFIG`` device tree blob. Default is 0. 253 254- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 255 are compiled out. For debug builds, this option defaults to 1, and calls to 256 ``assert()`` are left in place. For release builds, this option defaults to 0 257 and calls to ``assert()`` function are compiled out. This option can be set 258 independently of ``DEBUG``. It can also be used to hide any auxiliary code 259 that is only required for the assertion and does not fit in the assertion 260 itself. 261 262- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 263 dumps or not. It is supported in both AArch64 and AArch32. However, in 264 AArch32 the format of the frame records are not defined in the AAPCS and they 265 are defined by the implementation. This implementation of backtrace only 266 supports the format used by GCC when T32 interworking is disabled. For this 267 reason enabling this option in AArch32 will force the compiler to only 268 generate A32 code. This option is enabled by default only in AArch64 debug 269 builds, but this behaviour can be overridden in each platform's Makefile or 270 in the build command line. 271 272- ``ENABLE_FEAT`` 273 The Arm architecture defines several architecture extension features, 274 named FEAT_xxx in the architecure manual. Some of those features require 275 setup code in higher exception levels, other features might be used by TF-A 276 code itself. 277 Most of the feature flags defined in the TF-A build system permit to take 278 the values 0, 1 or 2, with the following meaning: 279 280 :: 281 282 ENABLE_FEAT_* = 0: Feature is disabled statically at compile time. 283 ENABLE_FEAT_* = 1: Feature is enabled unconditionally at compile time. 284 ENABLE_FEAT_* = 2: Feature is enabled, but checked at runtime. 285 286 When setting the flag to 0, the feature is disabled during compilation, 287 and the compiler's optimisation stage and the linker will try to remove 288 as much of this code as possible. 289 If it is defined to 1, the code will use the feature unconditionally, so the 290 CPU is expected to support that feature. The FEATURE_DETECTION debug 291 feature, if enabled, will verify this. 292 If the feature flag is set to 2, support for the feature will be compiled 293 in, but its existence will be checked at runtime, so it works on CPUs with 294 or without the feature. This is mostly useful for platforms which either 295 support multiple different CPUs, or where the CPU is configured at runtime, 296 like in emulators. 297 298- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 299 extensions. This flag can take the values 0 to 2, to align with the 300 ``ENABLE_FEAT`` mechanism. This is an optional architectural feature 301 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 302 and this option can be used to enable this feature on those systems as well. 303 This flag can take the values 0 to 2, the default is 0. 304 305- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 306 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 307 onwards. This flag can take the values 0 to 2, to align with the 308 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 309 310- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 311 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 312 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 313 optional feature available on Arm v8.0 onwards. This flag can take values 314 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 315 Default value is ``0``. 316 317- ``ENABLE_FEAT_CSV2_3``: Numeric value to enable support for ``FEAT_CSV2_3`` 318 extension. This feature is supported in AArch64 state only and is an optional 319 feature available in Arm v8.0 implementations. 320 ``FEAT_CSV2_3`` implies the implementation of ``FEAT_CSV2_2``. 321 The flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 322 mechanism. Default value is ``0``. 323 324- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 325 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 326 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 327 and upwards. This flag can take the values 0 to 2, to align with the 328 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 329 330- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 331 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 332 Physical Offset register) during EL2 to EL3 context save/restore operations. 333 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 334 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 335 mechanism. Default value is ``0``. 336 337- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 338 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 339 Read Trap Register) during EL2 to EL3 context save/restore operations. 340 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 341 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 342 mechanism. Default value is ``0``. 343 344- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 345 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 346 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 347 mandatory architectural feature and is enabled from v8.7 and upwards. This 348 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 349 mechanism. Default value is ``0``. 350 351- ``ENABLE_FEAT_MTE2``: Numeric value to enable Memory Tagging Extension2 352 if the platform wants to use this feature and MTE2 is enabled at ELX. 353 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 354 mechanism. Default value is ``0``. 355 356- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 357 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 358 permission fault for any privileged data access from EL1/EL2 to virtual 359 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 360 mandatory architectural feature and is enabled from v8.1 and upwards. This 361 flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 362 mechanism. Default value is ``0``. 363 364- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 365 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 366 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 367 mechanism. Default value is ``0``. 368 369- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 370 extension. This feature is only supported in AArch64 state. This flag can 371 take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 372 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 373 Armv8.5 onwards. 374 375- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB`` 376 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 377 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 378 later CPUs. It is enabled from v8.5 and upwards and if needed can be 379 overidden from platforms explicitly. 380 381- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 382 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 383 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 384 mechanism. Default is ``0``. 385 386- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 387 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 388 available on Arm v8.6. This flag can take values 0 to 2, to align with the 389 ``ENABLE_FEAT`` mechanism. Default is ``0``. 390 391 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 392 delayed by the amount of value in ``TWED_DELAY``. 393 394- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 395 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 396 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 397 architectural feature and is enabled from v8.1 and upwards. It can take 398 values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 399 Default value is ``0``. 400 401- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 402 allow access to TCR2_EL2 (extended translation control) from EL2 as 403 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 404 mandatory architectural feature and is enabled from v8.9 and upwards. This 405 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 406 mechanism. Default value is ``0``. 407 408- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 409 at EL2 and below, and context switch relevant registers. This flag 410 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 411 mechanism. Default value is ``0``. 412 413- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 414 at EL2 and below, and context switch relevant registers. This flag 415 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 416 mechanism. Default value is ``0``. 417 418- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 419 at EL2 and below, and context switch relevant registers. This flag 420 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 421 mechanism. Default value is ``0``. 422 423- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 424 at EL2 and below, and context switch relevant registers. This flag 425 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 426 mechanism. Default value is ``0``. 427 428- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to 429 allow use of Guarded Control Stack from EL2 as well as adding the GCS 430 registers to the EL2 context save/restore operations. This flag can take 431 the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 432 Default value is ``0``. 433 434- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 435 support in GCC for TF-A. This option is currently only supported for 436 AArch64. Default is 0. 437 438- ``ENABLE_FEAT_MPAM``: Numeric value to enable lower ELs to use MPAM 439 feature. MPAM is an optional Armv8.4 extension that enables various memory 440 system components and resources to define partitions; software running at 441 various ELs can assign themselves to desired partition to control their 442 performance aspects. 443 444 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 445 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 446 access their own MPAM registers without trapping into EL3. This option 447 doesn't make use of partitioning in EL3, however. Platform initialisation 448 code should configure and use partitions in EL3 as required. This option 449 defaults to ``2`` since MPAM is enabled by default for NS world only. 450 The flag is automatically disabled when the target 451 architecture is AArch32. 452 453- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 454 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 455 firmware to detect and limit high activity events to assist in SoC processor 456 power domain dynamic power budgeting and limit the triggering of whole-rail 457 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 458 459- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which 460 allows platforms with cores supporting MPMM to describe them via the 461 ``HW_CONFIG`` device tree blob. Default is 0. 462 463- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 464 support within generic code in TF-A. This option is currently only supported 465 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 466 in BL32 (SP_min) for AARCH32. Default is 0. 467 468- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 469 Measurement Framework(PMF). Default is 0. 470 471- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 472 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 473 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 474 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 475 software. 476 477- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 478 instrumentation which injects timestamp collection points into TF-A to 479 allow runtime performance to be measured. Currently, only PSCI is 480 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 481 as well. Default is 0. 482 483- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 484 extensions. This is an optional architectural feature for AArch64. 485 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 486 mechanism. The default is 2 but is automatically disabled when the target 487 architecture is AArch32. 488 489- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 490 (SVE) for the Non-secure world only. SVE is an optional architectural feature 491 for AArch64. Note that when SVE is enabled for the Non-secure world, access 492 to SIMD and floating-point functionality from the Secure world is disabled by 493 default and controlled with ENABLE_SVE_FOR_SWD. 494 This is to avoid corruption of the Non-secure world data in the Z-registers 495 which are aliased by the SIMD and FP registers. The build option is not 496 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 497 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` 498 enabled. This flag can take the values 0 to 2, to align with the 499 ``ENABLE_FEAT`` mechanism. At this time, this build option cannot be 500 used on systems that have SPM_MM enabled. The default is 1. 501 502- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. 503 SVE is an optional architectural feature for AArch64. Note that this option 504 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is 505 automatically disabled when the target architecture is AArch32. 506 507- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 508 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 509 default value is set to "none". "strong" is the recommended stack protection 510 level if this feature is desired. "none" disables the stack protection. For 511 all values other than "none", the ``plat_get_stack_protector_canary()`` 512 platform hook needs to be implemented. The value is passed as the last 513 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 514 515- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 516 flag depends on ``DECRYPTION_SUPPORT`` build flag. 517 518- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 519 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 520 521- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 522 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 523 on ``DECRYPTION_SUPPORT`` build flag. 524 525- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 526 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 527 build flag. 528 529- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 530 deprecated platform APIs, helper functions or drivers within Trusted 531 Firmware as error. It can take the value 1 (flag the use of deprecated 532 APIs as error) or 0. The default is 0. 533 534- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can 535 configure an Arm® Ethos™-N NPU. To use this service the target platform's 536 ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only 537 the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform 538 only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. 539 540- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the 541 Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and 542 ``TRUSTED_BOARD_BOOT`` to be enabled. 543 544- ``ETHOSN_NPU_FW``: location of the NPU firmware binary 545 (```ethosn.bin```). This firmware image will be included in the FIP and 546 loaded at runtime. 547 548- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 549 targeted at EL3. When set ``0`` (default), no exceptions are expected or 550 handled at EL3, and a panic will result. The exception to this rule is when 551 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 552 occuring during normal world execution, are trapped to EL3. Any exception 553 trapped during secure world execution are trapped to the SPMC. This is 554 supported only for AArch64 builds. 555 556- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 557 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 558 Default value is 40 (LOG_LEVEL_INFO). 559 560- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 561 injection from lower ELs, and this build option enables lower ELs to use 562 Error Records accessed via System Registers to inject faults. This is 563 applicable only to AArch64 builds. 564 565 This feature is intended for testing purposes only, and is advisable to keep 566 disabled for production images. 567 568- ``FIP_NAME``: This is an optional build option which specifies the FIP 569 filename for the ``fip`` target. Default is ``fip.bin``. 570 571- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 572 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 573 574- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 575 576 :: 577 578 0: Encryption is done with Secret Symmetric Key (SSK) which is common 579 for a class of devices. 580 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 581 unique per device. 582 583 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 584 585- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 586 tool to create certificates as per the Chain of Trust described in 587 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 588 include the certificates in the FIP and FWU_FIP. Default value is '0'. 589 590 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 591 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 592 the corresponding certificates, and to include those certificates in the 593 FIP and FWU_FIP. 594 595 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 596 images will not include support for Trusted Board Boot. The FIP will still 597 include the corresponding certificates. This FIP can be used to verify the 598 Chain of Trust on the host machine through other mechanisms. 599 600 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 601 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 602 will not include the corresponding certificates, causing a boot failure. 603 604- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 605 inherent support for specific EL3 type interrupts. Setting this build option 606 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 607 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 608 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 609 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 610 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 611 the Secure Payload interrupts needs to be synchronously handed over to Secure 612 EL1 for handling. The default value of this option is ``0``, which means the 613 Group 0 interrupts are assumed to be handled by Secure EL1. 614 615- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 616 Interrupts, resulting from errors in NS world, will be always trapped in 617 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 618 will be trapped in the current exception level (or in EL1 if the current 619 exception level is EL0). 620 621- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 622 software operations are required for CPUs to enter and exit coherency. 623 However, newer systems exist where CPUs' entry to and exit from coherency 624 is managed in hardware. Such systems require software to only initiate these 625 operations, and the rest is managed in hardware, minimizing active software 626 management. In such systems, this boolean option enables TF-A to carry out 627 build and run-time optimizations during boot and power management operations. 628 This option defaults to 0 and if it is enabled, then it implies 629 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 630 631 If this flag is disabled while the platform which TF-A is compiled for 632 includes cores that manage coherency in hardware, then a compilation error is 633 generated. This is based on the fact that a system cannot have, at the same 634 time, cores that manage coherency in hardware and cores that don't. In other 635 words, a platform cannot have, at the same time, cores that require 636 ``HW_ASSISTED_COHERENCY=1`` and cores that require 637 ``HW_ASSISTED_COHERENCY=0``. 638 639 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 640 translation library (xlat tables v2) must be used; version 1 of translation 641 library is not supported. 642 643- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for 644 implementation defined system register accesses from lower ELs. Default 645 value is ``0``. 646 647- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 648 bottom, higher addresses at the top. This build flag can be set to '1' to 649 invert this behavior. Lower addresses will be printed at the top and higher 650 addresses at the bottom. 651 652- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 653 used for generating the PKCS keys and subsequent signing of the certificate. 654 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 655 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 656 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 657 compatibility. The default value of this flag is ``rsa`` which is the TBBR 658 compliant PKCS#1 RSA 2.1 scheme. 659 660- ``KEY_SIZE``: This build flag enables the user to select the key size for 661 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 662 depend on the chosen algorithm and the cryptographic module. 663 664 +---------------------------+------------------------------------+ 665 | KEY_ALG | Possible key sizes | 666 +===========================+====================================+ 667 | rsa | 1024 , 2048 (default), 3072, 4096 | 668 +---------------------------+------------------------------------+ 669 | ecdsa | 256 (default), 384 | 670 +---------------------------+------------------------------------+ 671 | ecdsa-brainpool-regular | unavailable | 672 +---------------------------+------------------------------------+ 673 | ecdsa-brainpool-twisted | unavailable | 674 +---------------------------+------------------------------------+ 675 676- ``HASH_ALG``: This build flag enables the user to select the secure hash 677 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 678 The default value of this flag is ``sha256``. 679 680- ``LDFLAGS``: Extra user options appended to the linkers' command line in 681 addition to the one set by the build system. 682 683- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 684 output compiled into the build. This should be one of the following: 685 686 :: 687 688 0 (LOG_LEVEL_NONE) 689 10 (LOG_LEVEL_ERROR) 690 20 (LOG_LEVEL_NOTICE) 691 30 (LOG_LEVEL_WARNING) 692 40 (LOG_LEVEL_INFO) 693 50 (LOG_LEVEL_VERBOSE) 694 695 All log output up to and including the selected log level is compiled into 696 the build. The default value is 40 in debug builds and 20 in release builds. 697 698- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 699 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 700 provide trust that the code taking the measurements and recording them has 701 not been tampered with. 702 703 This option defaults to 0. 704 705- ``DICE_PROTECTION_ENVIRONMENT``: Boolean flag to specify the measured boot 706 backend when ``MEASURED_BOOT`` is enabled. The default value is ``0``. When 707 set to ``1`` then measurements and additional metadata collected during the 708 measured boot process are sent to the DICE Protection Environment for storage 709 and processing. A certificate chain, which represents the boot state of the 710 device, can be queried from the DPE. 711 712- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build 713 options to the compiler. An example usage: 714 715 .. code:: make 716 717 MARCH_DIRECTIVE := -march=armv8.5-a 718 719- ``HARDEN_SLS``: used to pass -mharden-sls=all from the TF-A build 720 options to the compiler currently supporting only of the options. 721 GCC documentation: 722 https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mharden-sls 723 724 An example usage: 725 726 .. code:: make 727 728 HARDEN_SLS := 1 729 730 This option defaults to 0. 731 732- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 733 specifies a file that contains the Non-Trusted World private key in PEM 734 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and it 735 will be used to save the key. 736 737- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 738 optional. It is only needed if the platform makefile specifies that it 739 is required in order to build the ``fwu_fip`` target. 740 741- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 742 contents upon world switch. It can take either 0 (don't save and restore) or 743 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 744 wants the timer registers to be saved and restored. 745 746- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 747 for the BL image. It can be either 0 (include) or 1 (remove). The default 748 value is 0. 749 750- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 751 the underlying hardware is not a full PL011 UART but a minimally compliant 752 generic UART, which is a subset of the PL011. The driver will not access 753 any register that is not part of the SBSA generic UART specification. 754 Default value is 0 (a full PL011 compliant UART is present). 755 756- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 757 must be subdirectory of any depth under ``plat/``, and must contain a 758 platform makefile named ``platform.mk``. For example, to build TF-A for the 759 Arm Juno board, select PLAT=juno. 760 761- ``PLATFORM_REPORT_CTX_MEM_USE``: Reports the context memory allocated for 762 each core as well as the global context. The data includes the memory used 763 by each world and each privileged exception level. This build option is 764 applicable only for ``ARCH=aarch64`` builds. The default value is 0. 765 766- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 767 instead of the normal boot flow. When defined, it must specify the entry 768 point address for the preloaded BL33 image. This option is incompatible with 769 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 770 over ``PRELOADED_BL33_BASE``. 771 772- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 773 vector address can be programmed or is fixed on the platform. It can take 774 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 775 programmable reset address, it is expected that a CPU will start executing 776 code directly at the right address, both on a cold and warm reset. In this 777 case, there is no need to identify the entrypoint on boot and the boot path 778 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 779 does not need to be implemented in this case. 780 781- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 782 possible for the PSCI power-state parameter: original and extended State-ID 783 formats. This flag if set to 1, configures the generic PSCI layer to use the 784 extended format. The default value of this flag is 0, which means by default 785 the original power-state format is used by the PSCI implementation. This flag 786 should be specified by the platform makefile and it governs the return value 787 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 788 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 789 set to 1 as well. 790 791- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 792 OS-initiated mode. This option defaults to 0. 793 794- ``ENABLE_FEAT_RAS``: Boolean flag to enable Armv8.2 RAS features. RAS features 795 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 796 or later CPUs. This flag can take the values 0 or 1. The default value is 0. 797 NOTE: This flag enables use of IESB capability to reduce entry latency into 798 EL3 even when RAS error handling is not performed on the platform. Hence this 799 flag is recommended to be turned on Armv8.2 and later CPUs. 800 801- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 802 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 803 entrypoint) or 1 (CPU reset to BL31 entrypoint). 804 The default value is 0. 805 806- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 807 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 808 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 809 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 810 811- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 812 file that contains the ROT private key in PEM format or a PKCS11 URI and 813 enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is 814 accepted and it will be used to save the key. 815 816- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 817 certificate generation tool to save the keys used to establish the Chain of 818 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 819 820- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 821 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 822 target. 823 824- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 825 file that contains the SCP_BL2 private key in PEM format or a PKCS11 URI. 826 If ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 827 828- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 829 optional. It is only needed if the platform makefile specifies that it 830 is required in order to build the ``fwu_fip`` target. 831 832- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 833 Delegated Exception Interface to BL31 image. This defaults to ``0``. 834 835 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 836 set to ``1``. 837 838- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 839 isolated on separate memory pages. This is a trade-off between security and 840 memory usage. See "Isolating code and read-only data on separate memory 841 pages" section in :ref:`Firmware Design`. This flag is disabled by default 842 and affects all BL images. 843 844- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 845 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 846 allocated in RAM discontiguous from the loaded firmware image. When set, the 847 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 848 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 849 sections are placed in RAM immediately following the loaded firmware image. 850 851- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 852 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 853 discontiguous from loaded firmware images. When set, the platform need to 854 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 855 flag is disabled by default and NOLOAD sections are placed in RAM immediately 856 following the loaded firmware image. 857 858- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 859 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 860 UEFI+ACPI this can provide a certain amount of OS forward compatibility 861 with newer platforms that aren't ECAM compliant. 862 863- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 864 This build option is only valid if ``ARCH=aarch64``. The value should be 865 the path to the directory containing the SPD source, relative to 866 ``services/spd/``; the directory is expected to contain a makefile called 867 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 868 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 869 cannot be enabled when the ``SPM_MM`` option is enabled. 870 871- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 872 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 873 execution in BL1 just before handing over to BL31. At this point, all 874 firmware images have been loaded in memory, and the MMU and caches are 875 turned off. Refer to the "Debugging options" section for more details. 876 877- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 878 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 879 component runs at the EL3 exception level. The default value is ``0`` ( 880 disabled). This configuration supports pre-Armv8.4 platforms (aka not 881 implementing the ``FEAT_SEL2`` extension). 882 883- ``SPMC_AT_EL3_SEL0_SP`` : Boolean option to enable SEL0 SP load support when 884 ``SPMC_AT_EL3`` is enabled. The default value if ``0`` (disabled). This 885 option cannot be enabled (``1``) when (``SPMC_AT_EL3``) is disabled. 886 887- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 888 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 889 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 890 mechanism should be used. 891 892- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 893 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 894 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 895 extension. This is the default when enabling the SPM Dispatcher. When 896 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 897 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 898 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 899 extension). 900 901- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 902 Partition Manager (SPM) implementation. The default value is ``0`` 903 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 904 enabled (``SPD=spmd``). 905 906- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 907 description of secure partitions. The build system will parse this file and 908 package all secure partition blobs into the FIP. This file is not 909 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 910 911- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 912 secure interrupts (caught through the FIQ line). Platforms can enable 913 this directive if they need to handle such interruption. When enabled, 914 the FIQ are handled in monitor mode and non secure world is not allowed 915 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 916 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 917 918- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 919 Platforms can configure this if they need to lower the hardware 920 limit, for example due to asymmetric configuration or limitations of 921 software run at lower ELs. The default is the architectural maximum 922 of 2048 which should be suitable for most configurations, the 923 hardware will limit the effective VL to the maximum physically supported 924 VL. 925 926- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 927 Random Number Generator Interface to BL31 image. This defaults to ``0``. 928 929- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 930 Boot feature. When set to '1', BL1 and BL2 images include support to load 931 and verify the certificates and images in a FIP, and BL1 includes support 932 for the Firmware Update. The default value is '0'. Generation and inclusion 933 of certificates in the FIP and FWU_FIP depends upon the value of the 934 ``GENERATE_COT`` option. 935 936 .. warning:: 937 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 938 already exist in disk, they will be overwritten without further notice. 939 940- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 941 specifies a file that contains the Trusted World private key in PEM 942 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and 943 it will be used to save the key. 944 945- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 946 synchronous, (see "Initializing a BL32 Image" section in 947 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 948 synchronous method) or 1 (BL32 is initialized using asynchronous method). 949 Default is 0. 950 951- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 952 routing model which routes non-secure interrupts asynchronously from TSP 953 to EL3 causing immediate preemption of TSP. The EL3 is responsible 954 for saving and restoring the TSP context in this routing model. The 955 default routing model (when the value is 0) is to route non-secure 956 interrupts to TSP allowing it to save its context and hand over 957 synchronously to EL3 via an SMC. 958 959 .. note:: 960 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 961 must also be set to ``1``. 962 963- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and 964 internal-trusted-storage) as SP in tb_fw_config device tree. 965 966- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 967 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 968 this delay. It can take values in the range (0-15). Default value is ``0`` 969 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 970 Platforms need to explicitly update this value based on their requirements. 971 972- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 973 linker. When the ``LINKER`` build variable points to the armlink linker, 974 this flag is enabled automatically. To enable support for armlink, platforms 975 will have to provide a scatter file for the BL image. Currently, Tegra 976 platforms use the armlink support to compile BL3-1 images. 977 978- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 979 memory region in the BL memory map or not (see "Use of Coherent memory in 980 TF-A" section in :ref:`Firmware Design`). It can take the value 1 981 (Coherent memory region is included) or 0 (Coherent memory region is 982 excluded). Default is 1. 983 984- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 985 firmware configuration framework. This will move the io_policies into a 986 configuration device tree, instead of static structure in the code base. 987 988- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 989 at runtime using fconf. If this flag is enabled, COT descriptors are 990 statically captured in tb_fw_config file in the form of device tree nodes 991 and properties. Currently, COT descriptors used by BL2 are moved to the 992 device tree and COT descriptors used by BL1 are retained in the code 993 base statically. 994 995- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 996 runtime using firmware configuration framework. The platform specific SDEI 997 shared and private events configuration is retrieved from device tree rather 998 than static C structures at compile time. This is only supported if 999 SDEI_SUPPORT build flag is enabled. 1000 1001- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 1002 and Group1 secure interrupts using the firmware configuration framework. The 1003 platform specific secure interrupt property descriptor is retrieved from 1004 device tree in runtime rather than depending on static C structure at compile 1005 time. 1006 1007- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 1008 This feature creates a library of functions to be placed in ROM and thus 1009 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 1010 is 0. 1011 1012- ``V``: Verbose build. If assigned anything other than 0, the build commands 1013 are printed. Default is 0. 1014 1015- ``VERSION_STRING``: String used in the log output for each TF-A image. 1016 Defaults to a string formed by concatenating the version number, build type 1017 and build string. 1018 1019- ``W``: Warning level. Some compiler warning options of interest have been 1020 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 1021 each level enabling more warning options. Default is 0. 1022 1023 This option is closely related to the ``E`` option, which enables 1024 ``-Werror``. 1025 1026 - ``W=0`` (default) 1027 1028 Enables a wide assortment of warnings, most notably ``-Wall`` and 1029 ``-Wextra``, as well as various bad practices and things that are likely to 1030 result in errors. Includes some compiler specific flags. No warnings are 1031 expected at this level for any build. 1032 1033 - ``W=1`` 1034 1035 Enables warnings we want the generic build to include but are too time 1036 consuming to fix at the moment. It re-enables warnings taken out for 1037 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1038 to eventually be merged into ``W=0``. Some warnings are expected on some 1039 builds, but new contributions should not introduce new ones. 1040 1041 - ``W=2`` (recommended) 1042 1043 Enables warnings we want the generic build to include but cannot be enabled 1044 due to external libraries. This level is expected to eventually be merged 1045 into ``W=0``. Lots of warnings are expected, primarily from external 1046 libraries like zlib and compiler-rt, but new controbutions should not 1047 introduce new ones. 1048 1049 - ``W=3`` 1050 1051 Enables warnings that are informative but not necessary and generally too 1052 verbose and frequently ignored. A very large number of warnings are 1053 expected. 1054 1055 The exact set of warning flags depends on the compiler and TF-A warning 1056 level, however they are all succinctly set in the top-level Makefile. Please 1057 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1058 individual flags. 1059 1060- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1061 the CPU after warm boot. This is applicable for platforms which do not 1062 require interconnect programming to enable cache coherency (eg: single 1063 cluster platforms). If this option is enabled, then warm boot path 1064 enables D-caches immediately after enabling MMU. This option defaults to 0. 1065 1066- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 1067 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 1068 default value of this flag is ``no``. Note this option must be enabled only 1069 for ARM architecture greater than Armv8.5-A. 1070 1071- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1072 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1073 The default value of this flag is ``0``. 1074 1075 ``AT`` speculative errata workaround disables stage1 page table walk for 1076 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1077 produces either the correct result or failure without TLB allocation. 1078 1079 This boolean option enables errata for all below CPUs. 1080 1081 +---------+--------------+-------------------------+ 1082 | Errata | CPU | Workaround Define | 1083 +=========+==============+=========================+ 1084 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1085 +---------+--------------+-------------------------+ 1086 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1087 +---------+--------------+-------------------------+ 1088 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1089 +---------+--------------+-------------------------+ 1090 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1091 +---------+--------------+-------------------------+ 1092 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1093 +---------+--------------+-------------------------+ 1094 1095 .. note:: 1096 This option is enabled by build only if platform sets any of above defines 1097 mentioned in ’Workaround Define' column in the table. 1098 If this option is enabled for the EL3 software then EL2 software also must 1099 implement this workaround due to the behaviour of the errata mentioned 1100 in new SDEN document which will get published soon. 1101 1102- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1103 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1104 This flag is disabled by default. 1105 1106- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1107 host machine where a custom installation of OpenSSL is located, which is used 1108 to build the certificate generation, firmware encryption and FIP tools. If 1109 this option is not set, the default OS installation will be used. 1110 1111- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1112 functions that wait for an arbitrary time length (udelay and mdelay). The 1113 default value is 0. 1114 1115- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1116 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1117 optional architectural feature for AArch64. This flag can take the values 1118 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0 1119 and it is automatically disabled when the target architecture is AArch32. 1120 1121- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1122 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1123 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1124 feature for AArch64. This flag can take the values 0 to 2, to align with the 1125 ``ENABLE_FEAT`` mechanism. The default is 0 and it is automatically 1126 disabled when the target architecture is AArch32. 1127 1128- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1129 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1130 but unused). This feature is available if trace unit such as ETMv4.x, and 1131 ETE(extending ETM feature) is implemented. This flag can take the values 1132 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0. 1133 1134- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1135 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1136 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1137 with the ``ENABLE_FEAT`` mechanism. This flag is disabled by default. 1138 1139- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1140 ``plat_can_cmo`` which will return zero if cache management operations should 1141 be skipped and non-zero otherwise. By default, this option is disabled which 1142 means platform hook won't be checked and CMOs will always be performed when 1143 related functions are called. 1144 1145- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management 1146 firmware interface for the BL31 image. By default its disabled (``0``). 1147 1148- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the 1149 errata mitigation for platforms with a non-arm interconnect using the errata 1150 ABI. By default its disabled (``0``). 1151 1152- ``ENABLE_CONSOLE_GETC``: Boolean option to enable `getc()` feature in console 1153 driver(s). By default it is disabled (``0``) because it constitutes an attack 1154 vector into TF-A by potentially allowing an attacker to inject arbitrary data. 1155 This option should only be enabled on a need basis if there is a use case for 1156 reading characters from the console. 1157 1158GICv3 driver options 1159-------------------- 1160 1161GICv3 driver files are included using directive: 1162 1163``include drivers/arm/gic/v3/gicv3.mk`` 1164 1165The driver can be configured with the following options set in the platform 1166makefile: 1167 1168- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1169 Enabling this option will add runtime detection support for the 1170 GIC-600, so is safe to select even for a GIC500 implementation. 1171 This option defaults to 0. 1172 1173- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1174 for GIC-600 AE. Enabling this option will introduce support to initialize 1175 the FMU. Platforms should call the init function during boot to enable the 1176 FMU and its safety mechanisms. This option defaults to 0. 1177 1178- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1179 functionality. This option defaults to 0 1180 1181- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1182 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1183 functions. This is required for FVP platform which need to simulate GIC save 1184 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1185 1186- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1187 This option defaults to 0. 1188 1189- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1190 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1191 1192Debugging options 1193----------------- 1194 1195To compile a debug version and make the build more verbose use 1196 1197.. code:: shell 1198 1199 make PLAT=<platform> DEBUG=1 V=1 all 1200 1201AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1202(for example Arm-DS) might not support this and may need an older version of 1203DWARF symbols to be emitted by GCC. This can be achieved by using the 1204``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1205the version to 4 is recommended for Arm-DS. 1206 1207When debugging logic problems it might also be useful to disable all compiler 1208optimizations by using ``-O0``. 1209 1210.. warning:: 1211 Using ``-O0`` could cause output images to be larger and base addresses 1212 might need to be recalculated (see the **Memory layout on Arm development 1213 platforms** section in the :ref:`Firmware Design`). 1214 1215Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1216``LDFLAGS``: 1217 1218.. code:: shell 1219 1220 CFLAGS='-O0 -gdwarf-2' \ 1221 make PLAT=<platform> DEBUG=1 V=1 all 1222 1223Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1224ignored as the linker is called directly. 1225 1226It is also possible to introduce an infinite loop to help in debugging the 1227post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1228``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1229section. In this case, the developer may take control of the target using a 1230debugger when indicated by the console output. When using Arm-DS, the following 1231commands can be used: 1232 1233:: 1234 1235 # Stop target execution 1236 interrupt 1237 1238 # 1239 # Prepare your debugging environment, e.g. set breakpoints 1240 # 1241 1242 # Jump over the debug loop 1243 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1244 1245 # Resume execution 1246 continue 1247 1248.. _build_options_experimental: 1249 1250Experimental build options 1251--------------------------- 1252 1253Common build options 1254~~~~~~~~~~~~~~~~~~~~ 1255 1256- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 1257 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 1258 the measurements and recording them as per `PSA DRTM specification`_. For 1259 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 1260 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 1261 should have mechanism to authenticate BL31. This option defaults to 0. 1262 1263- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 1264 Management Extension. This flag can take the values 0 to 2, to align with 1265 the ``ENABLE_FEAT`` mechanism. Default value is 0. 1266 1267- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1268 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 1269 registers so are enabled together. Using this option without 1270 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 1271 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a 1272 superset of SVE. SME is an optional architectural feature for AArch64. 1273 At this time, this build option cannot be used on systems that have 1274 SPD=spmd/SPM_MM and atempting to build with this option will fail. 1275 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 1276 mechanism. Default is 0. 1277 1278- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1279 version 2 (SME2) for the non-secure world only. SME2 is an optional 1280 architectural feature for AArch64. 1281 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME 1282 accesses will still be trapped. This flag can take the values 0 to 2, to 1283 align with the ``ENABLE_FEAT`` mechanism. Default is 0. 1284 1285- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 1286 Extension for secure world. Used along with SVE and FPU/SIMD. 1287 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. 1288 Default is 0. 1289 1290- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM 1291 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support 1292 for logical partitions in EL3, managed by the SPMD as defined in the 1293 FF-A v1.2 specification. This flag is disabled by default. This flag 1294 must not be used if ``SPMC_AT_EL3`` is enabled. 1295 1296- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 1297 verification mechanism. This is a debug feature that compares the 1298 architectural features enabled through the feature specific build flags 1299 (ENABLE_FEAT_xxx) with the features actually available on the CPU running, 1300 and reports any discrepancies. 1301 This flag will also enable errata ordering checking for ``DEBUG`` builds. 1302 1303 It is expected that this feature is only used for flexible platforms like 1304 software emulators, or for hardware platforms at bringup time, to verify 1305 that the configured feature set matches the CPU. 1306 The ``FEATURE_DETECTION`` macro is disabled by default. 1307 1308- ``PSA_CRYPTO``: Boolean option for enabling MbedTLS PSA crypto APIs support. 1309 The platform will use PSA compliant Crypto APIs during authentication and 1310 image measurement process by enabling this option. It uses APIs defined as 1311 per the `PSA Crypto API specification`_. This feature is only supported if 1312 using MbedTLS 3.x version. It is disabled (``0``) by default. 1313 1314- ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware 1315 Handoff using Transfer List defined in `Firmware Handoff specification`_. 1316 This defaults to ``0``. Current implementation follows the Firmware Handoff 1317 specification v0.9. 1318 1319- ``USE_DEBUGFS``: When set to 1 this option exposes a virtual filesystem 1320 interface through BL31 as a SiP SMC function. 1321 Default is disabled (0). 1322 1323Firmware update options 1324~~~~~~~~~~~~~~~~~~~~~~~ 1325 1326- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1327 `PSA FW update specification`_. The default value is 0. 1328 PSA firmware update implementation has few limitations, such as: 1329 1330 - BL2 is not part of the protocol-updatable images. If BL2 needs to 1331 be updated, then it should be done through another platform-defined 1332 mechanism. 1333 1334 - It assumes the platform's hardware supports CRC32 instructions. 1335 1336- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1337 in defining the firmware update metadata structure. This flag is by default 1338 set to '2'. 1339 1340- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1341 firmware bank. Each firmware bank must have the same number of images as per 1342 the `PSA FW update specification`_. 1343 This flag is used in defining the firmware update metadata structure. This 1344 flag is by default set to '1'. 1345 1346- ``PSA_FWU_METADATA_FW_STORE_DESC``: To be enabled when the FWU 1347 metadata contains image description. The default value is 1. 1348 1349 The version 2 of the FWU metadata allows for an opaque metadata 1350 structure where a platform can choose to not include the firmware 1351 store description in the metadata structure. This option indicates 1352 if the firmware store description, which provides information on 1353 the updatable images is part of the structure. 1354 1355-------------- 1356 1357*Copyright (c) 2019-2024, Arm Limited. All rights reserved.* 1358 1359.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1360.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/latest/ 1361.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1362.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1363.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1364.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9 1365.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/ 1366