1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. Reads from the 27 memory mapped view are unaffected by this control. 28 29- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 31 ``aarch64``. 32 33- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 34 one or more feature modifiers. This option has the form ``[no]feature+...`` 35 and defaults to ``none``. It translates into compiler option 36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 37 list of supported feature modifiers. 38 39- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 42 :ref:`Firmware Design`. 43 44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 47 48- ``BL2``: This is an optional build option which specifies the path to BL2 49 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 50 built. 51 52- ``BL2U``: This is an optional build option which specifies the path to 53 BL2U image. In this case, the BL2U in TF-A will not be built. 54 55- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 56 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 57 entrypoint) or 1 (CPU reset to BL2 entrypoint). 58 The default value is 0. 59 60- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 61 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 62 true in a 4-world system where RESET_TO_BL2 is 0. 63 64- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 65 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 66 67- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 68 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 69 the RW sections in RAM, while leaving the RO sections in place. This option 70 enable this use-case. For now, this option is only supported 71 when RESET_TO_BL2 is set to '1'. 72 73- ``BL31``: This is an optional build option which specifies the path to 74 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 75 be built. 76 77- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 78 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, 79 this file name will be used to save the key. 80 81- ``BL32``: This is an optional build option which specifies the path to 82 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 83 be built. 84 85- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 86 Trusted OS Extra1 image for the ``fip`` target. 87 88- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 89 Trusted OS Extra2 image for the ``fip`` target. 90 91- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 92 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, 93 this file name will be used to save the key. 94 95- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 96 ``fip`` target in case TF-A BL2 is used. 97 98- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 99 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, 100 this file name will be used to save the key. 101 102- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 103 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 104 If enabled, it is needed to use a compiler that supports the option 105 ``-mbranch-protection``. Selects the branch protection features to use: 106- 0: Default value turns off all types of branch protection 107- 1: Enables all types of branch protection features 108- 2: Return address signing to its standard level 109- 3: Extend the signing to include leaf functions 110- 4: Turn on branch target identification mechanism 111 112 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 113 and resulting PAuth/BTI features. 114 115 +-------+--------------+-------+-----+ 116 | Value | GCC option | PAuth | BTI | 117 +=======+==============+=======+=====+ 118 | 0 | none | N | N | 119 +-------+--------------+-------+-----+ 120 | 1 | standard | Y | Y | 121 +-------+--------------+-------+-----+ 122 | 2 | pac-ret | Y | N | 123 +-------+--------------+-------+-----+ 124 | 3 | pac-ret+leaf | Y | N | 125 +-------+--------------+-------+-----+ 126 | 4 | bti | N | Y | 127 +-------+--------------+-------+-----+ 128 129 This option defaults to 0. 130 Note that Pointer Authentication is enabled for Non-secure world 131 irrespective of the value of this option if the CPU supports it. 132 133- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 134 compilation of each build. It must be set to a C string (including quotes 135 where applicable). Defaults to a string that contains the time and date of 136 the compilation. 137 138- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 139 build to be uniquely identified. Defaults to the current git commit id. 140 141- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 142 143- ``CFLAGS``: Extra user options appended on the compiler's command line in 144 addition to the options set by the build system. 145 146- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 147 release several CPUs out of reset. It can take either 0 (several CPUs may be 148 brought up) or 1 (only one CPU will ever be brought up during cold reset). 149 Default is 0. If the platform always brings up a single CPU, there is no 150 need to distinguish between primary and secondary CPUs and the boot path can 151 be optimised. The ``plat_is_my_cpu_primary()`` and 152 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 153 to be implemented in this case. 154 155- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 156 Defaults to ``tbbr``. 157 158- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 159 register state when an unexpected exception occurs during execution of 160 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 161 this is only enabled for a debug build of the firmware. 162 163- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 164 certificate generation tool to create new keys in case no valid keys are 165 present or specified. Allowed options are '0' or '1'. Default is '1'. 166 167- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 168 the AArch32 system registers to be included when saving and restoring the 169 CPU context. The option must be set to 0 for AArch64-only platforms (that 170 is on hardware that does not implement AArch32, or at least not at EL1 and 171 higher ELs). Default value is 1. 172 173- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 174 registers to be included when saving and restoring the CPU context. Default 175 is 0. 176 177- ``CTX_INCLUDE_MTE_REGS``: Numeric value to include Memory Tagging Extension 178 registers in cpu context. This must be enabled, if the platform wants to use 179 this feature in the Secure world and MTE is enabled at ELX. This flag can 180 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 181 Default value is 0. 182 183- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 184 registers to be saved/restored when entering/exiting an EL2 execution 185 context. This flag can take values 0 to 2, to align with the 186 ``FEATURE_DETECTION`` mechanism. Default value is 0. 187 188- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 189 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 190 to be included when saving and restoring the CPU context as part of world 191 switch. This flag can take values 0 to 2, to align with ``FEATURE_DETECTION`` 192 mechanism. Default value is 0. 193 194 Note that Pointer Authentication is enabled for Non-secure world irrespective 195 of the value of this flag if the CPU supports it. 196 197- ``DEBUG``: Chooses between a debug and release build. It can take either 0 198 (release) or 1 (debug) as values. 0 is the default. 199 200- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 201 authenticated decryption algorithm to be used to decrypt firmware/s during 202 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 203 this flag is ``none`` to disable firmware decryption which is an optional 204 feature as per TBBR. 205 206- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 207 of the binary image. If set to 1, then only the ELF image is built. 208 0 is the default. 209 210- ``DISABLE_MTPMU``: Boolean option to disable FEAT_MTPMU if implemented 211 (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms 212 that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU, 213 check the latest Arm ARM. 214 215- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 216 Board Boot authentication at runtime. This option is meant to be enabled only 217 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 218 flag has to be enabled. 0 is the default. 219 220- ``E``: Boolean option to make warnings into errors. Default is 1. 221 222 When specifying higher warnings levels (``W=1`` and higher), this option 223 defaults to 0. This is done to encourage contributors to use them, as they 224 are expected to produce warnings that would otherwise fail the build. New 225 contributions are still expected to build with ``W=0`` and ``E=1`` (the 226 default). 227 228- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 229 the normal boot flow. It must specify the entry point address of the EL3 230 payload. Please refer to the "Booting an EL3 payload" section for more 231 details. 232 233- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 234 (also known as group 1 counters). These are implementation-defined counters, 235 and as such require additional platform configuration. Default is 0. 236 237- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which 238 allows platforms with auxiliary counters to describe them via the 239 ``HW_CONFIG`` device tree blob. Default is 0. 240 241- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 242 are compiled out. For debug builds, this option defaults to 1, and calls to 243 ``assert()`` are left in place. For release builds, this option defaults to 0 244 and calls to ``assert()`` function are compiled out. This option can be set 245 independently of ``DEBUG``. It can also be used to hide any auxiliary code 246 that is only required for the assertion and does not fit in the assertion 247 itself. 248 249- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 250 dumps or not. It is supported in both AArch64 and AArch32. However, in 251 AArch32 the format of the frame records are not defined in the AAPCS and they 252 are defined by the implementation. This implementation of backtrace only 253 supports the format used by GCC when T32 interworking is disabled. For this 254 reason enabling this option in AArch32 will force the compiler to only 255 generate A32 code. This option is enabled by default only in AArch64 debug 256 builds, but this behaviour can be overridden in each platform's Makefile or 257 in the build command line. 258 259- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 260 extensions. This flag can take the values 0 to 2, to align with the 261 ``FEATURE_DETECTION`` mechanism. This is an optional architectural feature 262 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 263 and this option can be used to enable this feature on those systems as well. 264 This flag can take the values 0 to 2, the default is 0. 265 266- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 267 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 268 onwards. This flag can take the values 0 to 2, to align with the 269 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 270 271- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 272 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 273 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 274 optional feature available on Arm v8.0 onwards. This flag can take values 275 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 276 Default value is ``0``. 277 278- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 279 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 280 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 281 and upwards. This flag can take the values 0 to 2, to align with the 282 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 283 284- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 285 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 286 Physical Offset register) during EL2 to EL3 context save/restore operations. 287 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 288 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 289 mechanism. Default value is ``0``. 290 291- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 292 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 293 Read Trap Register) during EL2 to EL3 context save/restore operations. 294 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 295 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 296 mechanism. Default value is ``0``. 297 298- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 299 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 300 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 301 mandatory architectural feature and is enabled from v8.7 and upwards. This 302 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 303 mechanism. Default value is ``0``. 304 305- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 306 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 307 permission fault for any privileged data access from EL1/EL2 to virtual 308 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 309 mandatory architectural feature and is enabled from v8.1 and upwards. This 310 flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 311 mechanism. Default value is ``0``. 312 313- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 314 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 315 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 316 mechanism. Default value is ``0``. 317 318- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 319 extension. This feature is only supported in AArch64 state. This flag can 320 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 321 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 322 Armv8.5 onwards. 323 324- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB`` 325 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 326 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 327 later CPUs. It is enabled from v8.5 and upwards and if needed can be 328 overidden from platforms explicitly. 329 330- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 331 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 332 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 333 mechanism. Default is ``0``. 334 335- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 336 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 337 available on Arm v8.6. This flag can take values 0 to 2, to align with the 338 ``FEATURE_DETECTION`` mechanism. Default is ``0``. 339 340 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 341 delayed by the amount of value in ``TWED_DELAY``. 342 343- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 344 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 345 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 346 architectural feature and is enabled from v8.1 and upwards. It can take 347 values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 348 Default value is ``0``. 349 350- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 351 allow access to TCR2_EL2 (extended translation control) from EL2 as 352 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 353 mandatory architectural feature and is enabled from v8.9 and upwards. This 354 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 355 mechanism. Default value is ``0``. 356 357- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 358 at EL2 and below, and context switch relevant registers. This flag 359 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 360 mechanism. Default value is ``0``. 361 362- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 363 at EL2 and below, and context switch relevant registers. This flag 364 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 365 mechanism. Default value is ``0``. 366 367- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 368 at EL2 and below, and context switch relevant registers. This flag 369 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 370 mechanism. Default value is ``0``. 371 372- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 373 at EL2 and below, and context switch relevant registers. This flag 374 can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 375 mechanism. Default value is ``0``. 376 377- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 378 support in GCC for TF-A. This option is currently only supported for 379 AArch64. Default is 0. 380 381- ``ENABLE_MPAM_FOR_LOWER_ELS``: Numeric value to enable lower ELs to use MPAM 382 feature. MPAM is an optional Armv8.4 extension that enables various memory 383 system components and resources to define partitions; software running at 384 various ELs can assign themselves to desired partition to control their 385 performance aspects. 386 387 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 388 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 389 access their own MPAM registers without trapping into EL3. This option 390 doesn't make use of partitioning in EL3, however. Platform initialisation 391 code should configure and use partitions in EL3 as required. This option 392 defaults to ``0``. 393 394- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 395 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 396 firmware to detect and limit high activity events to assist in SoC processor 397 power domain dynamic power budgeting and limit the triggering of whole-rail 398 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 399 400- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which 401 allows platforms with cores supporting MPMM to describe them via the 402 ``HW_CONFIG`` device tree blob. Default is 0. 403 404- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 405 support within generic code in TF-A. This option is currently only supported 406 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 407 in BL32 (SP_min) for AARCH32. Default is 0. 408 409- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 410 Measurement Framework(PMF). Default is 0. 411 412- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 413 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 414 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 415 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 416 software. 417 418- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 419 Management Extension. This flag can take the values 0 to 2, to align with 420 the ``FEATURE_DETECTION`` mechanism. Default value is 0. This is currently 421 an experimental feature. 422 423- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 424 instrumentation which injects timestamp collection points into TF-A to 425 allow runtime performance to be measured. Currently, only PSCI is 426 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 427 as well. Default is 0. 428 429- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 430 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 431 registers so are enabled together. Using this option without 432 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 433 world to trap to EL3. SME is an optional architectural feature for AArch64 434 and TF-A support is experimental. At this time, this build option cannot be 435 used on systems that have SPD=spmd/SPM_MM or ENABLE_RME, and attempting to 436 build with these options will fail. This flag can take the values 0 to 2, to 437 align with the ``FEATURE_DETECTION`` mechanism. Default is 0. 438 439- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 440 Extension for secure world use along with SVE and FPU/SIMD, ENABLE_SME_FOR_NS 441 must also be set to use this. If enabling this, the secure world MUST 442 handle context switching for SME, SVE, and FPU/SIMD registers to ensure that 443 no data is leaked to non-secure world. This is experimental. Default is 0. 444 445- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 446 extensions. This is an optional architectural feature for AArch64. 447 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 448 mechanism. The default is 2 but is automatically disabled when the target 449 architecture is AArch32. 450 451- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 452 (SVE) for the Non-secure world only. SVE is an optional architectural feature 453 for AArch64. Note that when SVE is enabled for the Non-secure world, access 454 to SIMD and floating-point functionality from the Secure world is disabled by 455 default and controlled with ENABLE_SVE_FOR_SWD. 456 This is to avoid corruption of the Non-secure world data in the Z-registers 457 which are aliased by the SIMD and FP registers. The build option is not 458 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 459 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` enabled. 460 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 461 mechanism. The default is 2 but is automatically disabled when 462 ENABLE_SME_FOR_NS is enabled ( set to 1 or 2) since SME encompasses SVE. 463 At this time, this build option cannot be used on systems that have SPM_MM 464 enabled. 465 466- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. 467 SVE is an optional architectural feature for AArch64. Note that this option 468 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it 469 is automatically disabled when the target architecture is AArch32. 470 471- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 472 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 473 default value is set to "none". "strong" is the recommended stack protection 474 level if this feature is desired. "none" disables the stack protection. For 475 all values other than "none", the ``plat_get_stack_protector_canary()`` 476 platform hook needs to be implemented. The value is passed as the last 477 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 478 479- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 480 flag depends on ``DECRYPTION_SUPPORT`` build flag. 481 482- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 483 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 484 485- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 486 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 487 on ``DECRYPTION_SUPPORT`` build flag. 488 489- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 490 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 491 build flag. 492 493- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 494 deprecated platform APIs, helper functions or drivers within Trusted 495 Firmware as error. It can take the value 1 (flag the use of deprecated 496 APIs as error) or 0. The default is 0. 497 498- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 499 targeted at EL3. When set ``0`` (default), no exceptions are expected or 500 handled at EL3, and a panic will result. The exception to this rule is when 501 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 502 occuring during normal world execution, are trapped to EL3. Any exception 503 trapped during secure world execution are trapped to the SPMC. This is 504 supported only for AArch64 builds. 505 506- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 507 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 508 Default value is 40 (LOG_LEVEL_INFO). 509 510- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 511 injection from lower ELs, and this build option enables lower ELs to use 512 Error Records accessed via System Registers to inject faults. This is 513 applicable only to AArch64 builds. 514 515 This feature is intended for testing purposes only, and is advisable to keep 516 disabled for production images. 517 518- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 519 detection mechanism. It detects whether the Architectural features enabled 520 through feature specific build flags are supported by the PE or not by 521 validating them either at boot phase or at runtime based on the value 522 possessed by the feature flag (0 to 2) and report error messages at an early 523 stage. 524 525 This prevents and benefits us from EL3 runtime exceptions during context save 526 and restore routines guarded by these build flags. Henceforth validating them 527 before their usage provides more control on the actions taken under them. 528 529 The mechanism permits the build flags to take values 0, 1 or 2 and 530 evaluates them accordingly. 531 532 Lets consider ``ENABLE_FEAT_HCX``, build flag for ``FEAT_HCX`` as an example: 533 534 :: 535 536 ENABLE_FEAT_HCX = 0: Feature disabled statically at compile time. 537 ENABLE_FEAT_HCX = 1: Feature Enabled and the flag is validated at boottime. 538 ENABLE_FEAT_HCX = 2: Feature Enabled and the flag is validated at runtime. 539 540 In the above example, if the feature build flag, ``ENABLE_FEAT_HCX`` set to 541 0, feature is disabled statically during compilation. If it is defined as 1, 542 feature is validated, wherein FEAT_HCX is detected at boot time. In case not 543 implemented by the PE, a hard panic is generated. Finally, if the flag is set 544 to 2, feature is validated at runtime. 545 546 Note that the entire implementation is divided into two phases, wherein as 547 as part of phase-1 we are supporting the values 0,1. Value 2 is currently not 548 supported and is planned to be handled explicilty in phase-2 implementation. 549 550 FEATURE_DETECTION macro is disabled by default, and is currently an 551 experimental procedure. Platforms can explicitly make use of this by 552 mechanism, by enabling it to validate whether they have set their build flags 553 properly at an early phase. 554 555- ``FIP_NAME``: This is an optional build option which specifies the FIP 556 filename for the ``fip`` target. Default is ``fip.bin``. 557 558- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 559 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 560 561- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 562 563 :: 564 565 0: Encryption is done with Secret Symmetric Key (SSK) which is common 566 for a class of devices. 567 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 568 unique per device. 569 570 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 571 572- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 573 tool to create certificates as per the Chain of Trust described in 574 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 575 include the certificates in the FIP and FWU_FIP. Default value is '0'. 576 577 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 578 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 579 the corresponding certificates, and to include those certificates in the 580 FIP and FWU_FIP. 581 582 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 583 images will not include support for Trusted Board Boot. The FIP will still 584 include the corresponding certificates. This FIP can be used to verify the 585 Chain of Trust on the host machine through other mechanisms. 586 587 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 588 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 589 will not include the corresponding certificates, causing a boot failure. 590 591- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 592 inherent support for specific EL3 type interrupts. Setting this build option 593 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 594 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 595 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 596 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 597 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 598 the Secure Payload interrupts needs to be synchronously handed over to Secure 599 EL1 for handling. The default value of this option is ``0``, which means the 600 Group 0 interrupts are assumed to be handled by Secure EL1. 601 602- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 603 Interrupts, resulting from errors in NS world, will be always trapped in 604 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 605 will be trapped in the current exception level (or in EL1 if the current 606 exception level is EL0). 607 608- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 609 software operations are required for CPUs to enter and exit coherency. 610 However, newer systems exist where CPUs' entry to and exit from coherency 611 is managed in hardware. Such systems require software to only initiate these 612 operations, and the rest is managed in hardware, minimizing active software 613 management. In such systems, this boolean option enables TF-A to carry out 614 build and run-time optimizations during boot and power management operations. 615 This option defaults to 0 and if it is enabled, then it implies 616 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 617 618 If this flag is disabled while the platform which TF-A is compiled for 619 includes cores that manage coherency in hardware, then a compilation error is 620 generated. This is based on the fact that a system cannot have, at the same 621 time, cores that manage coherency in hardware and cores that don't. In other 622 words, a platform cannot have, at the same time, cores that require 623 ``HW_ASSISTED_COHERENCY=1`` and cores that require 624 ``HW_ASSISTED_COHERENCY=0``. 625 626 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 627 translation library (xlat tables v2) must be used; version 1 of translation 628 library is not supported. 629 630- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for 631 implementation defined system register accesses from lower ELs. Default 632 value is ``0``. 633 634- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 635 bottom, higher addresses at the top. This build flag can be set to '1' to 636 invert this behavior. Lower addresses will be printed at the top and higher 637 addresses at the bottom. 638 639- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 640 runtime software in AArch32 mode, which is required to run AArch32 on Juno. 641 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in 642 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable 643 images. 644 645- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 646 used for generating the PKCS keys and subsequent signing of the certificate. 647 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 648 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 649 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 650 compatibility. The default value of this flag is ``rsa`` which is the TBBR 651 compliant PKCS#1 RSA 2.1 scheme. 652 653- ``KEY_SIZE``: This build flag enables the user to select the key size for 654 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 655 depend on the chosen algorithm and the cryptographic module. 656 657 +---------------------------+------------------------------------+ 658 | KEY_ALG | Possible key sizes | 659 +===========================+====================================+ 660 | rsa | 1024 , 2048 (default), 3072, 4096* | 661 +---------------------------+------------------------------------+ 662 | ecdsa | unavailable | 663 +---------------------------+------------------------------------+ 664 | ecdsa-brainpool-regular | unavailable | 665 +---------------------------+------------------------------------+ 666 | ecdsa-brainpool-twisted | unavailable | 667 +---------------------------+------------------------------------+ 668 669 670 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. 671 Only 3072 bits size is available with CryptoCell 712 SBROM release 2. 672 673- ``HASH_ALG``: This build flag enables the user to select the secure hash 674 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 675 The default value of this flag is ``sha256``. 676 677- ``LDFLAGS``: Extra user options appended to the linkers' command line in 678 addition to the one set by the build system. 679 680- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 681 output compiled into the build. This should be one of the following: 682 683 :: 684 685 0 (LOG_LEVEL_NONE) 686 10 (LOG_LEVEL_ERROR) 687 20 (LOG_LEVEL_NOTICE) 688 30 (LOG_LEVEL_WARNING) 689 40 (LOG_LEVEL_INFO) 690 50 (LOG_LEVEL_VERBOSE) 691 692 All log output up to and including the selected log level is compiled into 693 the build. The default value is 40 in debug builds and 20 in release builds. 694 695- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 696 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 697 provide trust that the code taking the measurements and recording them has 698 not been tampered with. 699 700 This option defaults to 0. 701 702- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 703 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 704 the measurements and recording them as per `PSA DRTM specification`_. For 705 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 706 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 707 should have mechanism to authenticate BL31. This is an experimental feature. 708 709 This option defaults to 0. 710 711- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 712 specifies the file that contains the Non-Trusted World private key in PEM 713 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 714 715- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 716 optional. It is only needed if the platform makefile specifies that it 717 is required in order to build the ``fwu_fip`` target. 718 719- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 720 contents upon world switch. It can take either 0 (don't save and restore) or 721 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 722 wants the timer registers to be saved and restored. 723 724- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 725 for the BL image. It can be either 0 (include) or 1 (remove). The default 726 value is 0. 727 728- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 729 the underlying hardware is not a full PL011 UART but a minimally compliant 730 generic UART, which is a subset of the PL011. The driver will not access 731 any register that is not part of the SBSA generic UART specification. 732 Default value is 0 (a full PL011 compliant UART is present). 733 734- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 735 must be subdirectory of any depth under ``plat/``, and must contain a 736 platform makefile named ``platform.mk``. For example, to build TF-A for the 737 Arm Juno board, select PLAT=juno. 738 739- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 740 instead of the normal boot flow. When defined, it must specify the entry 741 point address for the preloaded BL33 image. This option is incompatible with 742 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 743 over ``PRELOADED_BL33_BASE``. 744 745- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 746 vector address can be programmed or is fixed on the platform. It can take 747 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 748 programmable reset address, it is expected that a CPU will start executing 749 code directly at the right address, both on a cold and warm reset. In this 750 case, there is no need to identify the entrypoint on boot and the boot path 751 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 752 does not need to be implemented in this case. 753 754- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 755 possible for the PSCI power-state parameter: original and extended State-ID 756 formats. This flag if set to 1, configures the generic PSCI layer to use the 757 extended format. The default value of this flag is 0, which means by default 758 the original power-state format is used by the PSCI implementation. This flag 759 should be specified by the platform makefile and it governs the return value 760 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 761 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 762 set to 1 as well. 763 764- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 765 OS-initiated mode. This option defaults to 0. 766 767- ``RAS_EXTENSION``: Numeric value to enable Armv8.2 RAS features. RAS features 768 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 769 or later CPUs. This flag can take the values 0 to 2, to align with the 770 ``FEATURE_DETECTION`` mechanism. 771 772 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST_NS`` must also be 773 set to ``1``. 774 775 This option is disabled by default. 776 777- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 778 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 779 entrypoint) or 1 (CPU reset to BL31 entrypoint). 780 The default value is 0. 781 782- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 783 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 784 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 785 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 786 787- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 788 file that contains the ROT private key in PEM format and enforces public key 789 hash generation. If ``SAVE_KEYS=1``, this 790 file name will be used to save the key. 791 792- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 793 certificate generation tool to save the keys used to establish the Chain of 794 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 795 796- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 797 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 798 target. 799 800- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 801 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, 802 this file name will be used to save the key. 803 804- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 805 optional. It is only needed if the platform makefile specifies that it 806 is required in order to build the ``fwu_fip`` target. 807 808- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 809 Delegated Exception Interface to BL31 image. This defaults to ``0``. 810 811 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 812 set to ``1``. 813 814- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 815 isolated on separate memory pages. This is a trade-off between security and 816 memory usage. See "Isolating code and read-only data on separate memory 817 pages" section in :ref:`Firmware Design`. This flag is disabled by default 818 and affects all BL images. 819 820- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 821 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 822 allocated in RAM discontiguous from the loaded firmware image. When set, the 823 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 824 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 825 sections are placed in RAM immediately following the loaded firmware image. 826 827- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 828 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 829 discontiguous from loaded firmware images. When set, the platform need to 830 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 831 flag is disabled by default and NOLOAD sections are placed in RAM immediately 832 following the loaded firmware image. 833 834- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 835 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 836 UEFI+ACPI this can provide a certain amount of OS forward compatibility 837 with newer platforms that aren't ECAM compliant. 838 839- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 840 This build option is only valid if ``ARCH=aarch64``. The value should be 841 the path to the directory containing the SPD source, relative to 842 ``services/spd/``; the directory is expected to contain a makefile called 843 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 844 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 845 cannot be enabled when the ``SPM_MM`` option is enabled. 846 847- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 848 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 849 execution in BL1 just before handing over to BL31. At this point, all 850 firmware images have been loaded in memory, and the MMU and caches are 851 turned off. Refer to the "Debugging options" section for more details. 852 853- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 854 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 855 component runs at the EL3 exception level. The default value is ``0`` ( 856 disabled). This configuration supports pre-Armv8.4 platforms (aka not 857 implementing the ``FEAT_SEL2`` extension). This is an experimental feature. 858 859- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 860 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 861 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 862 mechanism should be used. 863 864- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 865 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 866 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 867 extension. This is the default when enabling the SPM Dispatcher. When 868 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 869 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 870 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 871 extension). 872 873- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 874 Partition Manager (SPM) implementation. The default value is ``0`` 875 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 876 enabled (``SPD=spmd``). 877 878- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 879 description of secure partitions. The build system will parse this file and 880 package all secure partition blobs into the FIP. This file is not 881 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 882 883- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 884 secure interrupts (caught through the FIQ line). Platforms can enable 885 this directive if they need to handle such interruption. When enabled, 886 the FIQ are handled in monitor mode and non secure world is not allowed 887 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 888 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 889 890- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 891 Platforms can configure this if they need to lower the hardware 892 limit, for example due to asymmetric configuration or limitations of 893 software run at lower ELs. The default is the architectural maximum 894 of 2048 which should be suitable for most configurations, the 895 hardware will limit the effective VL to the maximum physically supported 896 VL. 897 898- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 899 Random Number Generator Interface to BL31 image. This defaults to ``0``. 900 901- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 902 Boot feature. When set to '1', BL1 and BL2 images include support to load 903 and verify the certificates and images in a FIP, and BL1 includes support 904 for the Firmware Update. The default value is '0'. Generation and inclusion 905 of certificates in the FIP and FWU_FIP depends upon the value of the 906 ``GENERATE_COT`` option. 907 908 .. warning:: 909 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 910 already exist in disk, they will be overwritten without further notice. 911 912- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 913 specifies the file that contains the Trusted World private key in PEM 914 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 915 916- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 917 synchronous, (see "Initializing a BL32 Image" section in 918 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 919 synchronous method) or 1 (BL32 is initialized using asynchronous method). 920 Default is 0. 921 922- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 923 routing model which routes non-secure interrupts asynchronously from TSP 924 to EL3 causing immediate preemption of TSP. The EL3 is responsible 925 for saving and restoring the TSP context in this routing model. The 926 default routing model (when the value is 0) is to route non-secure 927 interrupts to TSP allowing it to save its context and hand over 928 synchronously to EL3 via an SMC. 929 930 .. note:: 931 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 932 must also be set to ``1``. 933 934- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 935 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 936 this delay. It can take values in the range (0-15). Default value is ``0`` 937 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 938 Platforms need to explicitly update this value based on their requirements. 939 940- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 941 linker. When the ``LINKER`` build variable points to the armlink linker, 942 this flag is enabled automatically. To enable support for armlink, platforms 943 will have to provide a scatter file for the BL image. Currently, Tegra 944 platforms use the armlink support to compile BL3-1 images. 945 946- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 947 memory region in the BL memory map or not (see "Use of Coherent memory in 948 TF-A" section in :ref:`Firmware Design`). It can take the value 1 949 (Coherent memory region is included) or 0 (Coherent memory region is 950 excluded). Default is 1. 951 952- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature 953 exposing a virtual filesystem interface through BL31 as a SiP SMC function. 954 Default is 0. 955 956- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 957 firmware configuration framework. This will move the io_policies into a 958 configuration device tree, instead of static structure in the code base. 959 960- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 961 at runtime using fconf. If this flag is enabled, COT descriptors are 962 statically captured in tb_fw_config file in the form of device tree nodes 963 and properties. Currently, COT descriptors used by BL2 are moved to the 964 device tree and COT descriptors used by BL1 are retained in the code 965 base statically. 966 967- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 968 runtime using firmware configuration framework. The platform specific SDEI 969 shared and private events configuration is retrieved from device tree rather 970 than static C structures at compile time. This is only supported if 971 SDEI_SUPPORT build flag is enabled. 972 973- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 974 and Group1 secure interrupts using the firmware configuration framework. The 975 platform specific secure interrupt property descriptor is retrieved from 976 device tree in runtime rather than depending on static C structure at compile 977 time. 978 979- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 980 This feature creates a library of functions to be placed in ROM and thus 981 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 982 is 0. 983 984- ``V``: Verbose build. If assigned anything other than 0, the build commands 985 are printed. Default is 0. 986 987- ``VERSION_STRING``: String used in the log output for each TF-A image. 988 Defaults to a string formed by concatenating the version number, build type 989 and build string. 990 991- ``W``: Warning level. Some compiler warning options of interest have been 992 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 993 each level enabling more warning options. Default is 0. 994 995 This option is closely related to the ``E`` option, which enables 996 ``-Werror``. 997 998 - ``W=0`` (default) 999 1000 Enables a wide assortment of warnings, most notably ``-Wall`` and 1001 ``-Wextra``, as well as various bad practices and things that are likely to 1002 result in errors. Includes some compiler specific flags. No warnings are 1003 expected at this level for any build. 1004 1005 - ``W=1`` 1006 1007 Enables warnings we want the generic build to include but are too time 1008 consuming to fix at the moment. It re-enables warnings taken out for 1009 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1010 to eventually be merged into ``W=0``. Some warnings are expected on some 1011 builds, but new contributions should not introduce new ones. 1012 1013 - ``W=2`` (recommended) 1014 1015 Enables warnings we want the generic build to include but cannot be enabled 1016 due to external libraries. This level is expected to eventually be merged 1017 into ``W=0``. Lots of warnings are expected, primarily from external 1018 libraries like zlib and compiler-rt, but new controbutions should not 1019 introduce new ones. 1020 1021 - ``W=3`` 1022 1023 Enables warnings that are informative but not necessary and generally too 1024 verbose and frequently ignored. A very large number of warnings are 1025 expected. 1026 1027 The exact set of warning flags depends on the compiler and TF-A warning 1028 level, however they are all succinctly set in the top-level Makefile. Please 1029 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1030 individual flags. 1031 1032- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1033 the CPU after warm boot. This is applicable for platforms which do not 1034 require interconnect programming to enable cache coherency (eg: single 1035 cluster platforms). If this option is enabled, then warm boot path 1036 enables D-caches immediately after enabling MMU. This option defaults to 0. 1037 1038- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 1039 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 1040 default value of this flag is ``no``. Note this option must be enabled only 1041 for ARM architecture greater than Armv8.5-A. 1042 1043- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1044 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1045 The default value of this flag is ``0``. 1046 1047 ``AT`` speculative errata workaround disables stage1 page table walk for 1048 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1049 produces either the correct result or failure without TLB allocation. 1050 1051 This boolean option enables errata for all below CPUs. 1052 1053 +---------+--------------+-------------------------+ 1054 | Errata | CPU | Workaround Define | 1055 +=========+==============+=========================+ 1056 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1057 +---------+--------------+-------------------------+ 1058 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1059 +---------+--------------+-------------------------+ 1060 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1061 +---------+--------------+-------------------------+ 1062 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1063 +---------+--------------+-------------------------+ 1064 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1065 +---------+--------------+-------------------------+ 1066 1067 .. note:: 1068 This option is enabled by build only if platform sets any of above defines 1069 mentioned in ’Workaround Define' column in the table. 1070 If this option is enabled for the EL3 software then EL2 software also must 1071 implement this workaround due to the behaviour of the errata mentioned 1072 in new SDEN document which will get published soon. 1073 1074- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1075 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1076 This flag is disabled by default. 1077 1078- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1079 host machine where a custom installation of OpenSSL is located, which is used 1080 to build the certificate generation, firmware encryption and FIP tools. If 1081 this option is not set, the default OS installation will be used. 1082 1083- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1084 functions that wait for an arbitrary time length (udelay and mdelay). The 1085 default value is 0. 1086 1087- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1088 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1089 optional architectural feature for AArch64. This flag can take the values 1090 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0 1091 and it is automatically disabled when the target architecture is AArch32. 1092 1093- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1094 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1095 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1096 feature for AArch64. This flag can take the values 0 to 2, to align with the 1097 ``FEATURE_DETECTION`` mechanism. The default is 0 and it is automatically 1098 disabled when the target architecture is AArch32. 1099 1100- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1101 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1102 but unused). This feature is available if trace unit such as ETMv4.x, and 1103 ETE(extending ETM feature) is implemented. This flag can take the values 1104 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. The default is 0. 1105 1106- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1107 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1108 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1109 with the ``FEATURE_DETECTION`` mechanism. This flag is disabled by default. 1110 1111- ``PLAT_RSS_NOT_SUPPORTED``: Boolean option to enable the usage of the PSA 1112 APIs on platforms that doesn't support RSS (providing Arm CCA HES 1113 functionalities). When enabled (``1``), a mocked version of the APIs are used. 1114 The default value is 0. 1115 1116- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1117 ``plat_can_cmo`` which will return zero if cache management operations should 1118 be skipped and non-zero otherwise. By default, this option is disabled which 1119 means platform hook won't be checked and CMOs will always be performed when 1120 related functions are called. 1121 1122GICv3 driver options 1123-------------------- 1124 1125GICv3 driver files are included using directive: 1126 1127``include drivers/arm/gic/v3/gicv3.mk`` 1128 1129The driver can be configured with the following options set in the platform 1130makefile: 1131 1132- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1133 Enabling this option will add runtime detection support for the 1134 GIC-600, so is safe to select even for a GIC500 implementation. 1135 This option defaults to 0. 1136 1137- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1138 for GIC-600 AE. Enabling this option will introduce support to initialize 1139 the FMU. Platforms should call the init function during boot to enable the 1140 FMU and its safety mechanisms. This option defaults to 0. 1141 1142- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1143 functionality. This option defaults to 0 1144 1145- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1146 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1147 functions. This is required for FVP platform which need to simulate GIC save 1148 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1149 1150- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1151 This option defaults to 0. 1152 1153- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1154 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1155 1156Debugging options 1157----------------- 1158 1159To compile a debug version and make the build more verbose use 1160 1161.. code:: shell 1162 1163 make PLAT=<platform> DEBUG=1 V=1 all 1164 1165AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1166(for example Arm-DS) might not support this and may need an older version of 1167DWARF symbols to be emitted by GCC. This can be achieved by using the 1168``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1169the version to 4 is recommended for Arm-DS. 1170 1171When debugging logic problems it might also be useful to disable all compiler 1172optimizations by using ``-O0``. 1173 1174.. warning:: 1175 Using ``-O0`` could cause output images to be larger and base addresses 1176 might need to be recalculated (see the **Memory layout on Arm development 1177 platforms** section in the :ref:`Firmware Design`). 1178 1179Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1180``LDFLAGS``: 1181 1182.. code:: shell 1183 1184 CFLAGS='-O0 -gdwarf-2' \ 1185 make PLAT=<platform> DEBUG=1 V=1 all 1186 1187Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1188ignored as the linker is called directly. 1189 1190It is also possible to introduce an infinite loop to help in debugging the 1191post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1192``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1193section. In this case, the developer may take control of the target using a 1194debugger when indicated by the console output. When using Arm-DS, the following 1195commands can be used: 1196 1197:: 1198 1199 # Stop target execution 1200 interrupt 1201 1202 # 1203 # Prepare your debugging environment, e.g. set breakpoints 1204 # 1205 1206 # Jump over the debug loop 1207 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1208 1209 # Resume execution 1210 continue 1211 1212Firmware update options 1213----------------------- 1214 1215- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1216 in defining the firmware update metadata structure. This flag is by default 1217 set to '2'. 1218 1219- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1220 firmware bank. Each firmware bank must have the same number of images as per 1221 the `PSA FW update specification`_. 1222 This flag is used in defining the firmware update metadata structure. This 1223 flag is by default set to '1'. 1224 1225- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1226 `PSA FW update specification`_. The default value is 0, and this is an 1227 experimental feature. 1228 PSA firmware update implementation has some limitations, such as BL2 is 1229 not part of the protocol-updatable images, if BL2 needs to be updated, then 1230 it should be done through another platform-defined mechanism, and it assumes 1231 that the platform's hardware supports CRC32 instructions. 1232 1233-------------- 1234 1235*Copyright (c) 2019-2023, Arm Limited. All rights reserved.* 1236 1237.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1238.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/ 1239.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1240.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1241.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1242