1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. External 27 memory-mapped debug accesses are unaffected by this control. 28 The default value is 1 for all platforms. 29 30- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 31 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 32 ``aarch64``. 33 34- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 35 one or more feature modifiers. This option has the form ``[no]feature+...`` 36 and defaults to ``none``. It translates into compiler option 37 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 38 list of supported feature modifiers. 39 40- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 41 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 42 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 43 :ref:`Firmware Design`. 44 45- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 46 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 47 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 48 49- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded 50 SP nodes in tb_fw_config. 51 52- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the 53 SPMC Core manifest. Valid when ``SPD=spmd`` is selected. 54 55- ``BL2``: This is an optional build option which specifies the path to BL2 56 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 57 built. 58 59- ``BL2U``: This is an optional build option which specifies the path to 60 BL2U image. In this case, the BL2U in TF-A will not be built. 61 62- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 63 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 64 entrypoint) or 1 (CPU reset to BL2 entrypoint). 65 The default value is 0. 66 67- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 68 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 69 true in a 4-world system where RESET_TO_BL2 is 0. 70 71- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 72 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 73 74- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 75 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 76 the RW sections in RAM, while leaving the RO sections in place. This option 77 enable this use-case. For now, this option is only supported 78 when RESET_TO_BL2 is set to '1'. 79 80- ``BL31``: This is an optional build option which specifies the path to 81 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 82 be built. 83 84- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 85 file that contains the BL31 private key in PEM format or a PKCS11 URI. If 86 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 87 88- ``BL32``: This is an optional build option which specifies the path to 89 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 90 be built. 91 92- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 93 Trusted OS Extra1 image for the ``fip`` target. 94 95- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 96 Trusted OS Extra2 image for the ``fip`` target. 97 98- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 99 file that contains the BL32 private key in PEM format or a PKCS11 URI. If 100 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 101 102- ``RMM``: This is an optional build option used when ``ENABLE_RME`` is set. 103 It specifies the path to RMM binary for the ``fip`` target. If the RMM option 104 is not specified, TF-A builds the TRP to load and run at R-EL2. 105 106- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 107 ``fip`` target in case TF-A BL2 is used. 108 109- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 110 file that contains the BL33 private key in PEM format or a PKCS11 URI. If 111 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 112 113- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 114 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 115 If enabled, it is needed to use a compiler that supports the option 116 ``-mbranch-protection``. The value of the ``-march`` (via ``ARM_ARCH_MINOR`` 117 and ``ARM_ARCH_MAJOR``) option will control which instructions will be 118 emitted (HINT space or not). Selects the branch protection features to use: 119- 0: Default value turns off all types of branch protection (FEAT_STATE_DISABLED) 120- 1: Enables all types of branch protection features 121- 2: Return address signing to its standard level 122- 3: Extend the signing to include leaf functions 123- 4: Turn on branch target identification mechanism 124- 5: Enables all types of branch protection features, only if present in 125 hardware (FEAT_STATE_CHECK). 126 127 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 128 and resulting PAuth/BTI features. 129 130 +-------+--------------+-------+-----+ 131 | Value | GCC option | PAuth | BTI | 132 +=======+==============+=======+=====+ 133 | 0 | none | N | N | 134 +-------+--------------+-------+-----+ 135 | 1 | standard | Y | Y | 136 +-------+--------------+-------+-----+ 137 | 2 | pac-ret | Y | N | 138 +-------+--------------+-------+-----+ 139 | 3 | pac-ret+leaf | Y | N | 140 +-------+--------------+-------+-----+ 141 | 4 | bti | N | Y | 142 +-------+--------------+-------+-----+ 143 | 5 | dynamic | Y | Y | 144 +-------+--------------+-------+-----+ 145 146 This option defaults to 0. 147 Note that Pointer Authentication is enabled for Non-secure world 148 irrespective of the value of this option if the CPU supports it. 149 150- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 151 compilation of each build. It must be set to a C string (including quotes 152 where applicable). Defaults to a string that contains the time and date of 153 the compilation. 154 155- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 156 build to be uniquely identified. Defaults to the current git commit id. 157 158- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 159 160- ``CFLAGS``: Extra user options appended on the compiler's command line in 161 addition to the options set by the build system. 162 163- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 164 release several CPUs out of reset. It can take either 0 (several CPUs may be 165 brought up) or 1 (only one CPU will ever be brought up during cold reset). 166 Default is 0. If the platform always brings up a single CPU, there is no 167 need to distinguish between primary and secondary CPUs and the boot path can 168 be optimised. The ``plat_is_my_cpu_primary()`` and 169 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 170 to be implemented in this case. 171 172- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 173 Defaults to ``tbbr``. 174 175- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 176 register state when an unexpected exception occurs during execution of 177 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 178 this is only enabled for a debug build of the firmware. 179 180- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 181 certificate generation tool to create new keys in case no valid keys are 182 present or specified. Allowed options are '0' or '1'. Default is '1'. 183 184- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 185 the AArch32 system registers to be included when saving and restoring the 186 CPU context. The option must be set to 0 for AArch64-only platforms (that 187 is on hardware that does not implement AArch32, or at least not at EL1 and 188 higher ELs). Default value is 1. 189 190- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 191 registers to be included when saving and restoring the CPU context. Default 192 is 0. 193 194- ``CTX_INCLUDE_MPAM_REGS``: Boolean option that, when set to 1, will cause the 195 Memory System Resource Partitioning and Monitoring (MPAM) 196 registers to be included when saving and restoring the CPU context. 197 Default is '0'. 198 199- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 200 registers to be saved/restored when entering/exiting an EL2 execution 201 context. This flag can take values 0 to 2, to align with the 202 ``ENABLE_FEAT`` mechanism. Default value is 0. 203 204- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 205 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 206 to be included when saving and restoring the CPU context as part of world 207 switch. Automatically enabled when ``BRANCH_PROTECTION`` is enabled. This flag 208 can take values 0 to 2, to align with ``ENABLE_FEAT`` mechanism. Default value 209 is 0. 210 211 Note that Pointer Authentication is enabled for Non-secure world irrespective 212 of the value of this flag if the CPU supports it. Alternatively, when 213 ``BRANCH_PROTECTION`` is enabled, this flag is superseded. 214 215- ``CTX_INCLUDE_SVE_REGS``: Boolean option that, when set to 1, will cause the 216 SVE registers to be included when saving and restoring the CPU context. Note 217 that this build option requires ``ENABLE_SVE_FOR_SWD`` to be enabled. In 218 general, it is recommended to perform SVE context management in lower ELs 219 and skip in EL3 due to the additional cost of maintaining large data 220 structures to track the SVE state. Hence, the default value is 0. 221 222- ``DEBUG``: Chooses between a debug and release build. It can take either 0 223 (release) or 1 (debug) as values. 0 is the default. 224 225- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 226 authenticated decryption algorithm to be used to decrypt firmware/s during 227 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 228 this flag is ``none`` to disable firmware decryption which is an optional 229 feature as per TBBR. 230 231- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 232 of the binary image. If set to 1, then only the ELF image is built. 233 0 is the default. 234 235- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded 236 PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards. 237 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 238 mechanism. Default is ``0``. 239 240- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 241 Board Boot authentication at runtime. This option is meant to be enabled only 242 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 243 flag has to be enabled. 0 is the default. 244 245- ``E``: Boolean option to make warnings into errors. Default is 1. 246 247 When specifying higher warnings levels (``W=1`` and higher), this option 248 defaults to 0. This is done to encourage contributors to use them, as they 249 are expected to produce warnings that would otherwise fail the build. New 250 contributions are still expected to build with ``W=0`` and ``E=1`` (the 251 default). 252 253- ``EARLY_CONSOLE``: This option is used to enable early traces before default 254 console is properly setup. It introduces EARLY_* traces macros, that will 255 use the non-EARLY traces macros if the flag is enabled, or do nothing 256 otherwise. To use this feature, platforms will have to create the function 257 plat_setup_early_console(). 258 Default is 0 (disabled) 259 260- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 261 the normal boot flow. It must specify the entry point address of the EL3 262 payload. Please refer to the "Booting an EL3 payload" section for more 263 details. 264 265- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 266 (also known as group 1 counters). These are implementation-defined counters, 267 and as such require additional platform configuration. Default is 0. 268 269- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 270 are compiled out. For debug builds, this option defaults to 1, and calls to 271 ``assert()`` are left in place. For release builds, this option defaults to 0 272 and calls to ``assert()`` function are compiled out. This option can be set 273 independently of ``DEBUG``. It can also be used to hide any auxiliary code 274 that is only required for the assertion and does not fit in the assertion 275 itself. 276 277- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 278 dumps or not. It is supported in both AArch64 and AArch32. However, in 279 AArch32 the format of the frame records are not defined in the AAPCS and they 280 are defined by the implementation. This implementation of backtrace only 281 supports the format used by GCC when T32 interworking is disabled. For this 282 reason enabling this option in AArch32 will force the compiler to only 283 generate A32 code. This option is enabled by default only in AArch64 debug 284 builds, but this behaviour can be overridden in each platform's Makefile or 285 in the build command line. 286 287- ``ENABLE_FEAT`` 288 The Arm architecture defines several architecture extension features, 289 named FEAT_xxx in the architecure manual. Some of those features require 290 setup code in higher exception levels, other features might be used by TF-A 291 code itself. 292 Most of the feature flags defined in the TF-A build system permit to take 293 the values 0, 1 or 2, with the following meaning: 294 295 :: 296 297 ENABLE_FEAT_* = 0: Feature is disabled statically at compile time. 298 ENABLE_FEAT_* = 1: Feature is enabled unconditionally at compile time. 299 ENABLE_FEAT_* = 2: Feature is enabled, but checked at runtime. 300 301 When setting the flag to 0, the feature is disabled during compilation, 302 and the compiler's optimisation stage and the linker will try to remove 303 as much of this code as possible. 304 If it is defined to 1, the code will use the feature unconditionally, so the 305 CPU is expected to support that feature. The FEATURE_DETECTION debug 306 feature, if enabled, will verify this. 307 If the feature flag is set to 2, support for the feature will be compiled 308 in, but its existence will be checked at runtime, so it works on CPUs with 309 or without the feature. This is mostly useful for platforms which either 310 support multiple different CPUs, or where the CPU is configured at runtime, 311 like in emulators. 312 313- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 314 extensions. This flag can take the values 0 to 2, to align with the 315 ``ENABLE_FEAT`` mechanism. This is an optional architectural feature 316 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 317 and this option can be used to enable this feature on those systems as well. 318 This flag can take the values 0 to 2, the default is 0. 319 320- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 321 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 322 onwards. This flag can take the values 0 to 2, to align with the 323 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 324 325- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 326 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 327 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 328 optional feature available on Arm v8.0 onwards. This flag can take values 329 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 330 Default value is ``0``. 331 332- ``ENABLE_FEAT_CSV2_3``: Numeric value to enable support for ``FEAT_CSV2_3`` 333 extension. This feature is supported in AArch64 state only and is an optional 334 feature available in Arm v8.0 implementations. 335 ``FEAT_CSV2_3`` implies the implementation of ``FEAT_CSV2_2``. 336 The flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 337 mechanism. Default value is ``0``. 338 339- ``ENABLE_FEAT_DEBUGV8P9``: Numeric value to enable ``FEAT_DEBUGV8P9`` 340 extension which allows the ability to implement more than 16 breakpoints 341 and/or watchpoints. This feature is mandatory from v8.9 and is optional 342 from v8.8. This flag can take the values of 0 to 2, to align with the 343 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 344 345- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 346 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 347 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 348 and upwards. This flag can take the values 0 to 2, to align with the 349 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 350 351- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 352 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 353 Physical Offset register) during EL2 to EL3 context save/restore operations. 354 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 355 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 356 mechanism. Default value is ``0``. 357 358- ``ENABLE_FEAT_FPMR``: Numerical value to enable support for Floating Point 359 Mode Register feature, allowing access to the FPMR register. FPMR register 360 controls the behaviors of FP8 instructions. It is an optional architectural 361 feature from v9.2 and upwards. This flag can take value of 0 to 2, to align 362 with the ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 363 364- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 365 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 366 Read Trap Register) during EL2 to EL3 context save/restore operations. 367 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 368 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 369 mechanism. Default value is ``0``. 370 371- ``ENABLE_FEAT_FGT2``: Numeric value to enable support for FGT2 372 (Fine Grain Traps 2) feature allowing for access to Fine-grained trap 2 registers 373 during EL2 to EL3 context save/restore operations. 374 Its an optional architectural feature and is available from v8.8 and upwards. 375 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 376 mechanism. Default value is ``0``. 377 378- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 379 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 380 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 381 mandatory architectural feature and is enabled from v8.7 and upwards. This 382 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 383 mechanism. Default value is ``0``. 384 385- ``ENABLE_FEAT_MOPS``: Numeric value to enable FEAT_MOPS (Standardization 386 of memory operations) when INIT_UNUSED_NS_EL2=1. 387 This feature is mandatory from v8.8 and enabling of FEAT_MOPS does not 388 require any settings from EL3 as the controls are present in EL2 registers 389 (HCRX_EL2.{MSCEn,MCE2} and SCTLR_EL2.MSCEn) and in most configurations 390 we expect EL2 to be present. But in case of INIT_UNUSED_NS_EL2=1 , 391 EL3 should configure the EL2 registers. This flag 392 can take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 393 Default value is ``0``. 394 395- ``ENABLE_FEAT_MTE2``: Numeric value to enable Memory Tagging Extension2 396 if the platform wants to use this feature and MTE2 is enabled at ELX. 397 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 398 mechanism. Default value is ``0``. 399 400- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 401 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 402 permission fault for any privileged data access from EL1/EL2 to virtual 403 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 404 mandatory architectural feature and is enabled from v8.1 and upwards. This 405 flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 406 mechanism. Default value is ``0``. 407 408- ``ENABLE_FEAT_PAUTH_LR``: Numeric value to enable the ``FEAT_PAUTH_LR`` 409 extension. ``FEAT_PAUTH_LR`` is an optional feature available from Arm v9.4 410 onwards. This feature requires PAUTH to be enabled via the 411 ``BRANCH_PROTECTION`` flag. This flag can take the values 0 to 2, to align 412 with the ``ENABLE_FEAT`` mechanism. Default value is ``0``. 413 414- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 415 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 416 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 417 mechanism. Default value is ``0``. 418 419- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 420 extension. This feature is only supported in AArch64 state. This flag can 421 take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 422 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 423 Armv8.5 onwards. 424 425- ``ENABLE_FEAT_SB``: Boolean option to let the TF-A code use the ``FEAT_SB`` 426 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 427 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 428 later CPUs. It is enabled from v8.5 and upwards and if needed can be 429 overidden from platforms explicitly. 430 431- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 432 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 433 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 434 mechanism. Default is ``0``. 435 436- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 437 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 438 available on Arm v8.6. This flag can take values 0 to 2, to align with the 439 ``ENABLE_FEAT`` mechanism. Default is ``0``. 440 441 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 442 delayed by the amount of value in ``TWED_DELAY``. 443 444- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 445 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 446 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 447 architectural feature and is enabled from v8.1 and upwards. It can take 448 values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 449 Default value is ``0``. 450 451- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 452 allow access to TCR2_EL2 (extended translation control) from EL2 as 453 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 454 mandatory architectural feature and is enabled from v8.9 and upwards. This 455 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 456 mechanism. Default value is ``0``. 457 458- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 459 at EL2 and below, and context switch relevant registers. This flag 460 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 461 mechanism. Default value is ``0``. 462 463- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 464 at EL2 and below, and context switch relevant registers. This flag 465 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 466 mechanism. Default value is ``0``. 467 468- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 469 at EL2 and below, and context switch relevant registers. This flag 470 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 471 mechanism. Default value is ``0``. 472 473- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 474 at EL2 and below, and context switch relevant registers. This flag 475 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 476 mechanism. Default value is ``0``. 477 478- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to 479 allow use of Guarded Control Stack from EL2 as well as adding the GCS 480 registers to the EL2 context save/restore operations. This flag can take 481 the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 482 Default value is ``0``. 483 484- ``ENABLE_FEAT_THE``: Numeric value to enable support for FEAT_THE 485 (Translation Hardening Extension) at EL2 and below, setting the bit 486 SCR_EL3.RCWMASKEn in EL3 to allow access to RCWMASK_EL1 and RCWSMASK_EL1 487 registers and context switch them. 488 Its an optional architectural feature and is available from v8.8 and upwards. 489 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 490 mechanism. Default value is ``0``. 491 492- ``ENABLE_FEAT_SCTLR2``: Numeric value to enable support for FEAT_SCTLR2 493 (Extension to SCTLR_ELx) at EL2 and below, setting the bit 494 SCR_EL3.SCTLR2En in EL3 to allow access to SCTLR2_ELx registers and 495 context switch them. This feature is OPTIONAL from Armv8.0 implementations 496 and mandatory in Armv8.9 implementations. 497 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 498 mechanism. Default value is ``0``. 499 500- ``ENABLE_FEAT_D128``: Numeric value to enable support for FEAT_D128 501 at EL2 and below, setting the bit SCT_EL3.D128En in EL3 to allow access to 502 128 bit version of system registers like PAR_EL1, TTBR0_EL1, TTBR1_EL1, 503 TTBR0_EL2, TTBR1_EL2, TTBR0_EL12, TTBR1_EL12 , VTTBR_EL2, RCWMASK_EL1, and 504 RCWSMASK_EL1. Its an optional architectural feature and is available from 505 9.3 and upwards. 506 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 507 mechanism. Default value is ``0``. 508 509- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 510 support in GCC for TF-A. This option is currently only supported for 511 AArch64. Default is 0. 512 513- ``ENABLE_FEAT_MPAM``: Numeric value to enable lower ELs to use MPAM 514 feature. MPAM is an optional Armv8.4 extension that enables various memory 515 system components and resources to define partitions; software running at 516 various ELs can assign themselves to desired partition to control their 517 performance aspects. 518 519 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 520 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 521 access their own MPAM registers without trapping into EL3. This option 522 doesn't make use of partitioning in EL3, however. Platform initialisation 523 code should configure and use partitions in EL3 as required. This option 524 defaults to ``2`` since MPAM is enabled by default for NS world only. 525 The flag is automatically disabled when the target 526 architecture is AArch32. 527 528- ``ENABLE_FEAT_LS64_ACCDATA``: Numeric value to enable access and save and 529 restore the ACCDATA_EL1 system register, at EL2 and below. This flag can 530 take the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 531 Default value is ``0``. 532 533- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 534 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 535 firmware to detect and limit high activity events to assist in SoC processor 536 power domain dynamic power budgeting and limit the triggering of whole-rail 537 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 538 539 - ``FEAT_PABANDON``: Boolean option to enable support for powerdown abandon on 540 Arm cores that support it (currently Gelas and Travis). Extends the PSCI 541 implementation to expect waking up after the terminal ``wfi``. Currently, 542 introduces a performance penalty. Once this is removed, this option will be 543 removed and the feature will be enabled by default. Defaults to ``0``. 544 545- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 546 support within generic code in TF-A. This option is currently only supported 547 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 548 in BL32 (SP_min) for AARCH32. Default is 0. 549 550- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 551 Measurement Framework(PMF). Default is 0. 552 553- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 554 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 555 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 556 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 557 software. 558 559- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 560 instrumentation which injects timestamp collection points into TF-A to 561 allow runtime performance to be measured. Currently, only PSCI is 562 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 563 as well. Default is 0. 564 565- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 566 extensions. This is an optional architectural feature for AArch64. 567 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 568 mechanism. The default is 2 but is automatically disabled when the target 569 architecture is AArch32. 570 571- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 572 (SVE) for the Non-secure world only. SVE is an optional architectural feature 573 for AArch64. This flag can take the values 0 to 2, to align with the 574 ``ENABLE_FEAT`` mechanism. At this time, this build option cannot be used on 575 systems that have SPM_MM enabled. The default value is 2. 576 577 Note that when SVE is enabled for the Non-secure world, access 578 to SVE, SIMD and floating-point functionality from the Secure world is 579 independently controlled by build option ``ENABLE_SVE_FOR_SWD``. When enabling 580 ``CTX_INCLUDE_FPREGS`` and ``ENABLE_SVE_FOR_NS`` together, it is mandatory to 581 enable ``CTX_INCLUDE_SVE_REGS``. This is to avoid corruption of the Non-secure 582 world data in the Z-registers which are aliased by the SIMD and FP registers. 583 584- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE and FPU/SIMD functionality 585 for the Secure world. SVE is an optional architectural feature for AArch64. 586 The default is 0 and it is automatically disabled when the target architecture 587 is AArch32. 588 589 .. note:: 590 This build flag requires ``ENABLE_SVE_FOR_NS`` to be enabled. When enabling 591 ``ENABLE_SVE_FOR_SWD``, a developer must carefully consider whether 592 ``CTX_INCLUDE_SVE_REGS`` is also needed. 593 594- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 595 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 596 default value is set to "none". "strong" is the recommended stack protection 597 level if this feature is desired. "none" disables the stack protection. For 598 all values other than "none", the ``plat_get_stack_protector_canary()`` 599 platform hook needs to be implemented. The value is passed as the last 600 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 601 602- ``ENABLE_ERRATA_ALL``: This option is used only for testing purposes, Boolean 603 option to enable the workarounds for all errata that TF-A implements. Normally 604 they should be explicitly enabled depending on each platform's needs. Not 605 recommended for release builds. This option is default set to 0. 606 607- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 608 flag depends on ``DECRYPTION_SUPPORT`` build flag. 609 610- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 611 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 612 613- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 614 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 615 on ``DECRYPTION_SUPPORT`` build flag. 616 617- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 618 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 619 build flag. 620 621- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 622 deprecated platform APIs, helper functions or drivers within Trusted 623 Firmware as error. It can take the value 1 (flag the use of deprecated 624 APIs as error) or 0. The default is 0. 625 626- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can 627 configure an Arm® Ethos™-N NPU. To use this service the target platform's 628 ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only 629 the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform 630 only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. 631 632- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the 633 Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and 634 ``TRUSTED_BOARD_BOOT`` to be enabled. 635 636- ``ETHOSN_NPU_FW``: location of the NPU firmware binary 637 (```ethosn.bin```). This firmware image will be included in the FIP and 638 loaded at runtime. 639 640- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 641 targeted at EL3. When set ``0`` (default), no exceptions are expected or 642 handled at EL3, and a panic will result. The exception to this rule is when 643 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 644 occuring during normal world execution, are trapped to EL3. Any exception 645 trapped during secure world execution are trapped to the SPMC. This is 646 supported only for AArch64 builds. 647 648- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 649 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 650 Default value is 40 (LOG_LEVEL_INFO). 651 652- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 653 injection from lower ELs, and this build option enables lower ELs to use 654 Error Records accessed via System Registers to inject faults. This is 655 applicable only to AArch64 builds. 656 657 This feature is intended for testing purposes only, and is advisable to keep 658 disabled for production images. 659 660- ``FIP_NAME``: This is an optional build option which specifies the FIP 661 filename for the ``fip`` target. Default is ``fip.bin``. 662 663- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 664 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 665 666- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 667 668 :: 669 670 0: Encryption is done with Secret Symmetric Key (SSK) which is common 671 for a class of devices. 672 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 673 unique per device. 674 675 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 676 677- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 678 tool to create certificates as per the Chain of Trust described in 679 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 680 include the certificates in the FIP and FWU_FIP. Default value is '0'. 681 682 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 683 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 684 the corresponding certificates, and to include those certificates in the 685 FIP and FWU_FIP. 686 687 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 688 images will not include support for Trusted Board Boot. The FIP will still 689 include the corresponding certificates. This FIP can be used to verify the 690 Chain of Trust on the host machine through other mechanisms. 691 692 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 693 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 694 will not include the corresponding certificates, causing a boot failure. 695 696- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 697 inherent support for specific EL3 type interrupts. Setting this build option 698 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 699 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 700 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 701 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 702 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 703 the Secure Payload interrupts needs to be synchronously handed over to Secure 704 EL1 for handling. The default value of this option is ``0``, which means the 705 Group 0 interrupts are assumed to be handled by Secure EL1. 706 707- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 708 Interrupts, resulting from errors in NS world, will be always trapped in 709 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 710 will be trapped in the current exception level (or in EL1 if the current 711 exception level is EL0). 712 713- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 714 software operations are required for CPUs to enter and exit coherency. 715 However, newer systems exist where CPUs' entry to and exit from coherency 716 is managed in hardware. Such systems require software to only initiate these 717 operations, and the rest is managed in hardware, minimizing active software 718 management. In such systems, this boolean option enables TF-A to carry out 719 build and run-time optimizations during boot and power management operations. 720 This option defaults to 0 and if it is enabled, then it implies 721 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 722 723 If this flag is disabled while the platform which TF-A is compiled for 724 includes cores that manage coherency in hardware, then a compilation error is 725 generated. This is based on the fact that a system cannot have, at the same 726 time, cores that manage coherency in hardware and cores that don't. In other 727 words, a platform cannot have, at the same time, cores that require 728 ``HW_ASSISTED_COHERENCY=1`` and cores that require 729 ``HW_ASSISTED_COHERENCY=0``. 730 731 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 732 translation library (xlat tables v2) must be used; version 1 of translation 733 library is not supported. 734 735- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for 736 implementation defined system register accesses from lower ELs. Default 737 value is ``0``. 738 739- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 740 bottom, higher addresses at the top. This build flag can be set to '1' to 741 invert this behavior. Lower addresses will be printed at the top and higher 742 addresses at the bottom. 743 744- ``INIT_UNUSED_NS_EL2``: This build flag guards code that disables EL2 745 safely in scenario where NS-EL2 is present but unused. This flag is set to 0 746 by default. Platforms without NS-EL2 in use must enable this flag. 747 748- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 749 used for generating the PKCS keys and subsequent signing of the certificate. 750 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 751 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 752 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 753 compatibility. The default value of this flag is ``rsa`` which is the TBBR 754 compliant PKCS#1 RSA 2.1 scheme. 755 756- ``KEY_SIZE``: This build flag enables the user to select the key size for 757 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 758 depend on the chosen algorithm and the cryptographic module. 759 760 +---------------------------+------------------------------------+ 761 | KEY_ALG | Possible key sizes | 762 +===========================+====================================+ 763 | rsa | 1024 , 2048 (default), 3072, 4096 | 764 +---------------------------+------------------------------------+ 765 | ecdsa | 256 (default), 384 | 766 +---------------------------+------------------------------------+ 767 | ecdsa-brainpool-regular | 256 (default) | 768 +---------------------------+------------------------------------+ 769 | ecdsa-brainpool-twisted | 256 (default) | 770 +---------------------------+------------------------------------+ 771 772- ``HASH_ALG``: This build flag enables the user to select the secure hash 773 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 774 The default value of this flag is ``sha256``. 775 776- ``LDFLAGS``: Extra user options appended to the linkers' command line in 777 addition to the one set by the build system. 778 779- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 780 output compiled into the build. This should be one of the following: 781 782 :: 783 784 0 (LOG_LEVEL_NONE) 785 10 (LOG_LEVEL_ERROR) 786 20 (LOG_LEVEL_NOTICE) 787 30 (LOG_LEVEL_WARNING) 788 40 (LOG_LEVEL_INFO) 789 50 (LOG_LEVEL_VERBOSE) 790 791 All log output up to and including the selected log level is compiled into 792 the build. The default value is 40 in debug builds and 20 in release builds. 793 794- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 795 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 796 provide trust that the code taking the measurements and recording them has 797 not been tampered with. 798 799 This option defaults to 0. 800 801- ``DISCRETE_TPM``: Boolean flag to include support for a Discrete TPM. 802 803 This option defaults to 0. 804 805- ``TPM_INTERFACE``: When ``DISCRETE_TPM=1``, this is a required flag to 806 select the TPM interface. Currently only one interface is supported: 807 808 :: 809 810 FIFO_SPI 811 812- ``MBOOT_TPM_HASH_ALG``: Build flag to select the TPM hash algorithm used during 813 Measured Boot. Currently only accepts ``sha256`` as a valid algorithm. 814 815- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build 816 options to the compiler. An example usage: 817 818 .. code:: make 819 820 MARCH_DIRECTIVE := -march=armv8.5-a 821 822- ``HARDEN_SLS``: used to pass -mharden-sls=all from the TF-A build 823 options to the compiler currently supporting only of the options. 824 GCC documentation: 825 https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mharden-sls 826 827 An example usage: 828 829 .. code:: make 830 831 HARDEN_SLS := 1 832 833 This option defaults to 0. 834 835- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 836 specifies a file that contains the Non-Trusted World private key in PEM 837 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and it 838 will be used to save the key. 839 840- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 841 optional. It is only needed if the platform makefile specifies that it 842 is required in order to build the ``fwu_fip`` target. 843 844- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 845 contents upon world switch. It can take either 0 (don't save and restore) or 846 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 847 wants the timer registers to be saved and restored. 848 849- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 850 for the BL image. It can be either 0 (include) or 1 (remove). The default 851 value is 0. 852 853- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 854 the underlying hardware is not a full PL011 UART but a minimally compliant 855 generic UART, which is a subset of the PL011. The driver will not access 856 any register that is not part of the SBSA generic UART specification. 857 Default value is 0 (a full PL011 compliant UART is present). 858 859- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 860 must be subdirectory of any depth under ``plat/``, and must contain a 861 platform makefile named ``platform.mk``. For example, to build TF-A for the 862 Arm Juno board, select PLAT=juno. 863 864- ``PLATFORM_REPORT_CTX_MEM_USE``: Reports the context memory allocated for 865 each core as well as the global context. The data includes the memory used 866 by each world and each privileged exception level. This build option is 867 applicable only for ``ARCH=aarch64`` builds. The default value is 0. 868 869- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 870 instead of the normal boot flow. When defined, it must specify the entry 871 point address for the preloaded BL33 image. This option is incompatible with 872 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 873 over ``PRELOADED_BL33_BASE``. 874 875- ``PRESERVE_DSU_PMU_REGS``: This options when enabled allows the platform to 876 save/restore the DynamIQ Shared Unit's(DSU) Performance Monitoring Unit(PMU) 877 registers when the cluster goes through a power cycle. This is disabled by 878 default and platforms that require this feature have to enable them. 879 880- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 881 vector address can be programmed or is fixed on the platform. It can take 882 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 883 programmable reset address, it is expected that a CPU will start executing 884 code directly at the right address, both on a cold and warm reset. In this 885 case, there is no need to identify the entrypoint on boot and the boot path 886 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 887 does not need to be implemented in this case. 888 889- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 890 possible for the PSCI power-state parameter: original and extended State-ID 891 formats. This flag if set to 1, configures the generic PSCI layer to use the 892 extended format. The default value of this flag is 0, which means by default 893 the original power-state format is used by the PSCI implementation. This flag 894 should be specified by the platform makefile and it governs the return value 895 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 896 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 897 set to 1 as well. 898 899- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 900 OS-initiated mode. This option defaults to 0. 901 902- ``ARCH_FEATURE_AVAILABILITY``: Boolean flag to enable support for the 903 optional SMCCC_ARCH_FEATURE_AVAILABILITY call. This option implicitly 904 interacts with IMPDEF_SYSREG_TRAP and software emulation. This option 905 defaults to 0. 906 907- ``ENABLE_FEAT_RAS``: Boolean flag to enable Armv8.2 RAS features. RAS features 908 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 909 or later CPUs. This flag can take the values 0 or 1. The default value is 0. 910 NOTE: This flag enables use of IESB capability to reduce entry latency into 911 EL3 even when RAS error handling is not performed on the platform. Hence this 912 flag is recommended to be turned on Armv8.2 and later CPUs. 913 914- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 915 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 916 entrypoint) or 1 (CPU reset to BL31 entrypoint). 917 The default value is 0. 918 919- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 920 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 921 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 922 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 923 924- ``RME_GPT_BITLOCK_BLOCK``: This defines the block size (in number of 512MB 925- blocks) covered by a single bit of the bitlock structure during RME GPT 926- operations. The lower the block size, the better opportunity for 927- parallelising GPT operations but at the cost of more bits being needed 928- for the bitlock structure. This numeric parameter can take the values 929- from 0 to 512 and must be a power of 2. The value of 0 is special and 930- and it chooses a single spinlock for all GPT L1 table entries. Default 931- value is 1 which corresponds to block size of 512MB per bit of bitlock 932- structure. 933 934- ``RME_GPT_MAX_BLOCK``: Numeric value in MB to define the maximum size of 935 supported contiguous blocks in GPT Library. This parameter can take the 936 values 0, 2, 32 and 512. Setting this value to 0 disables use of Contigious 937 descriptors. Default value is 512. 938 939- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 940 file that contains the ROT private key in PEM format or a PKCS11 URI and 941 enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is 942 accepted and it will be used to save the key. 943 944- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 945 certificate generation tool to save the keys used to establish the Chain of 946 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 947 948- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 949 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 950 target. 951 952- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 953 file that contains the SCP_BL2 private key in PEM format or a PKCS11 URI. 954 If ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 955 956- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 957 optional. It is only needed if the platform makefile specifies that it 958 is required in order to build the ``fwu_fip`` target. 959 960- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 961 Delegated Exception Interface to BL31 image. This defaults to ``0``. 962 963 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 964 set to ``1``. 965 966- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 967 isolated on separate memory pages. This is a trade-off between security and 968 memory usage. See "Isolating code and read-only data on separate memory 969 pages" section in :ref:`Firmware Design`. This flag is disabled by default 970 and affects all BL images. 971 972- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 973 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 974 allocated in RAM discontiguous from the loaded firmware image. When set, the 975 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 976 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 977 sections are placed in RAM immediately following the loaded firmware image. 978 979- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 980 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 981 discontiguous from loaded firmware images. When set, the platform need to 982 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 983 flag is disabled by default and NOLOAD sections are placed in RAM immediately 984 following the loaded firmware image. 985 986- ``SEPARATE_SIMD_SECTION``: Setting this option to ``1`` allows the SIMD context 987 data structures to be put in a dedicated memory region as decided by platform 988 integrator. Default value is ``0`` which means the SIMD context is put in BSS 989 section of EL3 firmware. 990 991- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 992 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 993 UEFI+ACPI this can provide a certain amount of OS forward compatibility 994 with newer platforms that aren't ECAM compliant. 995 996- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 997 This build option is only valid if ``ARCH=aarch64``. The value should be 998 the path to the directory containing the SPD source, relative to 999 ``services/spd/``; the directory is expected to contain a makefile called 1000 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 1001 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 1002 cannot be enabled when the ``SPM_MM`` option is enabled. 1003 1004- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 1005 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 1006 execution in BL1 just before handing over to BL31. At this point, all 1007 firmware images have been loaded in memory, and the MMU and caches are 1008 turned off. Refer to the "Debugging options" section for more details. 1009 1010- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 1011 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 1012 component runs at the EL3 exception level. The default value is ``0`` ( 1013 disabled). This configuration supports pre-Armv8.4 platforms (aka not 1014 implementing the ``FEAT_SEL2`` extension). 1015 1016- ``SPMC_AT_EL3_SEL0_SP`` : Boolean option to enable SEL0 SP load support when 1017 ``SPMC_AT_EL3`` is enabled. The default value if ``0`` (disabled). This 1018 option cannot be enabled (``1``) when (``SPMC_AT_EL3``) is disabled. 1019 1020- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 1021 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 1022 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 1023 mechanism should be used. 1024 1025- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 1026 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 1027 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 1028 extension. This is the default when enabling the SPM Dispatcher. When 1029 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 1030 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 1031 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 1032 extension). 1033 1034- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 1035 Partition Manager (SPM) implementation. The default value is ``0`` 1036 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 1037 enabled (``SPD=spmd``). 1038 1039- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 1040 description of secure partitions. The build system will parse this file and 1041 package all secure partition blobs into the FIP. This file is not 1042 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 1043 1044- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 1045 secure interrupts (caught through the FIQ line). Platforms can enable 1046 this directive if they need to handle such interruption. When enabled, 1047 the FIQ are handled in monitor mode and non secure world is not allowed 1048 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 1049 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 1050 1051- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 1052 Platforms can configure this if they need to lower the hardware 1053 limit, for example due to asymmetric configuration or limitations of 1054 software run at lower ELs. The default is the architectural maximum 1055 of 2048 which should be suitable for most configurations, the 1056 hardware will limit the effective VL to the maximum physically supported 1057 VL. 1058 1059- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 1060 Random Number Generator Interface to BL31 image. This defaults to ``0``. 1061 1062- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 1063 Boot feature. When set to '1', BL1 and BL2 images include support to load 1064 and verify the certificates and images in a FIP, and BL1 includes support 1065 for the Firmware Update. The default value is '0'. Generation and inclusion 1066 of certificates in the FIP and FWU_FIP depends upon the value of the 1067 ``GENERATE_COT`` option. 1068 1069 .. warning:: 1070 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 1071 already exist in disk, they will be overwritten without further notice. 1072 1073- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 1074 specifies a file that contains the Trusted World private key in PEM 1075 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and 1076 it will be used to save the key. 1077 1078- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 1079 synchronous, (see "Initializing a BL32 Image" section in 1080 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 1081 synchronous method) or 1 (BL32 is initialized using asynchronous method). 1082 Default is 0. 1083 1084- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 1085 routing model which routes non-secure interrupts asynchronously from TSP 1086 to EL3 causing immediate preemption of TSP. The EL3 is responsible 1087 for saving and restoring the TSP context in this routing model. The 1088 default routing model (when the value is 0) is to route non-secure 1089 interrupts to TSP allowing it to save its context and hand over 1090 synchronously to EL3 via an SMC. 1091 1092 .. note:: 1093 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 1094 must also be set to ``1``. 1095 1096- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and 1097 internal-trusted-storage) as SP in tb_fw_config device tree. 1098 1099- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 1100 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 1101 this delay. It can take values in the range (0-15). Default value is ``0`` 1102 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 1103 Platforms need to explicitly update this value based on their requirements. 1104 1105- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 1106 linker. When the ``LINKER`` build variable points to the armlink linker, 1107 this flag is enabled automatically. To enable support for armlink, platforms 1108 will have to provide a scatter file for the BL image. Currently, Tegra 1109 platforms use the armlink support to compile BL3-1 images. 1110 1111- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 1112 memory region in the BL memory map or not (see "Use of Coherent memory in 1113 TF-A" section in :ref:`Firmware Design`). It can take the value 1 1114 (Coherent memory region is included) or 0 (Coherent memory region is 1115 excluded). Default is 1. 1116 1117- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 1118 firmware configuration framework. This will move the io_policies into a 1119 configuration device tree, instead of static structure in the code base. 1120 1121- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 1122 at runtime using fconf. If this flag is enabled, COT descriptors are 1123 statically captured in tb_fw_config file in the form of device tree nodes 1124 and properties. Currently, COT descriptors used by BL2 are moved to the 1125 device tree and COT descriptors used by BL1 are retained in the code 1126 base statically. 1127 1128- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 1129 runtime using firmware configuration framework. The platform specific SDEI 1130 shared and private events configuration is retrieved from device tree rather 1131 than static C structures at compile time. This is only supported if 1132 SDEI_SUPPORT build flag is enabled. 1133 1134- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 1135 and Group1 secure interrupts using the firmware configuration framework. The 1136 platform specific secure interrupt property descriptor is retrieved from 1137 device tree in runtime rather than depending on static C structure at compile 1138 time. 1139 1140- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 1141 This feature creates a library of functions to be placed in ROM and thus 1142 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 1143 is 0. 1144 1145- ``V``: Verbose build. If assigned anything other than 0, the build commands 1146 are printed. Default is 0. 1147 1148- ``VERSION_STRING``: String used in the log output for each TF-A image. 1149 Defaults to a string formed by concatenating the version number, build type 1150 and build string. 1151 1152- ``W``: Warning level. Some compiler warning options of interest have been 1153 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 1154 each level enabling more warning options. Default is 0. 1155 1156 This option is closely related to the ``E`` option, which enables 1157 ``-Werror``. 1158 1159 - ``W=0`` (default) 1160 1161 Enables a wide assortment of warnings, most notably ``-Wall`` and 1162 ``-Wextra``, as well as various bad practices and things that are likely to 1163 result in errors. Includes some compiler specific flags. No warnings are 1164 expected at this level for any build. 1165 1166 - ``W=1`` 1167 1168 Enables warnings we want the generic build to include but are too time 1169 consuming to fix at the moment. It re-enables warnings taken out for 1170 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1171 to eventually be merged into ``W=0``. Some warnings are expected on some 1172 builds, but new contributions should not introduce new ones. 1173 1174 - ``W=2`` (recommended) 1175 1176 Enables warnings we want the generic build to include but cannot be enabled 1177 due to external libraries. This level is expected to eventually be merged 1178 into ``W=0``. Lots of warnings are expected, primarily from external 1179 libraries like zlib and compiler-rt, but new controbutions should not 1180 introduce new ones. 1181 1182 - ``W=3`` 1183 1184 Enables warnings that are informative but not necessary and generally too 1185 verbose and frequently ignored. A very large number of warnings are 1186 expected. 1187 1188 The exact set of warning flags depends on the compiler and TF-A warning 1189 level, however they are all succinctly set in the top-level Makefile. Please 1190 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1191 individual flags. 1192 1193- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1194 the CPU after warm boot. This is applicable for platforms which do not 1195 require interconnect programming to enable cache coherency (eg: single 1196 cluster platforms). If this option is enabled, then warm boot path 1197 enables D-caches immediately after enabling MMU. This option defaults to 0. 1198 1199- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 1200 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 1201 default value of this flag is ``no``. Note this option must be enabled only 1202 for ARM architecture greater than Armv8.5-A. 1203 1204- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1205 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1206 The default value of this flag is ``0``. 1207 1208 ``AT`` speculative errata workaround disables stage1 page table walk for 1209 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1210 produces either the correct result or failure without TLB allocation. 1211 1212 This boolean option enables errata for all below CPUs. 1213 1214 +---------+--------------+-------------------------+ 1215 | Errata | CPU | Workaround Define | 1216 +=========+==============+=========================+ 1217 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1218 +---------+--------------+-------------------------+ 1219 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1220 +---------+--------------+-------------------------+ 1221 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1222 +---------+--------------+-------------------------+ 1223 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1224 +---------+--------------+-------------------------+ 1225 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1226 +---------+--------------+-------------------------+ 1227 1228 .. note:: 1229 This option is enabled by build only if platform sets any of above defines 1230 mentioned in ’Workaround Define' column in the table. 1231 If this option is enabled for the EL3 software then EL2 software also must 1232 implement this workaround due to the behaviour of the errata mentioned 1233 in new SDEN document which will get published soon. 1234 1235- ``ERRATA_SME_POWER_DOWN``: Boolean option to disable SME (PSTATE.{ZA,SM}=0) 1236 before power down and downgrade a suspend to power down request to a normal 1237 suspend request. This is necessary when software running at lower ELs requests 1238 power down without first clearing these bits. On affected cores, the CME 1239 connected to it will reject its power down request. The default value is 0. 1240 1241- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1242 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1243 This flag is disabled by default. 1244 1245- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1246 host machine where a custom installation of OpenSSL is located, which is used 1247 to build the certificate generation, firmware encryption and FIP tools. If 1248 this option is not set, the default OS installation will be used. 1249 1250- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1251 functions that wait for an arbitrary time length (udelay and mdelay). The 1252 default value is 0. 1253 1254- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1255 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1256 optional architectural feature for AArch64. This flag can take the values 1257 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0 1258 and it is automatically disabled when the target architecture is AArch32. 1259 1260- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1261 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1262 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1263 feature for AArch64. This flag can take the values 0 to 2, to align with the 1264 ``ENABLE_FEAT`` mechanism. The default is 0 and it is automatically 1265 disabled when the target architecture is AArch32. 1266 1267- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1268 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1269 but unused). This feature is available if trace unit such as ETMv4.x, and 1270 ETE(extending ETM feature) is implemented. This flag can take the values 1271 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0. 1272 1273- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1274 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1275 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1276 with the ``ENABLE_FEAT`` mechanism. This flag is disabled by default. 1277 1278- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1279 ``plat_can_cmo`` which will return zero if cache management operations should 1280 be skipped and non-zero otherwise. By default, this option is disabled which 1281 means platform hook won't be checked and CMOs will always be performed when 1282 related functions are called. 1283 1284- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management 1285 firmware interface for the BL31 image. By default its disabled (``0``). 1286 1287- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the 1288 errata mitigation for platforms with a non-arm interconnect using the errata 1289 ABI. By default its disabled (``0``). 1290 1291- ``ENABLE_CONSOLE_GETC``: Boolean option to enable `getc()` feature in console 1292 driver(s). By default it is disabled (``0``) because it constitutes an attack 1293 vector into TF-A by potentially allowing an attacker to inject arbitrary data. 1294 This option should only be enabled on a need basis if there is a use case for 1295 reading characters from the console. 1296 1297GIC driver options 1298-------------------- 1299 1300The generic GIC driver can be included with the ``USE_GIC_DRIVER`` option. It is 1301a numeric option that can take the following values: 1302 1303 - ``0``: generic GIC driver not enabled. Any support is entirely in platform 1304 code. Strongly discouraged for GIC based interrupt controllers. 1305 1306 - ``1``: enable the use of the generic GIC driver but do not include any files 1307 or function definitions. It is then the platform's responsibility to provide 1308 these. This is useful if the platform either has a custom GIC implementation 1309 or an alternative interrupt controller design. Use of this option is strongly 1310 discouraged for standard GIC implementations. 1311 1312 - ``2``: use the GICv2 driver 1313 1314 - ``3``: use the GICv3 driver. See the next section on how to further configure 1315 it. Use this option for GICv4 implementations. 1316 1317 For GIC driver versions other than ``1``, deciding when to save and restore GIC 1318 context on a power domain state transition, as well as any GIC actions outside 1319 of the PSCI library's visibility are the platform's responsibility. The driver 1320 provides implementations of all necessary subroutines, they only need to be 1321 called as appropriate. 1322 1323GICv3 driver options 1324~~~~~~~~~~~~~~~~~~~~ 1325 1326``USE_GIC_DRIVER=3`` is the preferred way of including GICv3 driver files. The 1327old (deprecated) way of included them is using the directive: 1328``include drivers/arm/gic/v3/gicv3.mk`` 1329 1330The driver can be configured with the following options set in the platform 1331makefile: 1332 1333- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1334 Enabling this option will add runtime detection support for the 1335 GIC-600, so is safe to select even for a GIC500 implementation. 1336 This option defaults to 0. 1337 1338- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1339 for GIC-600 AE. Enabling this option will introduce support to initialize 1340 the FMU. Platforms should call the init function during boot to enable the 1341 FMU and its safety mechanisms. This option defaults to 0. 1342 1343- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1344 functionality. This option defaults to 0 1345 1346- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1347 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1348 functions. This is required for FVP platform which need to simulate GIC save 1349 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1350 1351- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1352 This option defaults to 0. 1353 1354- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1355 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1356 1357Debugging options 1358----------------- 1359 1360To compile a debug version and make the build more verbose use 1361 1362.. code:: shell 1363 1364 make PLAT=<platform> DEBUG=1 V=1 all 1365 1366AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1367(for example Arm-DS) might not support this and may need an older version of 1368DWARF symbols to be emitted by GCC. This can be achieved by using the 1369``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1370the version to 4 is recommended for Arm-DS. 1371 1372When debugging logic problems it might also be useful to disable all compiler 1373optimizations by using ``-O0``. 1374 1375.. warning:: 1376 Using ``-O0`` could cause output images to be larger and base addresses 1377 might need to be recalculated (see the **Memory layout on Arm development 1378 platforms** section in the :ref:`Firmware Design`). 1379 1380Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1381``LDFLAGS``: 1382 1383.. code:: shell 1384 1385 CFLAGS='-O0 -gdwarf-2' \ 1386 make PLAT=<platform> DEBUG=1 V=1 all 1387 1388Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1389ignored as the linker is called directly. 1390 1391It is also possible to introduce an infinite loop to help in debugging the 1392post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1393``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1394section. In this case, the developer may take control of the target using a 1395debugger when indicated by the console output. When using Arm-DS, the following 1396commands can be used: 1397 1398:: 1399 1400 # Stop target execution 1401 interrupt 1402 1403 # 1404 # Prepare your debugging environment, e.g. set breakpoints 1405 # 1406 1407 # Jump over the debug loop 1408 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1409 1410 # Resume execution 1411 continue 1412 1413.. _build_options_experimental: 1414 1415Experimental build options 1416--------------------------- 1417 1418Common build options 1419~~~~~~~~~~~~~~~~~~~~ 1420 1421- ``DICE_PROTECTION_ENVIRONMENT``: Boolean flag to specify the measured boot 1422 backend when ``MEASURED_BOOT`` is enabled. The default value is ``0``. When 1423 set to ``1`` then measurements and additional metadata collected during the 1424 measured boot process are sent to the DICE Protection Environment for storage 1425 and processing. A certificate chain, which represents the boot state of the 1426 device, can be queried from the DPE. 1427 1428- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 1429 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 1430 the measurements and recording them as per `PSA DRTM specification`_. For 1431 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 1432 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 1433 should have mechanism to authenticate BL31. This option defaults to 0. 1434 1435- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 1436 Management Extension. This flag can take the values 0 to 2, to align with 1437 the ``ENABLE_FEAT`` mechanism. Default value is 0. 1438 1439- ``ENABLE_FEAT_MEC``: Numeric value to enable support for the ARMv9.2 Memory 1440 Encryption Contexts (MEC). This flag can take the values 0 to 2, to align 1441 with the ``ENABLE_FEAT`` mechanism. MEC supports multiple encryption 1442 contexts for Realm security state and only one encryption context for the 1443 rest of the security states. Default value is 0. 1444 1445- ``RMMD_ENABLE_EL3_TOKEN_SIGN``: Numeric value to enable support for singing 1446 realm attestation token signing requests in EL3. This flag can take the 1447 values 0 and 1. The default value is ``0``. When set to ``1``, this option 1448 enables additional RMMD SMCs to push and pop requests for signing to 1449 EL3 along with platform hooks that must be implemented to service those 1450 requests and responses. 1451 1452- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1453 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 1454 registers so are enabled together. Using this option without 1455 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 1456 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a 1457 superset of SVE. SME is an optional architectural feature for AArch64. 1458 At this time, this build option cannot be used on systems that have 1459 SPD=spmd/SPM_MM and atempting to build with this option will fail. 1460 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 1461 mechanism. Default is 0. 1462 1463- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1464 version 2 (SME2) for the non-secure world only. SME2 is an optional 1465 architectural feature for AArch64. 1466 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME 1467 accesses will still be trapped. This flag can take the values 0 to 2, to 1468 align with the ``ENABLE_FEAT`` mechanism. Default is 0. 1469 1470- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 1471 Extension for secure world. Used along with SVE and FPU/SIMD. 1472 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. 1473 Default is 0. 1474 1475- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM 1476 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support 1477 for logical partitions in EL3, managed by the SPMD as defined in the 1478 FF-A v1.2 specification. This flag is disabled by default. This flag 1479 must not be used if ``SPMC_AT_EL3`` is enabled. 1480 1481- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 1482 verification mechanism. This is a debug feature that compares the 1483 architectural features enabled through the feature specific build flags 1484 (ENABLE_FEAT_xxx) with the features actually available on the CPU running, 1485 and reports any discrepancies. 1486 This flag will also enable errata ordering checking for ``DEBUG`` builds. 1487 1488 It is expected that this feature is only used for flexible platforms like 1489 software emulators, or for hardware platforms at bringup time, to verify 1490 that the configured feature set matches the CPU. 1491 The ``FEATURE_DETECTION`` macro is disabled by default. 1492 1493- ``PSA_CRYPTO``: Boolean option for enabling MbedTLS PSA crypto APIs support. 1494 The platform will use PSA compliant Crypto APIs during authentication and 1495 image measurement process by enabling this option. It uses APIs defined as 1496 per the `PSA Crypto API specification`_. This feature is only supported if 1497 using MbedTLS 3.x version. It is disabled (``0``) by default. 1498 1499- ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware 1500 Handoff using Transfer List defined in `Firmware Handoff specification`_. 1501 This defaults to ``0``. Current implementation follows the Firmware Handoff 1502 specification v0.9. 1503 1504- ``USE_DEBUGFS``: When set to 1 this option exposes a virtual filesystem 1505 interface through BL31 as a SiP SMC function. 1506 Default is disabled (0). 1507 1508- ``HOB_LIST``: Setting this to ``1`` enables support for passing boot 1509 information using HOB defined in `Platform Initialization specification`_. 1510 This defaults to ``0``. 1511 1512- ``ENABLE_ACS_SMC``: When set to ``1``, this enables support for ACS SMC 1513 handler code to handle SMC calls from the Architecture Compliance Suite. The 1514 handler is intentionally empty to reserve the SMC section and allow 1515 project-specific implementations in future ACS use cases. 1516 1517Firmware update options 1518~~~~~~~~~~~~~~~~~~~~~~~ 1519 1520- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1521 `PSA FW update specification`_. The default value is 0. 1522 PSA firmware update implementation has few limitations, such as: 1523 1524 - BL2 is not part of the protocol-updatable images. If BL2 needs to 1525 be updated, then it should be done through another platform-defined 1526 mechanism. 1527 1528 - It assumes the platform's hardware supports CRC32 instructions. 1529 1530- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1531 in defining the firmware update metadata structure. This flag is by default 1532 set to '2'. 1533 1534- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1535 firmware bank. Each firmware bank must have the same number of images as per 1536 the `PSA FW update specification`_. 1537 This flag is used in defining the firmware update metadata structure. This 1538 flag is by default set to '1'. 1539 1540- ``PSA_FWU_METADATA_FW_STORE_DESC``: To be enabled when the FWU 1541 metadata contains image description. The default value is 1. 1542 1543 The version 2 of the FWU metadata allows for an opaque metadata 1544 structure where a platform can choose to not include the firmware 1545 store description in the metadata structure. This option indicates 1546 if the firmware store description, which provides information on 1547 the updatable images is part of the structure. 1548 1549-------------- 1550 1551*Copyright (c) 2019-2025, Arm Limited. All rights reserved.* 1552 1553.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1554.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/latest/ 1555.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1556.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1557.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1558.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9 1559.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/ 1560.. _Platform Initialization specification: https://uefi.org/specs/PI/1.8/index.html 1561