1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. Reads from the 27 memory mapped view are unaffected by this control. 28 29- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 30 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 31 ``aarch64``. 32 33- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 34 one or more feature modifiers. This option has the form ``[no]feature+...`` 35 and defaults to ``none``. It translates into compiler option 36 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 37 list of supported feature modifiers. 38 39- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 40 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 41 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 42 :ref:`Firmware Design`. 43 44- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 45 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 46 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 47 48- ``BL2``: This is an optional build option which specifies the path to BL2 49 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 50 built. 51 52- ``BL2U``: This is an optional build option which specifies the path to 53 BL2U image. In this case, the BL2U in TF-A will not be built. 54 55- ``BL2_AT_EL3``: This is an optional build option that enables the use of 56 BL2 at EL3 execution level. 57 58- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 59 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 60 61- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 62 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 63 the RW sections in RAM, while leaving the RO sections in place. This option 64 enable this use-case. For now, this option is only supported when BL2_AT_EL3 65 is set to '1'. 66 67- ``BL31``: This is an optional build option which specifies the path to 68 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 69 be built. 70 71- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 72 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, 73 this file name will be used to save the key. 74 75- ``BL32``: This is an optional build option which specifies the path to 76 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 77 be built. 78 79- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 80 Trusted OS Extra1 image for the ``fip`` target. 81 82- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 83 Trusted OS Extra2 image for the ``fip`` target. 84 85- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 86 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, 87 this file name will be used to save the key. 88 89- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 90 ``fip`` target in case TF-A BL2 is used. 91 92- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 93 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, 94 this file name will be used to save the key. 95 96- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 97 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 98 If enabled, it is needed to use a compiler that supports the option 99 ``-mbranch-protection``. Selects the branch protection features to use: 100- 0: Default value turns off all types of branch protection 101- 1: Enables all types of branch protection features 102- 2: Return address signing to its standard level 103- 3: Extend the signing to include leaf functions 104- 4: Turn on branch target identification mechanism 105 106 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 107 and resulting PAuth/BTI features. 108 109 +-------+--------------+-------+-----+ 110 | Value | GCC option | PAuth | BTI | 111 +=======+==============+=======+=====+ 112 | 0 | none | N | N | 113 +-------+--------------+-------+-----+ 114 | 1 | standard | Y | Y | 115 +-------+--------------+-------+-----+ 116 | 2 | pac-ret | Y | N | 117 +-------+--------------+-------+-----+ 118 | 3 | pac-ret+leaf | Y | N | 119 +-------+--------------+-------+-----+ 120 | 4 | bti | N | Y | 121 +-------+--------------+-------+-----+ 122 123 This option defaults to 0. 124 Note that Pointer Authentication is enabled for Non-secure world 125 irrespective of the value of this option if the CPU supports it. 126 127- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 128 compilation of each build. It must be set to a C string (including quotes 129 where applicable). Defaults to a string that contains the time and date of 130 the compilation. 131 132- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 133 build to be uniquely identified. Defaults to the current git commit id. 134 135- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 136 137- ``CFLAGS``: Extra user options appended on the compiler's command line in 138 addition to the options set by the build system. 139 140- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 141 release several CPUs out of reset. It can take either 0 (several CPUs may be 142 brought up) or 1 (only one CPU will ever be brought up during cold reset). 143 Default is 0. If the platform always brings up a single CPU, there is no 144 need to distinguish between primary and secondary CPUs and the boot path can 145 be optimised. The ``plat_is_my_cpu_primary()`` and 146 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 147 to be implemented in this case. 148 149- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 150 Defaults to ``tbbr``. 151 152- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 153 register state when an unexpected exception occurs during execution of 154 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 155 this is only enabled for a debug build of the firmware. 156 157- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 158 certificate generation tool to create new keys in case no valid keys are 159 present or specified. Allowed options are '0' or '1'. Default is '1'. 160 161- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 162 the AArch32 system registers to be included when saving and restoring the 163 CPU context. The option must be set to 0 for AArch64-only platforms (that 164 is on hardware that does not implement AArch32, or at least not at EL1 and 165 higher ELs). Default value is 1. 166 167- ``CTX_INCLUDE_EL2_REGS`` : This boolean option provides context save/restore 168 operations when entering/exiting an EL2 execution context. This is of primary 169 interest when Armv8.4-SecEL2 extension is implemented. Default is 0 (disabled). 170 This option must be equal to 1 (enabled) when ``SPD=spmd`` and 171 ``SPMD_SPM_AT_SEL2`` is set. 172 173- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 174 registers to be included when saving and restoring the CPU context. Default 175 is 0. 176 177- ``CTX_INCLUDE_MTE_REGS``: Numeric value to include Memory Tagging Extension 178 registers in cpu context. This must be enabled, if the platform wants to use 179 this feature in the Secure world and MTE is enabled at ELX. This flag can 180 take values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 181 Default value is 0. 182 183- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 184 registers to be saved/restored when entering/exiting an EL2 execution 185 context. This flag can take values 0 to 2, to align with the 186 ``FEATURE_DETECTION`` mechanism. Default value is 0. 187 188- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 189 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 190 to be included when saving and restoring the CPU context as part of world 191 switch. This flag can take values 0 to 2, to align with ``FEATURE_DETECTION`` 192 mechanism. Default value is 0. 193 194 Note that Pointer Authentication is enabled for Non-secure world irrespective 195 of the value of this flag if the CPU supports it. 196 197- ``DEBUG``: Chooses between a debug and release build. It can take either 0 198 (release) or 1 (debug) as values. 0 is the default. 199 200- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 201 authenticated decryption algorithm to be used to decrypt firmware/s during 202 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 203 this flag is ``none`` to disable firmware decryption which is an optional 204 feature as per TBBR. 205 206- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 207 of the binary image. If set to 1, then only the ELF image is built. 208 0 is the default. 209 210- ``DISABLE_MTPMU``: Boolean option to disable FEAT_MTPMU if implemented 211 (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms 212 that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU, 213 check the latest Arm ARM. 214 215- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 216 Board Boot authentication at runtime. This option is meant to be enabled only 217 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 218 flag has to be enabled. 0 is the default. 219 220- ``E``: Boolean option to make warnings into errors. Default is 1. 221 222- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 223 the normal boot flow. It must specify the entry point address of the EL3 224 payload. Please refer to the "Booting an EL3 payload" section for more 225 details. 226 227- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions. 228 This is an optional architectural feature available on v8.4 onwards. Some 229 v8.2 implementations also implement an AMU and this option can be used to 230 enable this feature on those systems as well. Default is 0. 231 232- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 233 (also known as group 1 counters). These are implementation-defined counters, 234 and as such require additional platform configuration. Default is 0. 235 236- ``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which 237 allows platforms with auxiliary counters to describe them via the 238 ``HW_CONFIG`` device tree blob. Default is 0. 239 240- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 241 are compiled out. For debug builds, this option defaults to 1, and calls to 242 ``assert()`` are left in place. For release builds, this option defaults to 0 243 and calls to ``assert()`` function are compiled out. This option can be set 244 independently of ``DEBUG``. It can also be used to hide any auxiliary code 245 that is only required for the assertion and does not fit in the assertion 246 itself. 247 248- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 249 dumps or not. It is supported in both AArch64 and AArch32. However, in 250 AArch32 the format of the frame records are not defined in the AAPCS and they 251 are defined by the implementation. This implementation of backtrace only 252 supports the format used by GCC when T32 interworking is disabled. For this 253 reason enabling this option in AArch32 will force the compiler to only 254 generate A32 code. This option is enabled by default only in AArch64 debug 255 builds, but this behaviour can be overridden in each platform's Makefile or 256 in the build command line. 257 258- ``ENABLE_FEAT_AMUv1``: Numeric value to enable access to the HAFGRTR_EL2 259 (Hypervisor Activity Monitors Fine-Grained Read Trap Register) during EL2 260 to EL3 context save/restore operations. This flag can take the values 0 to 2, 261 to align with the ``FEATURE_DETECTION`` mechanism. It is an optional feature 262 available on v8.4 and onwards and must be set to either 1 or 2 alongside 263 ``ENABLE_FEAT_FGT``, to access the HAFGRTR_EL2 register. 264 Default value is ``0``. 265 266- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 267 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 268 onwards. This flag can take the values 0 to 2, to align with the 269 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 270 271- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 272 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 273 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 274 optional feature available on Arm v8.0 onwards. This flag can take values 275 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 276 Default value is ``0``. 277 278- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 279 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 280 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 281 and upwards. This flag can take the values 0 to 2, to align with the 282 ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 283 284- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 285 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 286 Physical Offset register) during EL2 to EL3 context save/restore operations. 287 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 288 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 289 mechanism. Default value is ``0``. 290 291- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 292 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 293 Read Trap Register) during EL2 to EL3 context save/restore operations. 294 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 295 This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 296 mechanism. Default value is ``0``. 297 298- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 299 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 300 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 301 mandatory architectural feature and is enabled from v8.7 and upwards. This 302 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 303 mechanism. Default value is ``0``. 304 305- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 306 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 307 permission fault for any privileged data access from EL1/EL2 to virtual 308 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 309 mandatory architectural feature and is enabled from v8.1 and upwards. This 310 flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 311 mechanism. Default value is ``0``. 312 313- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 314 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 315 flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION`` 316 mechanism. Default is ``0``. 317 318- ``ENABLE_FEAT_SB``: Numeric value to enable the ``FEAT_SB`` (Speculation 319 Barrier) extension allowing access to ``sb`` instruction. ``FEAT_SB`` is an 320 optional feature and defaults to ``0`` for pre-Armv8.5 CPUs but are mandatory 321 for Armv8.5 or later CPUs. This flag can take values 0 to 2, to align with 322 ``FEATURE_DETECTION`` mechanism. It is enabled from v8.5 and upwards and if 323 needed could be overidden from platforms explicitly. Default value is ``0``. 324 325- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 326 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 327 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 328 mechanism. Default is ``0``. 329 330- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 331 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 332 available on Arm v8.6. This flag can take values 0 to 2, to align with the 333 ``FEATURE_DETECTION`` mechanism. Default is ``0``. 334 335 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 336 delayed by the amount of value in ``TWED_DELAY``. 337 338- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 339 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 340 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 341 architectural feature and is enabled from v8.1 and upwards. It can take 342 values 0 to 2, to align with the ``FEATURE_DETECTION`` mechanism. 343 Default value is ``0``. 344 345- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 346 support in GCC for TF-A. This option is currently only supported for 347 AArch64. Default is 0. 348 349- ``ENABLE_MPAM_FOR_LOWER_ELS``: Numeric value to enable lower ELs to use MPAM 350 feature. MPAM is an optional Armv8.4 extension that enables various memory 351 system components and resources to define partitions; software running at 352 various ELs can assign themselves to desired partition to control their 353 performance aspects. 354 355 This flag can take values 0 to 2, to align with the ``FEATURE_DETECTION`` 356 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 357 access their own MPAM registers without trapping into EL3. This option 358 doesn't make use of partitioning in EL3, however. Platform initialisation 359 code should configure and use partitions in EL3 as required. This option 360 defaults to ``0``. 361 362- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 363 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 364 firmware to detect and limit high activity events to assist in SoC processor 365 power domain dynamic power budgeting and limit the triggering of whole-rail 366 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 367 368- ``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which 369 allows platforms with cores supporting MPMM to describe them via the 370 ``HW_CONFIG`` device tree blob. Default is 0. 371 372- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 373 support within generic code in TF-A. This option is currently only supported 374 in BL2_AT_EL3, BL31, and BL32 (TSP) for AARCH64 binaries, and in BL32 375 (SP_min) for AARCH32. Default is 0. 376 377- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 378 Measurement Framework(PMF). Default is 0. 379 380- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 381 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 382 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 383 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 384 software. 385 386- ``ENABLE_RME``: Numeric value to enable support for the ARMv9 Realm 387 Management Extension. This flag can take the values 0 to 2, to align with 388 the ``FEATURE_DETECTION`` mechanism. Default value is 0. This is currently 389 an experimental feature. 390 391- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 392 instrumentation which injects timestamp collection points into TF-A to 393 allow runtime performance to be measured. Currently, only PSCI is 394 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 395 as well. Default is 0. 396 397- ``ENABLE_SME_FOR_NS``: Boolean option to enable Scalable Matrix Extension 398 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 399 registers so are enabled together. Using this option without 400 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 401 world to trap to EL3. SME is an optional architectural feature for AArch64 402 and TF-A support is experimental. At this time, this build option cannot be 403 used on systems that have SPD=spmd/SPM_MM or ENABLE_RME, and attempting to 404 build with these options will fail. Default is 0. 405 406- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 407 Extension for secure world use along with SVE and FPU/SIMD, ENABLE_SME_FOR_NS 408 must also be set to use this. If enabling this, the secure world MUST 409 handle context switching for SME, SVE, and FPU/SIMD registers to ensure that 410 no data is leaked to non-secure world. This is experimental. Default is 0. 411 412- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling 413 extensions. This is an optional architectural feature for AArch64. 414 The default is 1 but is automatically disabled when the target architecture 415 is AArch32. 416 417- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension 418 (SVE) for the Non-secure world only. SVE is an optional architectural feature 419 for AArch64. Note that when SVE is enabled for the Non-secure world, access 420 to SIMD and floating-point functionality from the Secure world is disabled by 421 default and controlled with ENABLE_SVE_FOR_SWD. 422 This is to avoid corruption of the Non-secure world data in the Z-registers 423 which are aliased by the SIMD and FP registers. The build option is not 424 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 425 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to 426 1. The default is 1 but is automatically disabled when ENABLE_SME_FOR_NS=1 427 since SME encompasses SVE. At this time, this build option cannot be used on 428 systems that have SPM_MM enabled. 429 430- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. 431 SVE is an optional architectural feature for AArch64. Note that this option 432 requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it 433 is automatically disabled when the target architecture is AArch32. 434 435- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 436 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 437 default value is set to "none". "strong" is the recommended stack protection 438 level if this feature is desired. "none" disables the stack protection. For 439 all values other than "none", the ``plat_get_stack_protector_canary()`` 440 platform hook needs to be implemented. The value is passed as the last 441 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 442 443- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 444 flag depends on ``DECRYPTION_SUPPORT`` build flag. 445 446- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 447 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 448 449- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 450 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 451 on ``DECRYPTION_SUPPORT`` build flag. 452 453- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 454 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 455 build flag. 456 457- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 458 deprecated platform APIs, helper functions or drivers within Trusted 459 Firmware as error. It can take the value 1 (flag the use of deprecated 460 APIs as error) or 0. The default is 0. 461 462- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 463 targeted at EL3. When set ``0`` (default), no exceptions are expected or 464 handled at EL3, and a panic will result. This is supported only for AArch64 465 builds. 466 467- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 468 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 469 Default value is 40 (LOG_LEVEL_INFO). 470 471- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 472 injection from lower ELs, and this build option enables lower ELs to use 473 Error Records accessed via System Registers to inject faults. This is 474 applicable only to AArch64 builds. 475 476 This feature is intended for testing purposes only, and is advisable to keep 477 disabled for production images. 478 479- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 480 detection mechanism. It detects whether the Architectural features enabled 481 through feature specific build flags are supported by the PE or not by 482 validating them either at boot phase or at runtime based on the value 483 possessed by the feature flag (0 to 2) and report error messages at an early 484 stage. 485 486 This prevents and benefits us from EL3 runtime exceptions during context save 487 and restore routines guarded by these build flags. Henceforth validating them 488 before their usage provides more control on the actions taken under them. 489 490 The mechanism permits the build flags to take values 0, 1 or 2 and 491 evaluates them accordingly. 492 493 Lets consider ``ENABLE_FEAT_HCX``, build flag for ``FEAT_HCX`` as an example: 494 495 :: 496 497 ENABLE_FEAT_HCX = 0: Feature disabled statically at compile time. 498 ENABLE_FEAT_HCX = 1: Feature Enabled and the flag is validated at boottime. 499 ENABLE_FEAT_HCX = 2: Feature Enabled and the flag is validated at runtime. 500 501 In the above example, if the feature build flag, ``ENABLE_FEAT_HCX`` set to 502 0, feature is disabled statically during compilation. If it is defined as 1, 503 feature is validated, wherein FEAT_HCX is detected at boot time. In case not 504 implemented by the PE, a hard panic is generated. Finally, if the flag is set 505 to 2, feature is validated at runtime. 506 507 Note that the entire implementation is divided into two phases, wherein as 508 as part of phase-1 we are supporting the values 0,1. Value 2 is currently not 509 supported and is planned to be handled explicilty in phase-2 implementation. 510 511 FEATURE_DETECTION macro is disabled by default, and is currently an 512 experimental procedure. Platforms can explicitly make use of this by 513 mechanism, by enabling it to validate whether they have set their build flags 514 properly at an early phase. 515 516- ``FIP_NAME``: This is an optional build option which specifies the FIP 517 filename for the ``fip`` target. Default is ``fip.bin``. 518 519- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 520 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 521 522- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 523 524 :: 525 526 0: Encryption is done with Secret Symmetric Key (SSK) which is common 527 for a class of devices. 528 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 529 unique per device. 530 531 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 532 533- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 534 tool to create certificates as per the Chain of Trust described in 535 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 536 include the certificates in the FIP and FWU_FIP. Default value is '0'. 537 538 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 539 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 540 the corresponding certificates, and to include those certificates in the 541 FIP and FWU_FIP. 542 543 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 544 images will not include support for Trusted Board Boot. The FIP will still 545 include the corresponding certificates. This FIP can be used to verify the 546 Chain of Trust on the host machine through other mechanisms. 547 548 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 549 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 550 will not include the corresponding certificates, causing a boot failure. 551 552- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 553 inherent support for specific EL3 type interrupts. Setting this build option 554 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 555 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 556 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 557 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 558 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 559 the Secure Payload interrupts needs to be synchronously handed over to Secure 560 EL1 for handling. The default value of this option is ``0``, which means the 561 Group 0 interrupts are assumed to be handled by Secure EL1. 562 563- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError 564 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to 565 ``0`` (default), these exceptions will be trapped in the current exception 566 level (or in EL1 if the current exception level is EL0). 567 568- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 569 software operations are required for CPUs to enter and exit coherency. 570 However, newer systems exist where CPUs' entry to and exit from coherency 571 is managed in hardware. Such systems require software to only initiate these 572 operations, and the rest is managed in hardware, minimizing active software 573 management. In such systems, this boolean option enables TF-A to carry out 574 build and run-time optimizations during boot and power management operations. 575 This option defaults to 0 and if it is enabled, then it implies 576 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 577 578 If this flag is disabled while the platform which TF-A is compiled for 579 includes cores that manage coherency in hardware, then a compilation error is 580 generated. This is based on the fact that a system cannot have, at the same 581 time, cores that manage coherency in hardware and cores that don't. In other 582 words, a platform cannot have, at the same time, cores that require 583 ``HW_ASSISTED_COHERENCY=1`` and cores that require 584 ``HW_ASSISTED_COHERENCY=0``. 585 586 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 587 translation library (xlat tables v2) must be used; version 1 of translation 588 library is not supported. 589 590- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 591 bottom, higher addresses at the top. This build flag can be set to '1' to 592 invert this behavior. Lower addresses will be printed at the top and higher 593 addresses at the bottom. 594 595- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 596 runtime software in AArch32 mode, which is required to run AArch32 on Juno. 597 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in 598 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable 599 images. 600 601- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 602 used for generating the PKCS keys and subsequent signing of the certificate. 603 It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option 604 ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR 605 compliant and is retained only for compatibility. The default value of this 606 flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme. 607 608- ``KEY_SIZE``: This build flag enables the user to select the key size for 609 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 610 depend on the chosen algorithm and the cryptographic module. 611 612 +-----------+------------------------------------+ 613 | KEY_ALG | Possible key sizes | 614 +===========+====================================+ 615 | rsa | 1024 , 2048 (default), 3072, 4096* | 616 +-----------+------------------------------------+ 617 | ecdsa | unavailable | 618 +-----------+------------------------------------+ 619 620 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. 621 Only 3072 bits size is available with CryptoCell 712 SBROM release 2. 622 623- ``HASH_ALG``: This build flag enables the user to select the secure hash 624 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 625 The default value of this flag is ``sha256``. 626 627- ``LDFLAGS``: Extra user options appended to the linkers' command line in 628 addition to the one set by the build system. 629 630- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 631 output compiled into the build. This should be one of the following: 632 633 :: 634 635 0 (LOG_LEVEL_NONE) 636 10 (LOG_LEVEL_ERROR) 637 20 (LOG_LEVEL_NOTICE) 638 30 (LOG_LEVEL_WARNING) 639 40 (LOG_LEVEL_INFO) 640 50 (LOG_LEVEL_VERBOSE) 641 642 All log output up to and including the selected log level is compiled into 643 the build. The default value is 40 in debug builds and 20 in release builds. 644 645- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 646 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 647 provide trust that the code taking the measurements and recording them has 648 not been tampered with. 649 650 This option defaults to 0. 651 652- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 653 specifies the file that contains the Non-Trusted World private key in PEM 654 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 655 656- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 657 optional. It is only needed if the platform makefile specifies that it 658 is required in order to build the ``fwu_fip`` target. 659 660- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 661 contents upon world switch. It can take either 0 (don't save and restore) or 662 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 663 wants the timer registers to be saved and restored. 664 665- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 666 for the BL image. It can be either 0 (include) or 1 (remove). The default 667 value is 0. 668 669- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 670 the underlying hardware is not a full PL011 UART but a minimally compliant 671 generic UART, which is a subset of the PL011. The driver will not access 672 any register that is not part of the SBSA generic UART specification. 673 Default value is 0 (a full PL011 compliant UART is present). 674 675- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 676 must be subdirectory of any depth under ``plat/``, and must contain a 677 platform makefile named ``platform.mk``. For example, to build TF-A for the 678 Arm Juno board, select PLAT=juno. 679 680- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 681 instead of the normal boot flow. When defined, it must specify the entry 682 point address for the preloaded BL33 image. This option is incompatible with 683 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 684 over ``PRELOADED_BL33_BASE``. 685 686- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 687 vector address can be programmed or is fixed on the platform. It can take 688 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 689 programmable reset address, it is expected that a CPU will start executing 690 code directly at the right address, both on a cold and warm reset. In this 691 case, there is no need to identify the entrypoint on boot and the boot path 692 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 693 does not need to be implemented in this case. 694 695- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 696 possible for the PSCI power-state parameter: original and extended State-ID 697 formats. This flag if set to 1, configures the generic PSCI layer to use the 698 extended format. The default value of this flag is 0, which means by default 699 the original power-state format is used by the PSCI implementation. This flag 700 should be specified by the platform makefile and it governs the return value 701 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 702 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 703 set to 1 as well. 704 705- ``RAS_EXTENSION``: Numeric value to enable Armv8.2 RAS features. RAS features 706 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 707 or later CPUs. This flag can take the values 0 to 2, to align with the 708 ``FEATURE_DETECTION`` mechanism. 709 710 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be 711 set to ``1``. 712 713 This option is disabled by default. 714 715- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 716 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 717 entrypoint) or 1 (CPU reset to BL31 entrypoint). 718 The default value is 0. 719 720- ``RESET_TO_BL31_WITH_PARAMS``: If ``RESET_TO_BL31`` has been enabled, setting 721 this additional option guarantees that the input registers are not cleared 722 therefore allowing parameters to be passed to the BL31 entrypoint. 723 The default value is 0. 724 725- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 726 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 727 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 728 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 729 730- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 731 file that contains the ROT private key in PEM format and enforces public key 732 hash generation. If ``SAVE_KEYS=1``, this 733 file name will be used to save the key. 734 735- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 736 certificate generation tool to save the keys used to establish the Chain of 737 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 738 739- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 740 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 741 target. 742 743- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 744 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, 745 this file name will be used to save the key. 746 747- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 748 optional. It is only needed if the platform makefile specifies that it 749 is required in order to build the ``fwu_fip`` target. 750 751- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 752 Delegated Exception Interface to BL31 image. This defaults to ``0``. 753 754 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 755 set to ``1``. 756 757- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 758 isolated on separate memory pages. This is a trade-off between security and 759 memory usage. See "Isolating code and read-only data on separate memory 760 pages" section in :ref:`Firmware Design`. This flag is disabled by default 761 and affects all BL images. 762 763- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 764 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 765 allocated in RAM discontiguous from the loaded firmware image. When set, the 766 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 767 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 768 sections are placed in RAM immediately following the loaded firmware image. 769 770- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 771 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 772 discontiguous from loaded firmware images. When set, the platform need to 773 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 774 flag is disabled by default and NOLOAD sections are placed in RAM immediately 775 following the loaded firmware image. 776 777- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 778 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 779 UEFI+ACPI this can provide a certain amount of OS forward compatibility 780 with newer platforms that aren't ECAM compliant. 781 782- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 783 This build option is only valid if ``ARCH=aarch64``. The value should be 784 the path to the directory containing the SPD source, relative to 785 ``services/spd/``; the directory is expected to contain a makefile called 786 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 787 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 788 cannot be enabled when the ``SPM_MM`` option is enabled. 789 790- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 791 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 792 execution in BL1 just before handing over to BL31. At this point, all 793 firmware images have been loaded in memory, and the MMU and caches are 794 turned off. Refer to the "Debugging options" section for more details. 795 796- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 797 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 798 component runs at the EL3 exception level. The default value is ``0`` ( 799 disabled). This configuration supports pre-Armv8.4 platforms (aka not 800 implementing the ``FEAT_SEL2`` extension). This is an experimental feature. 801 802- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 803 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 804 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 805 extension. This is the default when enabling the SPM Dispatcher. When 806 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 807 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 808 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 809 extension). 810 811- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 812 Partition Manager (SPM) implementation. The default value is ``0`` 813 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 814 enabled (``SPD=spmd``). 815 816- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 817 description of secure partitions. The build system will parse this file and 818 package all secure partition blobs into the FIP. This file is not 819 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 820 821- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 822 secure interrupts (caught through the FIQ line). Platforms can enable 823 this directive if they need to handle such interruption. When enabled, 824 the FIQ are handled in monitor mode and non secure world is not allowed 825 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 826 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 827 828- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 829 Boot feature. When set to '1', BL1 and BL2 images include support to load 830 and verify the certificates and images in a FIP, and BL1 includes support 831 for the Firmware Update. The default value is '0'. Generation and inclusion 832 of certificates in the FIP and FWU_FIP depends upon the value of the 833 ``GENERATE_COT`` option. 834 835 .. warning:: 836 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 837 already exist in disk, they will be overwritten without further notice. 838 839- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 840 specifies the file that contains the Trusted World private key in PEM 841 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 842 843- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 844 synchronous, (see "Initializing a BL32 Image" section in 845 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 846 synchronous method) or 1 (BL32 is initialized using asynchronous method). 847 Default is 0. 848 849- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 850 routing model which routes non-secure interrupts asynchronously from TSP 851 to EL3 causing immediate preemption of TSP. The EL3 is responsible 852 for saving and restoring the TSP context in this routing model. The 853 default routing model (when the value is 0) is to route non-secure 854 interrupts to TSP allowing it to save its context and hand over 855 synchronously to EL3 via an SMC. 856 857 .. note:: 858 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 859 must also be set to ``1``. 860 861- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 862 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 863 this delay. It can take values in the range (0-15). Default value is ``0`` 864 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 865 Platforms need to explicitly update this value based on their requirements. 866 867- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 868 linker. When the ``LINKER`` build variable points to the armlink linker, 869 this flag is enabled automatically. To enable support for armlink, platforms 870 will have to provide a scatter file for the BL image. Currently, Tegra 871 platforms use the armlink support to compile BL3-1 images. 872 873- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 874 memory region in the BL memory map or not (see "Use of Coherent memory in 875 TF-A" section in :ref:`Firmware Design`). It can take the value 1 876 (Coherent memory region is included) or 0 (Coherent memory region is 877 excluded). Default is 1. 878 879- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature 880 exposing a virtual filesystem interface through BL31 as a SiP SMC function. 881 Default is 0. 882 883- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 884 firmware configuration framework. This will move the io_policies into a 885 configuration device tree, instead of static structure in the code base. 886 887- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 888 at runtime using fconf. If this flag is enabled, COT descriptors are 889 statically captured in tb_fw_config file in the form of device tree nodes 890 and properties. Currently, COT descriptors used by BL2 are moved to the 891 device tree and COT descriptors used by BL1 are retained in the code 892 base statically. 893 894- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 895 runtime using firmware configuration framework. The platform specific SDEI 896 shared and private events configuration is retrieved from device tree rather 897 than static C structures at compile time. This is only supported if 898 SDEI_SUPPORT build flag is enabled. 899 900- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 901 and Group1 secure interrupts using the firmware configuration framework. The 902 platform specific secure interrupt property descriptor is retrieved from 903 device tree in runtime rather than depending on static C structure at compile 904 time. 905 906- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 907 This feature creates a library of functions to be placed in ROM and thus 908 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 909 is 0. 910 911- ``V``: Verbose build. If assigned anything other than 0, the build commands 912 are printed. Default is 0. 913 914- ``VERSION_STRING``: String used in the log output for each TF-A image. 915 Defaults to a string formed by concatenating the version number, build type 916 and build string. 917 918- ``W``: Warning level. Some compiler warning options of interest have been 919 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 920 each level enabling more warning options. Default is 0. 921 922- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 923 the CPU after warm boot. This is applicable for platforms which do not 924 require interconnect programming to enable cache coherency (eg: single 925 cluster platforms). If this option is enabled, then warm boot path 926 enables D-caches immediately after enabling MMU. This option defaults to 0. 927 928- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 929 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 930 default value of this flag is ``no``. Note this option must be enabled only 931 for ARM architecture greater than Armv8.5-A. 932 933- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 934 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 935 The default value of this flag is ``0``. 936 937 ``AT`` speculative errata workaround disables stage1 page table walk for 938 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 939 produces either the correct result or failure without TLB allocation. 940 941 This boolean option enables errata for all below CPUs. 942 943 +---------+--------------+-------------------------+ 944 | Errata | CPU | Workaround Define | 945 +=========+==============+=========================+ 946 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 947 +---------+--------------+-------------------------+ 948 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 949 +---------+--------------+-------------------------+ 950 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 951 +---------+--------------+-------------------------+ 952 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 953 +---------+--------------+-------------------------+ 954 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 955 +---------+--------------+-------------------------+ 956 957 .. note:: 958 This option is enabled by build only if platform sets any of above defines 959 mentioned in ’Workaround Define' column in the table. 960 If this option is enabled for the EL3 software then EL2 software also must 961 implement this workaround due to the behaviour of the errata mentioned 962 in new SDEN document which will get published soon. 963 964- ``RAS_TRAP_LOWER_EL_ERR_ACCESS``: This flag enables/disables the SCR_EL3.TERR 965 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 966 This flag is disabled by default. 967 968- ``OPENSSL_DIR``: This flag is used to provide the installed openssl directory 969 path on the host machine which is used to build certificate generation and 970 firmware encryption tool. 971 972- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 973 functions that wait for an arbitrary time length (udelay and mdelay). The 974 default value is 0. 975 976- ``ENABLE_BRBE_FOR_NS``: This flag enables access to the branch record buffer 977 registers from NS ELs when FEAT_BRBE is implemented. BRBE is an optional 978 architectural feature for AArch64. The default is 0 and it is automatically 979 disabled when the target architecture is AArch32. 980 981- ``ENABLE_TRBE_FOR_NS``: This flag is used to enable access of trace buffer 982 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 983 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 984 feature for AArch64. The default is 0 and it is automatically disabled when 985 the target architecture is AArch32. 986 987- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Boolean option to enable trace system 988 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 989 but unused). This feature is available if trace unit such as ETMv4.x, and 990 ETE(extending ETM feature) is implemented. This flag is disabled by default. 991 992- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 993 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 994 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 995 with the ``FEATURE_DETECTION`` mechanism. This flag is disabled by default. 996 997GICv3 driver options 998-------------------- 999 1000GICv3 driver files are included using directive: 1001 1002``include drivers/arm/gic/v3/gicv3.mk`` 1003 1004The driver can be configured with the following options set in the platform 1005makefile: 1006 1007- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1008 Enabling this option will add runtime detection support for the 1009 GIC-600, so is safe to select even for a GIC500 implementation. 1010 This option defaults to 0. 1011 1012- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1013 for GIC-600 AE. Enabling this option will introduce support to initialize 1014 the FMU. Platforms should call the init function during boot to enable the 1015 FMU and its safety mechanisms. This option defaults to 0. 1016 1017- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1018 functionality. This option defaults to 0 1019 1020- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1021 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1022 functions. This is required for FVP platform which need to simulate GIC save 1023 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1024 1025- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1026 This option defaults to 0. 1027 1028- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1029 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1030 1031Debugging options 1032----------------- 1033 1034To compile a debug version and make the build more verbose use 1035 1036.. code:: shell 1037 1038 make PLAT=<platform> DEBUG=1 V=1 all 1039 1040AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for 1041example DS-5) might not support this and may need an older version of DWARF 1042symbols to be emitted by GCC. This can be achieved by using the 1043``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the 1044version to 2 is recommended for DS-5 versions older than 5.16. 1045 1046When debugging logic problems it might also be useful to disable all compiler 1047optimizations by using ``-O0``. 1048 1049.. warning:: 1050 Using ``-O0`` could cause output images to be larger and base addresses 1051 might need to be recalculated (see the **Memory layout on Arm development 1052 platforms** section in the :ref:`Firmware Design`). 1053 1054Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1055``LDFLAGS``: 1056 1057.. code:: shell 1058 1059 CFLAGS='-O0 -gdwarf-2' \ 1060 make PLAT=<platform> DEBUG=1 V=1 all 1061 1062Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1063ignored as the linker is called directly. 1064 1065It is also possible to introduce an infinite loop to help in debugging the 1066post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1067``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1068section. In this case, the developer may take control of the target using a 1069debugger when indicated by the console output. When using DS-5, the following 1070commands can be used: 1071 1072:: 1073 1074 # Stop target execution 1075 interrupt 1076 1077 # 1078 # Prepare your debugging environment, e.g. set breakpoints 1079 # 1080 1081 # Jump over the debug loop 1082 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1083 1084 # Resume execution 1085 continue 1086 1087Firmware update options 1088----------------------- 1089 1090- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1091 in defining the firmware update metadata structure. This flag is by default 1092 set to '2'. 1093 1094- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1095 firmware bank. Each firmware bank must have the same number of images as per 1096 the `PSA FW update specification`_. 1097 This flag is used in defining the firmware update metadata structure. This 1098 flag is by default set to '1'. 1099 1100- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1101 `PSA FW update specification`_. The default value is 0, and this is an 1102 experimental feature. 1103 PSA firmware update implementation has some limitations, such as BL2 is 1104 not part of the protocol-updatable images, if BL2 needs to be updated, then 1105 it should be done through another platform-defined mechanism, and it assumes 1106 that the platform's hardware supports CRC32 instructions. 1107 1108-------------- 1109 1110*Copyright (c) 2019-2022, Arm Limited. All rights reserved.* 1111 1112.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1113.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/ 1114