1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 26 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 27 ``aarch64``. 28 29- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 30 one or more feature modifiers. This option has the form ``[no]feature+...`` 31 and defaults to ``none``. It translates into compiler option 32 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 33 list of supported feature modifiers. 34 35- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 36 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 37 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 38 :ref:`Firmware Design`. 39 40- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 41 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 42 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 43 44- ``BL2``: This is an optional build option which specifies the path to BL2 45 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 46 built. 47 48- ``BL2U``: This is an optional build option which specifies the path to 49 BL2U image. In this case, the BL2U in TF-A will not be built. 50 51- ``BL2_AT_EL3``: This is an optional build option that enables the use of 52 BL2 at EL3 execution level. 53 54- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 55 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 56 the RW sections in RAM, while leaving the RO sections in place. This option 57 enable this use-case. For now, this option is only supported when BL2_AT_EL3 58 is set to '1'. 59 60- ``BL31``: This is an optional build option which specifies the path to 61 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 62 be built. 63 64- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 65 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, 66 this file name will be used to save the key. 67 68- ``BL32``: This is an optional build option which specifies the path to 69 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 70 be built. 71 72- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 73 Trusted OS Extra1 image for the ``fip`` target. 74 75- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 76 Trusted OS Extra2 image for the ``fip`` target. 77 78- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 79 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, 80 this file name will be used to save the key. 81 82- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 83 ``fip`` target in case TF-A BL2 is used. 84 85- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 86 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, 87 this file name will be used to save the key. 88 89- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 90 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 91 If enabled, it is needed to use a compiler that supports the option 92 ``-mbranch-protection``. Selects the branch protection features to use: 93- 0: Default value turns off all types of branch protection 94- 1: Enables all types of branch protection features 95- 2: Return address signing to its standard level 96- 3: Extend the signing to include leaf functions 97- 4: Turn on branch target identification mechanism 98 99 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 100 and resulting PAuth/BTI features. 101 102 +-------+--------------+-------+-----+ 103 | Value | GCC option | PAuth | BTI | 104 +=======+==============+=======+=====+ 105 | 0 | none | N | N | 106 +-------+--------------+-------+-----+ 107 | 1 | standard | Y | Y | 108 +-------+--------------+-------+-----+ 109 | 2 | pac-ret | Y | N | 110 +-------+--------------+-------+-----+ 111 | 3 | pac-ret+leaf | Y | N | 112 +-------+--------------+-------+-----+ 113 | 4 | bti | N | Y | 114 +-------+--------------+-------+-----+ 115 116 This option defaults to 0 and this is an experimental feature. 117 Note that Pointer Authentication is enabled for Non-secure world 118 irrespective of the value of this option if the CPU supports it. 119 120- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 121 compilation of each build. It must be set to a C string (including quotes 122 where applicable). Defaults to a string that contains the time and date of 123 the compilation. 124 125- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 126 build to be uniquely identified. Defaults to the current git commit id. 127 128- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 129 130- ``CFLAGS``: Extra user options appended on the compiler's command line in 131 addition to the options set by the build system. 132 133- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 134 release several CPUs out of reset. It can take either 0 (several CPUs may be 135 brought up) or 1 (only one CPU will ever be brought up during cold reset). 136 Default is 0. If the platform always brings up a single CPU, there is no 137 need to distinguish between primary and secondary CPUs and the boot path can 138 be optimised. The ``plat_is_my_cpu_primary()`` and 139 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 140 to be implemented in this case. 141 142- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 143 Defaults to ``tbbr``. 144 145- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 146 register state when an unexpected exception occurs during execution of 147 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 148 this is only enabled for a debug build of the firmware. 149 150- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 151 certificate generation tool to create new keys in case no valid keys are 152 present or specified. Allowed options are '0' or '1'. Default is '1'. 153 154- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 155 the AArch32 system registers to be included when saving and restoring the 156 CPU context. The option must be set to 0 for AArch64-only platforms (that 157 is on hardware that does not implement AArch32, or at least not at EL1 and 158 higher ELs). Default value is 1. 159 160- ``CTX_INCLUDE_EL2_REGS`` : This boolean option provides context save/restore 161 operations when entering/exiting an EL2 execution context. This is of primary 162 interest when Armv8.4-SecEL2 extension is implemented. Default is 0 (disabled). 163 This option must be equal to 1 (enabled) when ``SPD=spmd`` and 164 ``SPMD_SPM_AT_SEL2`` is set. 165 166- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 167 registers to be included when saving and restoring the CPU context. Default 168 is 0. 169 170- ``CTX_INCLUDE_NEVE_REGS``: Boolean option that, when set to 1, will cause the 171 Armv8.4-NV registers to be saved/restored when entering/exiting an EL2 172 execution context. Default value is 0. 173 174- ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables 175 Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth 176 registers to be included when saving and restoring the CPU context as 177 part of world switch. Default value is 0 and this is an experimental feature. 178 Note that Pointer Authentication is enabled for Non-secure world irrespective 179 of the value of this flag if the CPU supports it. 180 181- ``DEBUG``: Chooses between a debug and release build. It can take either 0 182 (release) or 1 (debug) as values. 0 is the default. 183 184- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 185 authenticated decryption algorithm to be used to decrypt firmware/s during 186 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 187 this flag is ``none`` to disable firmware decryption which is an optional 188 feature as per TBBR. Also, it is an experimental feature. 189 190- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 191 of the binary image. If set to 1, then only the ELF image is built. 192 0 is the default. 193 194- ``DISABLE_MTPMU``: Boolean option to disable FEAT_MTPMU if implemented 195 (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms 196 that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU, 197 check the latest Arm ARM. 198 199- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 200 Board Boot authentication at runtime. This option is meant to be enabled only 201 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 202 flag has to be enabled. 0 is the default. 203 204- ``E``: Boolean option to make warnings into errors. Default is 1. 205 206- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 207 the normal boot flow. It must specify the entry point address of the EL3 208 payload. Please refer to the "Booting an EL3 payload" section for more 209 details. 210 211- ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions. 212 This is an optional architectural feature available on v8.4 onwards. Some 213 v8.2 implementations also implement an AMU and this option can be used to 214 enable this feature on those systems as well. Default is 0. 215 216- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 217 are compiled out. For debug builds, this option defaults to 1, and calls to 218 ``assert()`` are left in place. For release builds, this option defaults to 0 219 and calls to ``assert()`` function are compiled out. This option can be set 220 independently of ``DEBUG``. It can also be used to hide any auxiliary code 221 that is only required for the assertion and does not fit in the assertion 222 itself. 223 224- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 225 dumps or not. It is supported in both AArch64 and AArch32. However, in 226 AArch32 the format of the frame records are not defined in the AAPCS and they 227 are defined by the implementation. This implementation of backtrace only 228 supports the format used by GCC when T32 interworking is disabled. For this 229 reason enabling this option in AArch32 will force the compiler to only 230 generate A32 code. This option is enabled by default only in AArch64 debug 231 builds, but this behaviour can be overridden in each platform's Makefile or 232 in the build command line. 233 234- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 235 support in GCC for TF-A. This option is currently only supported for 236 AArch64. Default is 0. 237 238- ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM 239 feature. MPAM is an optional Armv8.4 extension that enables various memory 240 system components and resources to define partitions; software running at 241 various ELs can assign themselves to desired partition to control their 242 performance aspects. 243 244 When this option is set to ``1``, EL3 allows lower ELs to access their own 245 MPAM registers without trapping into EL3. This option doesn't make use of 246 partitioning in EL3, however. Platform initialisation code should configure 247 and use partitions in EL3 as required. This option defaults to ``0``. 248 249- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 250 support within generic code in TF-A. This option is currently only supported 251 in BL2_AT_EL3, BL31, and BL32 (TSP). Default is 0. 252 253- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 254 Measurement Framework(PMF). Default is 0. 255 256- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 257 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 258 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 259 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 260 software. 261 262- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 263 instrumentation which injects timestamp collection points into TF-A to 264 allow runtime performance to be measured. Currently, only PSCI is 265 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 266 as well. Default is 0. 267 268- ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling 269 extensions. This is an optional architectural feature for AArch64. 270 The default is 1 but is automatically disabled when the target architecture 271 is AArch32. 272 273- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension 274 (SVE) for the Non-secure world only. SVE is an optional architectural feature 275 for AArch64. Note that when SVE is enabled for the Non-secure world, access 276 to SIMD and floating-point functionality from the Secure world is disabled. 277 This is to avoid corruption of the Non-secure world data in the Z-registers 278 which are aliased by the SIMD and FP registers. The build option is not 279 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an 280 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to 281 1. The default is 1 but is automatically disabled when the target 282 architecture is AArch32. 283 284- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 285 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 286 default value is set to "none". "strong" is the recommended stack protection 287 level if this feature is desired. "none" disables the stack protection. For 288 all values other than "none", the ``plat_get_stack_protector_canary()`` 289 platform hook needs to be implemented. The value is passed as the last 290 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 291 292- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 293 flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as 294 experimental. 295 296- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 297 This flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as 298 experimental. 299 300- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 301 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 302 on ``DECRYPTION_SUPPORT`` build flag which is marked as experimental. 303 304- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 305 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 306 build flag which is marked as experimental. 307 308- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 309 deprecated platform APIs, helper functions or drivers within Trusted 310 Firmware as error. It can take the value 1 (flag the use of deprecated 311 APIs as error) or 0. The default is 0. 312 313- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 314 targeted at EL3. When set ``0`` (default), no exceptions are expected or 315 handled at EL3, and a panic will result. This is supported only for AArch64 316 builds. 317 318- ``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when 319 ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. 320 Default value is 40 (LOG_LEVEL_INFO). 321 322- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 323 injection from lower ELs, and this build option enables lower ELs to use 324 Error Records accessed via System Registers to inject faults. This is 325 applicable only to AArch64 builds. 326 327 This feature is intended for testing purposes only, and is advisable to keep 328 disabled for production images. 329 330- ``FIP_NAME``: This is an optional build option which specifies the FIP 331 filename for the ``fip`` target. Default is ``fip.bin``. 332 333- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 334 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 335 336- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 337 338 :: 339 340 0: Encryption is done with Secret Symmetric Key (SSK) which is common 341 for a class of devices. 342 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 343 unique per device. 344 345 This flag depends on ``DECRYPTION_SUPPORT`` build flag which is marked as 346 experimental. 347 348- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 349 tool to create certificates as per the Chain of Trust described in 350 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 351 include the certificates in the FIP and FWU_FIP. Default value is '0'. 352 353 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 354 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 355 the corresponding certificates, and to include those certificates in the 356 FIP and FWU_FIP. 357 358 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 359 images will not include support for Trusted Board Boot. The FIP will still 360 include the corresponding certificates. This FIP can be used to verify the 361 Chain of Trust on the host machine through other mechanisms. 362 363 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 364 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 365 will not include the corresponding certificates, causing a boot failure. 366 367- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 368 inherent support for specific EL3 type interrupts. Setting this build option 369 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 370 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 371 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 372 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 373 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 374 the Secure Payload interrupts needs to be synchronously handed over to Secure 375 EL1 for handling. The default value of this option is ``0``, which means the 376 Group 0 interrupts are assumed to be handled by Secure EL1. 377 378- ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError 379 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to 380 ``0`` (default), these exceptions will be trapped in the current exception 381 level (or in EL1 if the current exception level is EL0). 382 383- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 384 software operations are required for CPUs to enter and exit coherency. 385 However, newer systems exist where CPUs' entry to and exit from coherency 386 is managed in hardware. Such systems require software to only initiate these 387 operations, and the rest is managed in hardware, minimizing active software 388 management. In such systems, this boolean option enables TF-A to carry out 389 build and run-time optimizations during boot and power management operations. 390 This option defaults to 0 and if it is enabled, then it implies 391 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 392 393 If this flag is disabled while the platform which TF-A is compiled for 394 includes cores that manage coherency in hardware, then a compilation error is 395 generated. This is based on the fact that a system cannot have, at the same 396 time, cores that manage coherency in hardware and cores that don't. In other 397 words, a platform cannot have, at the same time, cores that require 398 ``HW_ASSISTED_COHERENCY=1`` and cores that require 399 ``HW_ASSISTED_COHERENCY=0``. 400 401 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 402 translation library (xlat tables v2) must be used; version 1 of translation 403 library is not supported. 404 405- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 406 bottom, higher addresses at the top. This build flag can be set to '1' to 407 invert this behavior. Lower addresses will be printed at the top and higher 408 addresses at the bottom. 409 410- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 411 runtime software in AArch32 mode, which is required to run AArch32 on Juno. 412 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in 413 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable 414 images. 415 416- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 417 used for generating the PKCS keys and subsequent signing of the certificate. 418 It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option 419 ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR 420 compliant and is retained only for compatibility. The default value of this 421 flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme. 422 423- ``KEY_SIZE``: This build flag enables the user to select the key size for 424 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 425 depend on the chosen algorithm and the cryptographic module. 426 427 +-----------+------------------------------------+ 428 | KEY_ALG | Possible key sizes | 429 +===========+====================================+ 430 | rsa | 1024 , 2048 (default), 3072, 4096* | 431 +-----------+------------------------------------+ 432 | ecdsa | unavailable | 433 +-----------+------------------------------------+ 434 435 * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. 436 Only 3072 bits size is available with CryptoCell 712 SBROM release 2. 437 438- ``HASH_ALG``: This build flag enables the user to select the secure hash 439 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 440 The default value of this flag is ``sha256``. 441 442- ``LDFLAGS``: Extra user options appended to the linkers' command line in 443 addition to the one set by the build system. 444 445- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 446 output compiled into the build. This should be one of the following: 447 448 :: 449 450 0 (LOG_LEVEL_NONE) 451 10 (LOG_LEVEL_ERROR) 452 20 (LOG_LEVEL_NOTICE) 453 30 (LOG_LEVEL_WARNING) 454 40 (LOG_LEVEL_INFO) 455 50 (LOG_LEVEL_VERBOSE) 456 457 All log output up to and including the selected log level is compiled into 458 the build. The default value is 40 in debug builds and 20 in release builds. 459 460- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 461 feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set. 462 This option defaults to 0 and is an experimental feature in the stage of 463 development. 464 465- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 466 specifies the file that contains the Non-Trusted World private key in PEM 467 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 468 469- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 470 optional. It is only needed if the platform makefile specifies that it 471 is required in order to build the ``fwu_fip`` target. 472 473- ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register 474 contents upon world switch. It can take either 0 (don't save and restore) or 475 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it 476 wants the timer registers to be saved and restored. 477 478- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 479 for the BL image. It can be either 0 (include) or 1 (remove). The default 480 value is 0. 481 482- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 483 the underlying hardware is not a full PL011 UART but a minimally compliant 484 generic UART, which is a subset of the PL011. The driver will not access 485 any register that is not part of the SBSA generic UART specification. 486 Default value is 0 (a full PL011 compliant UART is present). 487 488- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 489 must be subdirectory of any depth under ``plat/``, and must contain a 490 platform makefile named ``platform.mk``. For example, to build TF-A for the 491 Arm Juno board, select PLAT=juno. 492 493- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 494 instead of the normal boot flow. When defined, it must specify the entry 495 point address for the preloaded BL33 image. This option is incompatible with 496 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 497 over ``PRELOADED_BL33_BASE``. 498 499- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 500 vector address can be programmed or is fixed on the platform. It can take 501 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 502 programmable reset address, it is expected that a CPU will start executing 503 code directly at the right address, both on a cold and warm reset. In this 504 case, there is no need to identify the entrypoint on boot and the boot path 505 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 506 does not need to be implemented in this case. 507 508- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 509 possible for the PSCI power-state parameter: original and extended State-ID 510 formats. This flag if set to 1, configures the generic PSCI layer to use the 511 extended format. The default value of this flag is 0, which means by default 512 the original power-state format is used by the PSCI implementation. This flag 513 should be specified by the platform makefile and it governs the return value 514 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 515 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 516 set to 1 as well. 517 518- ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features 519 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 520 or later CPUs. 521 522 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be 523 set to ``1``. 524 525 This option is disabled by default. 526 527- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 528 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 529 entrypoint) or 1 (CPU reset to BL31 entrypoint). 530 The default value is 0. 531 532- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 533 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 534 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 535 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 536 537- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 538 file that contains the ROT private key in PEM format and enforces public key 539 hash generation. If ``SAVE_KEYS=1``, this 540 file name will be used to save the key. 541 542- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 543 certificate generation tool to save the keys used to establish the Chain of 544 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 545 546- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 547 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 548 target. 549 550- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the 551 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, 552 this file name will be used to save the key. 553 554- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 555 optional. It is only needed if the platform makefile specifies that it 556 is required in order to build the ``fwu_fip`` target. 557 558- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 559 Delegated Exception Interface to BL31 image. This defaults to ``0``. 560 561 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 562 set to ``1``. 563 564- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 565 isolated on separate memory pages. This is a trade-off between security and 566 memory usage. See "Isolating code and read-only data on separate memory 567 pages" section in :ref:`Firmware Design`. This flag is disabled by default 568 and affects all BL images. 569 570- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 571 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 572 allocated in RAM discontiguous from the loaded firmware image. When set, the 573 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 574 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 575 sections are placed in RAM immediately following the loaded firmware image. 576 577- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 578 This build option is only valid if ``ARCH=aarch64``. The value should be 579 the path to the directory containing the SPD source, relative to 580 ``services/spd/``; the directory is expected to contain a makefile called 581 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 582 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 583 cannot be enabled when the ``SPM_MM`` option is enabled. 584 585- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 586 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 587 execution in BL1 just before handing over to BL31. At this point, all 588 firmware images have been loaded in memory, and the MMU and caches are 589 turned off. Refer to the "Debugging options" section for more details. 590 591- ``SPMD_SPM_AT_SEL2`` : this boolean option is used jointly with the SPM 592 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 593 component runs at the S-EL2 execution state provided by the Armv8.4-SecEL2 594 extension. This is the default when enabling the SPM Dispatcher. When 595 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 596 state. This latter configuration supports pre-Armv8.4 platforms (aka not 597 implementing the Armv8.4-SecEL2 extension). 598 599- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 600 Partition Manager (SPM) implementation. The default value is ``0`` 601 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 602 enabled (``SPD=spmd``). 603 604- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 605 description of secure partitions. The build system will parse this file and 606 package all secure partition blobs into the FIP. This file is not 607 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 608 609- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 610 secure interrupts (caught through the FIQ line). Platforms can enable 611 this directive if they need to handle such interruption. When enabled, 612 the FIQ are handled in monitor mode and non secure world is not allowed 613 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 614 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 615 616- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 617 Boot feature. When set to '1', BL1 and BL2 images include support to load 618 and verify the certificates and images in a FIP, and BL1 includes support 619 for the Firmware Update. The default value is '0'. Generation and inclusion 620 of certificates in the FIP and FWU_FIP depends upon the value of the 621 ``GENERATE_COT`` option. 622 623 .. warning:: 624 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 625 already exist in disk, they will be overwritten without further notice. 626 627- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 628 specifies the file that contains the Trusted World private key in PEM 629 format. If ``SAVE_KEYS=1``, this file name will be used to save the key. 630 631- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 632 synchronous, (see "Initializing a BL32 Image" section in 633 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 634 synchronous method) or 1 (BL32 is initialized using asynchronous method). 635 Default is 0. 636 637- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 638 routing model which routes non-secure interrupts asynchronously from TSP 639 to EL3 causing immediate preemption of TSP. The EL3 is responsible 640 for saving and restoring the TSP context in this routing model. The 641 default routing model (when the value is 0) is to route non-secure 642 interrupts to TSP allowing it to save its context and hand over 643 synchronously to EL3 via an SMC. 644 645 .. note:: 646 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 647 must also be set to ``1``. 648 649- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 650 linker. When the ``LINKER`` build variable points to the armlink linker, 651 this flag is enabled automatically. To enable support for armlink, platforms 652 will have to provide a scatter file for the BL image. Currently, Tegra 653 platforms use the armlink support to compile BL3-1 images. 654 655- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 656 memory region in the BL memory map or not (see "Use of Coherent memory in 657 TF-A" section in :ref:`Firmware Design`). It can take the value 1 658 (Coherent memory region is included) or 0 (Coherent memory region is 659 excluded). Default is 1. 660 661- ``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature 662 exposing a virtual filesystem interface through BL31 as a SiP SMC function. 663 Default is 0. 664 665- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 666 firmware configuration framework. This will move the io_policies into a 667 configuration device tree, instead of static structure in the code base. 668 This is currently an experimental feature. 669 670- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 671 at runtime using fconf. If this flag is enabled, COT descriptors are 672 statically captured in tb_fw_config file in the form of device tree nodes 673 and properties. Currently, COT descriptors used by BL2 are moved to the 674 device tree and COT descriptors used by BL1 are retained in the code 675 base statically. This is currently an experimental feature. 676 677- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 678 runtime using firmware configuration framework. The platform specific SDEI 679 shared and private events configuration is retrieved from device tree rather 680 than static C structures at compile time. This is currently an experimental 681 feature and is only supported if SDEI_SUPPORT build flag is enabled. 682 683- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 684 and Group1 secure interrupts using the firmware configuration framework. The 685 platform specific secure interrupt property descriptor is retrieved from 686 device tree in runtime rather than depending on static C structure at compile 687 time. This is currently an experimental feature. 688 689- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 690 This feature creates a library of functions to be placed in ROM and thus 691 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 692 is 0. 693 694- ``V``: Verbose build. If assigned anything other than 0, the build commands 695 are printed. Default is 0. 696 697- ``VERSION_STRING``: String used in the log output for each TF-A image. 698 Defaults to a string formed by concatenating the version number, build type 699 and build string. 700 701- ``W``: Warning level. Some compiler warning options of interest have been 702 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 703 each level enabling more warning options. Default is 0. 704 705- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 706 the CPU after warm boot. This is applicable for platforms which do not 707 require interconnect programming to enable cache coherency (eg: single 708 cluster platforms). If this option is enabled, then warm boot path 709 enables D-caches immediately after enabling MMU. This option defaults to 0. 710 711- ``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory 712 tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The 713 default value of this flag is ``no``. Note this option must be enabled only 714 for ARM architecture greater than Armv8.5-A. 715 716- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 717 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 718 The default value of this flag is ``0``. 719 720 ``AT`` speculative errata workaround disables stage1 page table walk for 721 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 722 produces either the correct result or failure without TLB allocation. 723 724 This boolean option enables errata for all below CPUs. 725 726 +---------+--------------+-------------------------+ 727 | Errata | CPU | Workaround Define | 728 +=========+==============+=========================+ 729 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 730 +---------+--------------+-------------------------+ 731 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 732 +---------+--------------+-------------------------+ 733 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 734 +---------+--------------+-------------------------+ 735 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 736 +---------+--------------+-------------------------+ 737 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 738 +---------+--------------+-------------------------+ 739 740 .. note:: 741 This option is enabled by build only if platform sets any of above defines 742 mentioned in ’Workaround Define' column in the table. 743 If this option is enabled for the EL3 software then EL2 software also must 744 implement this workaround due to the behaviour of the errata mentioned 745 in new SDEN document which will get published soon. 746 747- ``RAS_TRAP_LOWER_EL_ERR_ACCESS``: This flag enables/disables the SCR_EL3.TERR 748 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 749 This flag is disabled by default. 750 751- ``OPENSSL_DIR``: This flag is used to provide the installed openssl directory 752 path on the host machine which is used to build certificate generation and 753 firmware encryption tool. 754 755- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 756 functions that wait for an arbitrary time length (udelay and mdelay). The 757 default value is 0. 758 759GICv3 driver options 760-------------------- 761 762GICv3 driver files are included using directive: 763 764``include drivers/arm/gic/v3/gicv3.mk`` 765 766The driver can be configured with the following options set in the platform 767makefile: 768 769- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 770 Enabling this option will add runtime detection support for the 771 GIC-600, so is safe to select even for a GIC500 implementation. 772 This option defaults to 0. 773 774- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 775 functionality. This option defaults to 0 776 777- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 778 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 779 functions. This is required for FVP platform which need to simulate GIC save 780 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 781 782- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 783 This option defaults to 0. 784 785- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 786 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 787 788Debugging options 789----------------- 790 791To compile a debug version and make the build more verbose use 792 793.. code:: shell 794 795 make PLAT=<platform> DEBUG=1 V=1 all 796 797AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for 798example DS-5) might not support this and may need an older version of DWARF 799symbols to be emitted by GCC. This can be achieved by using the 800``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the 801version to 2 is recommended for DS-5 versions older than 5.16. 802 803When debugging logic problems it might also be useful to disable all compiler 804optimizations by using ``-O0``. 805 806.. warning:: 807 Using ``-O0`` could cause output images to be larger and base addresses 808 might need to be recalculated (see the **Memory layout on Arm development 809 platforms** section in the :ref:`Firmware Design`). 810 811Extra debug options can be passed to the build system by setting ``CFLAGS`` or 812``LDFLAGS``: 813 814.. code:: shell 815 816 CFLAGS='-O0 -gdwarf-2' \ 817 make PLAT=<platform> DEBUG=1 V=1 all 818 819Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 820ignored as the linker is called directly. 821 822It is also possible to introduce an infinite loop to help in debugging the 823post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 824``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 825section. In this case, the developer may take control of the target using a 826debugger when indicated by the console output. When using DS-5, the following 827commands can be used: 828 829:: 830 831 # Stop target execution 832 interrupt 833 834 # 835 # Prepare your debugging environment, e.g. set breakpoints 836 # 837 838 # Jump over the debug loop 839 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 840 841 # Resume execution 842 continue 843 844-------------- 845 846*Copyright (c) 2019-2020, Arm Limited. All rights reserved.* 847