1Firmware Design 2=============== 3 4Trusted Firmware-A (TF-A) implements a subset of the Trusted Board Boot 5Requirements (TBBR) Platform Design Document (PDD) for Arm reference 6platforms. 7 8The TBB sequence starts when the platform is powered on and runs up 9to the stage where it hands-off control to firmware running in the normal 10world in DRAM. This is the cold boot path. 11 12TF-A also implements the `Power State Coordination Interface PDD`_ as a 13runtime service. PSCI is the interface from normal world software to firmware 14implementing power management use-cases (for example, secondary CPU boot, 15hotplug and idle). Normal world software can access TF-A runtime services via 16the Arm SMC (Secure Monitor Call) instruction. The SMC instruction must be 17used as mandated by the SMC Calling Convention (`SMCCC`_). 18 19TF-A implements a framework for configuring and managing interrupts generated 20in either security state. The details of the interrupt management framework 21and its design can be found in :ref:`Interrupt Management Framework`. 22 23TF-A also implements a library for setting up and managing the translation 24tables. The details of this library can be found in 25:ref:`Translation (XLAT) Tables Library`. 26 27TF-A can be built to support either AArch64 or AArch32 execution state. 28 29Cold boot 30--------- 31 32The cold boot path starts when the platform is physically turned on. If 33``COLD_BOOT_SINGLE_CPU=0``, one of the CPUs released from reset is chosen as the 34primary CPU, and the remaining CPUs are considered secondary CPUs. The primary 35CPU is chosen through platform-specific means. The cold boot path is mainly 36executed by the primary CPU, other than essential CPU initialization executed by 37all CPUs. The secondary CPUs are kept in a safe platform-specific state until 38the primary CPU has performed enough initialization to boot them. 39 40Refer to the :ref:`CPU Reset` for more information on the effect of the 41``COLD_BOOT_SINGLE_CPU`` platform build option. 42 43The cold boot path in this implementation of TF-A depends on the execution 44state. For AArch64, it is divided into five steps (in order of execution): 45 46- Boot Loader stage 1 (BL1) *AP Trusted ROM* 47- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 48- Boot Loader stage 3-1 (BL31) *EL3 Runtime Software* 49- Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional) 50- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 51 52For AArch32, it is divided into four steps (in order of execution): 53 54- Boot Loader stage 1 (BL1) *AP Trusted ROM* 55- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 56- Boot Loader stage 3-2 (BL32) *EL3 Runtime Software* 57- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 58 59Arm development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a 60combination of the following types of memory regions. Each bootloader stage uses 61one or more of these memory regions. 62 63- Regions accessible from both non-secure and secure states. For example, 64 non-trusted SRAM, ROM and DRAM. 65- Regions accessible from only the secure state. For example, trusted SRAM and 66 ROM. The FVPs also implement the trusted DRAM which is statically 67 configured. Additionally, the Base FVPs and Juno development platform 68 configure the TrustZone Controller (TZC) to create a region in the DRAM 69 which is accessible only from the secure state. 70 71The sections below provide the following details: 72 73- dynamic configuration of Boot Loader stages 74- initialization and execution of the first three stages during cold boot 75- specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for 76 AArch32) entrypoint requirements for use by alternative Trusted Boot 77 Firmware in place of the provided BL1 and BL2 78 79Dynamic Configuration during cold boot 80~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 81 82Each of the Boot Loader stages may be dynamically configured if required by the 83platform. The Boot Loader stage may optionally specify a firmware 84configuration file and/or hardware configuration file as listed below: 85 86- HW_CONFIG - The hardware configuration file. Can be shared by all Boot Loader 87 stages and also by the Normal World Rich OS. 88- TB_FW_CONFIG - Trusted Boot Firmware configuration file. Shared between BL1 89 and BL2. 90- SOC_FW_CONFIG - SoC Firmware configuration file. Used by BL31. 91- TOS_FW_CONFIG - Trusted OS Firmware configuration file. Used by Trusted OS 92 (BL32). 93- NT_FW_CONFIG - Non Trusted Firmware configuration file. Used by Non-trusted 94 firmware (BL33). 95 96The Arm development platforms use the Flattened Device Tree format for the 97dynamic configuration files. 98 99Each Boot Loader stage can pass up to 4 arguments via registers to the next 100stage. BL2 passes the list of the next images to execute to the *EL3 Runtime 101Software* (BL31 for AArch64 and BL32 for AArch32) via `arg0`. All the other 102arguments are platform defined. The Arm development platforms use the following 103convention: 104 105- BL1 passes the address of a meminfo_t structure to BL2 via ``arg1``. This 106 structure contains the memory layout available to BL2. 107- When dynamic configuration files are present, the firmware configuration for 108 the next Boot Loader stage is populated in the first available argument and 109 the generic hardware configuration is passed the next available argument. 110 For example, 111 112 - If TB_FW_CONFIG is loaded by BL1, then its address is passed in ``arg0`` 113 to BL2. 114 - If HW_CONFIG is loaded by BL1, then its address is passed in ``arg2`` to 115 BL2. Note, ``arg1`` is already used for meminfo_t. 116 - If SOC_FW_CONFIG is loaded by BL2, then its address is passed in ``arg1`` 117 to BL31. Note, ``arg0`` is used to pass the list of executable images. 118 - Similarly, if HW_CONFIG is loaded by BL1 or BL2, then its address is 119 passed in ``arg2`` to BL31. 120 - For other BL3x images, if the firmware configuration file is loaded by 121 BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded 122 then its address is passed in ``arg1``. 123 124BL1 125~~~ 126 127This stage begins execution from the platform's reset vector at EL3. The reset 128address is platform dependent but it is usually located in a Trusted ROM area. 129The BL1 data section is copied to trusted SRAM at runtime. 130 131On the Arm development platforms, BL1 code starts execution from the reset 132vector defined by the constant ``BL1_RO_BASE``. The BL1 data section is copied 133to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``. 134 135The functionality implemented by this stage is as follows. 136 137Determination of boot path 138^^^^^^^^^^^^^^^^^^^^^^^^^^ 139 140Whenever a CPU is released from reset, BL1 needs to distinguish between a warm 141boot and a cold boot. This is done using platform-specific mechanisms (see the 142``plat_get_my_entrypoint()`` function in the :ref:`Porting Guide`). In the case 143of a warm boot, a CPU is expected to continue execution from a separate 144entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe 145platform-specific state (see the ``plat_secondary_cold_boot_setup()`` function in 146the :ref:`Porting Guide`) while the primary CPU executes the remaining cold boot 147path as described in the following sections. 148 149This step only applies when ``PROGRAMMABLE_RESET_ADDRESS=0``. Refer to the 150:ref:`CPU Reset` for more information on the effect of the 151``PROGRAMMABLE_RESET_ADDRESS`` platform build option. 152 153Architectural initialization 154^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 155 156BL1 performs minimal architectural initialization as follows. 157 158- Exception vectors 159 160 BL1 sets up simple exception vectors for both synchronous and asynchronous 161 exceptions. The default behavior upon receiving an exception is to populate 162 a status code in the general purpose register ``X0/R0`` and call the 163 ``plat_report_exception()`` function (see the :ref:`Porting Guide`). The 164 status code is one of: 165 166 For AArch64: 167 168 :: 169 170 0x0 : Synchronous exception from Current EL with SP_EL0 171 0x1 : IRQ exception from Current EL with SP_EL0 172 0x2 : FIQ exception from Current EL with SP_EL0 173 0x3 : System Error exception from Current EL with SP_EL0 174 0x4 : Synchronous exception from Current EL with SP_ELx 175 0x5 : IRQ exception from Current EL with SP_ELx 176 0x6 : FIQ exception from Current EL with SP_ELx 177 0x7 : System Error exception from Current EL with SP_ELx 178 0x8 : Synchronous exception from Lower EL using aarch64 179 0x9 : IRQ exception from Lower EL using aarch64 180 0xa : FIQ exception from Lower EL using aarch64 181 0xb : System Error exception from Lower EL using aarch64 182 0xc : Synchronous exception from Lower EL using aarch32 183 0xd : IRQ exception from Lower EL using aarch32 184 0xe : FIQ exception from Lower EL using aarch32 185 0xf : System Error exception from Lower EL using aarch32 186 187 For AArch32: 188 189 :: 190 191 0x10 : User mode 192 0x11 : FIQ mode 193 0x12 : IRQ mode 194 0x13 : SVC mode 195 0x16 : Monitor mode 196 0x17 : Abort mode 197 0x1a : Hypervisor mode 198 0x1b : Undefined mode 199 0x1f : System mode 200 201 The ``plat_report_exception()`` implementation on the Arm FVP port programs 202 the Versatile Express System LED register in the following format to 203 indicate the occurrence of an unexpected exception: 204 205 :: 206 207 SYS_LED[0] - Security state (Secure=0/Non-Secure=1) 208 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0) 209 For AArch32 it is always 0x0 210 SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value 211 of the status code 212 213 A write to the LED register reflects in the System LEDs (S6LED0..7) in the 214 CLCD window of the FVP. 215 216 BL1 does not expect to receive any exceptions other than the SMC exception. 217 For the latter, BL1 installs a simple stub. The stub expects to receive a 218 limited set of SMC types (determined by their function IDs in the general 219 purpose register ``X0/R0``): 220 221 - ``BL1_SMC_RUN_IMAGE``: This SMC is raised by BL2 to make BL1 pass control 222 to EL3 Runtime Software. 223 - All SMCs listed in section "BL1 SMC Interface" in the :ref:`Firmware Update (FWU)` 224 Design Guide are supported for AArch64 only. These SMCs are currently 225 not supported when BL1 is built for AArch32. 226 227 Any other SMC leads to an assertion failure. 228 229- CPU initialization 230 231 BL1 calls the ``reset_handler()`` function which in turn calls the CPU 232 specific reset handler function (see the section: "CPU specific operations 233 framework"). 234 235- Control register setup (for AArch64) 236 237 - ``SCTLR_EL3``. Instruction cache is enabled by setting the ``SCTLR_EL3.I`` 238 bit. Alignment and stack alignment checking is enabled by setting the 239 ``SCTLR_EL3.A`` and ``SCTLR_EL3.SA`` bits. Exception endianness is set to 240 little-endian by clearing the ``SCTLR_EL3.EE`` bit. 241 242 - ``SCR_EL3``. The register width of the next lower exception level is set 243 to AArch64 by setting the ``SCR.RW`` bit. The ``SCR.EA`` bit is set to trap 244 both External Aborts and SError Interrupts in EL3. The ``SCR.SIF`` bit is 245 also set to disable instruction fetches from Non-secure memory when in 246 secure state. 247 248 - ``CPTR_EL3``. Accesses to the ``CPACR_EL1`` register from EL1 or EL2, or the 249 ``CPTR_EL2`` register from EL2 are configured to not trap to EL3 by 250 clearing the ``CPTR_EL3.TCPAC`` bit. Access to the trace functionality is 251 configured not to trap to EL3 by clearing the ``CPTR_EL3.TTA`` bit. 252 Instructions that access the registers associated with Floating Point 253 and Advanced SIMD execution are configured to not trap to EL3 by 254 clearing the ``CPTR_EL3.TFP`` bit. 255 256 - ``DAIF``. The SError interrupt is enabled by clearing the SError interrupt 257 mask bit. 258 259 - ``MDCR_EL3``. The trap controls, ``MDCR_EL3.TDOSA``, ``MDCR_EL3.TDA`` and 260 ``MDCR_EL3.TPM``, are set so that accesses to the registers they control 261 do not trap to EL3. AArch64 Secure self-hosted debug is disabled by 262 setting the ``MDCR_EL3.SDD`` bit. Also ``MDCR_EL3.SPD32`` is set to 263 disable AArch32 Secure self-hosted privileged debug from S-EL1. 264 265- Control register setup (for AArch32) 266 267 - ``SCTLR``. Instruction cache is enabled by setting the ``SCTLR.I`` bit. 268 Alignment checking is enabled by setting the ``SCTLR.A`` bit. 269 Exception endianness is set to little-endian by clearing the 270 ``SCTLR.EE`` bit. 271 272 - ``SCR``. The ``SCR.SIF`` bit is set to disable instruction fetches from 273 Non-secure memory when in secure state. 274 275 - ``CPACR``. Allow execution of Advanced SIMD instructions at PL0 and PL1, 276 by clearing the ``CPACR.ASEDIS`` bit. Access to the trace functionality 277 is configured not to trap to undefined mode by clearing the 278 ``CPACR.TRCDIS`` bit. 279 280 - ``NSACR``. Enable non-secure access to Advanced SIMD functionality and 281 system register access to implemented trace registers. 282 283 - ``FPEXC``. Enable access to the Advanced SIMD and floating-point 284 functionality from all Exception levels. 285 286 - ``CPSR.A``. The Asynchronous data abort interrupt is enabled by clearing 287 the Asynchronous data abort interrupt mask bit. 288 289 - ``SDCR``. The ``SDCR.SPD`` field is set to disable AArch32 Secure 290 self-hosted privileged debug. 291 292Platform initialization 293^^^^^^^^^^^^^^^^^^^^^^^ 294 295On Arm platforms, BL1 performs the following platform initializations: 296 297- Enable the Trusted Watchdog. 298- Initialize the console. 299- Configure the Interconnect to enable hardware coherency. 300- Enable the MMU and map the memory it needs to access. 301- Configure any required platform storage to load the next bootloader image 302 (BL2). 303- If the BL1 dynamic configuration file, ``TB_FW_CONFIG``, is available, then 304 load it to the platform defined address and make it available to BL2 via 305 ``arg0``. 306- Configure the system timer and program the `CNTFRQ_EL0` for use by NS-BL1U 307 and NS-BL2U firmware update images. 308 309Firmware Update detection and execution 310^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 311 312After performing platform setup, BL1 common code calls 313``bl1_plat_get_next_image_id()`` to determine if :ref:`Firmware Update (FWU)` is 314required or to proceed with the normal boot process. If the platform code 315returns ``BL2_IMAGE_ID`` then the normal boot sequence is executed as described 316in the next section, else BL1 assumes that :ref:`Firmware Update (FWU)` is 317required and execution passes to the first image in the 318:ref:`Firmware Update (FWU)` process. In either case, BL1 retrieves a descriptor 319of the next image by calling ``bl1_plat_get_image_desc()``. The image descriptor 320contains an ``entry_point_info_t`` structure, which BL1 uses to initialize the 321execution state of the next image. 322 323BL2 image load and execution 324^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 325 326In the normal boot flow, BL1 execution continues as follows: 327 328#. BL1 prints the following string from the primary CPU to indicate successful 329 execution of the BL1 stage: 330 331 :: 332 333 "Booting Trusted Firmware" 334 335#. BL1 loads a BL2 raw binary image from platform storage, at a 336 platform-specific base address. Prior to the load, BL1 invokes 337 ``bl1_plat_handle_pre_image_load()`` which allows the platform to update or 338 use the image information. If the BL2 image file is not present or if 339 there is not enough free trusted SRAM the following error message is 340 printed: 341 342 :: 343 344 "Failed to load BL2 firmware." 345 346#. BL1 invokes ``bl1_plat_handle_post_image_load()`` which again is intended 347 for platforms to take further action after image load. This function must 348 populate the necessary arguments for BL2, which may also include the memory 349 layout. Further description of the memory layout can be found later 350 in this document. 351 352#. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at 353 Secure SVC mode (for AArch32), starting from its load address. 354 355BL2 356~~~ 357 358BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure 359SVC mode (for AArch32) . BL2 is linked against and loaded at a platform-specific 360base address (more information can be found later in this document). 361The functionality implemented by BL2 is as follows. 362 363Architectural initialization 364^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 365 366For AArch64, BL2 performs the minimal architectural initialization required 367for subsequent stages of TF-A and normal world software. EL1 and EL0 are given 368access to Floating Point and Advanced SIMD registers by clearing the 369``CPACR.FPEN`` bits. 370 371For AArch32, the minimal architectural initialization required for subsequent 372stages of TF-A and normal world software is taken care of in BL1 as both BL1 373and BL2 execute at PL1. 374 375Platform initialization 376^^^^^^^^^^^^^^^^^^^^^^^ 377 378On Arm platforms, BL2 performs the following platform initializations: 379 380- Initialize the console. 381- Configure any required platform storage to allow loading further bootloader 382 images. 383- Enable the MMU and map the memory it needs to access. 384- Perform platform security setup to allow access to controlled components. 385- Reserve some memory for passing information to the next bootloader image 386 EL3 Runtime Software and populate it. 387- Define the extents of memory available for loading each subsequent 388 bootloader image. 389- If BL1 has passed TB_FW_CONFIG dynamic configuration file in ``arg0``, 390 then parse it. 391 392Image loading in BL2 393^^^^^^^^^^^^^^^^^^^^ 394 395BL2 generic code loads the images based on the list of loadable images 396provided by the platform. BL2 passes the list of executable images 397provided by the platform to the next handover BL image. 398 399The list of loadable images provided by the platform may also contain 400dynamic configuration files. The files are loaded and can be parsed as 401needed in the ``bl2_plat_handle_post_image_load()`` function. These 402configuration files can be passed to next Boot Loader stages as arguments 403by updating the corresponding entrypoint information in this function. 404 405SCP_BL2 (System Control Processor Firmware) image load 406^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 407 408Some systems have a separate System Control Processor (SCP) for power, clock, 409reset and system control. BL2 loads the optional SCP_BL2 image from platform 410storage into a platform-specific region of secure memory. The subsequent 411handling of SCP_BL2 is platform specific. For example, on the Juno Arm 412development platform port the image is transferred into SCP's internal memory 413using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM 414memory. The SCP executes SCP_BL2 and signals to the Application Processor (AP) 415for BL2 execution to continue. 416 417EL3 Runtime Software image load 418^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 419 420BL2 loads the EL3 Runtime Software image from platform storage into a platform- 421specific address in trusted SRAM. If there is not enough memory to load the 422image or image is missing it leads to an assertion failure. 423 424AArch64 BL32 (Secure-EL1 Payload) image load 425^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 426 427BL2 loads the optional BL32 image from platform storage into a platform- 428specific region of secure memory. The image executes in the secure world. BL2 429relies on BL31 to pass control to the BL32 image, if present. Hence, BL2 430populates a platform-specific area of memory with the entrypoint/load-address 431of the BL32 image. The value of the Saved Processor Status Register (``SPSR``) 432for entry into BL32 is not determined by BL2, it is initialized by the 433Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for 434managing interaction with BL32. This information is passed to BL31. 435 436BL33 (Non-trusted Firmware) image load 437^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 438 439BL2 loads the BL33 image (e.g. UEFI or other test or boot software) from 440platform storage into non-secure memory as defined by the platform. 441 442BL2 relies on EL3 Runtime Software to pass control to BL33 once secure state 443initialization is complete. Hence, BL2 populates a platform-specific area of 444memory with the entrypoint and Saved Program Status Register (``SPSR``) of the 445normal world software image. The entrypoint is the load address of the BL33 446image. The ``SPSR`` is determined as specified in Section 5.13 of the 447`Power State Coordination Interface PDD`_. This information is passed to the 448EL3 Runtime Software. 449 450AArch64 BL31 (EL3 Runtime Software) execution 451^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 452 453BL2 execution continues as follows: 454 455#. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the 456 BL31 entrypoint. The exception is handled by the SMC exception handler 457 installed by BL1. 458 459#. BL1 turns off the MMU and flushes the caches. It clears the 460 ``SCTLR_EL3.M/I/C`` bits, flushes the data cache to the point of coherency 461 and invalidates the TLBs. 462 463#. BL1 passes control to BL31 at the specified entrypoint at EL3. 464 465Running BL2 at EL3 execution level 466~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 467 468Some platforms have a non-TF-A Boot ROM that expects the next boot stage 469to execute at EL3. On these platforms, TF-A BL1 is a waste of memory 470as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid 471this waste, a special mode enables BL2 to execute at EL3, which allows 472a non-TF-A Boot ROM to load and jump directly to BL2. This mode is selected 473when the build flag BL2_AT_EL3 is enabled. The main differences in this 474mode are: 475 476#. BL2 includes the reset code and the mailbox mechanism to differentiate 477 cold boot and warm boot. It runs at EL3 doing the arch 478 initialization required for EL3. 479 480#. BL2 does not receive the meminfo information from BL1 anymore. This 481 information can be passed by the Boot ROM or be internal to the 482 BL2 image. 483 484#. Since BL2 executes at EL3, BL2 jumps directly to the next image, 485 instead of invoking the RUN_IMAGE SMC call. 486 487 488We assume 3 different types of BootROM support on the platform: 489 490#. The Boot ROM always jumps to the same address, for both cold 491 and warm boot. In this case, we will need to keep a resident part 492 of BL2 whose memory cannot be reclaimed by any other image. The 493 linker script defines the symbols __TEXT_RESIDENT_START__ and 494 __TEXT_RESIDENT_END__ that allows the platform to configure 495 correctly the memory map. 496#. The platform has some mechanism to indicate the jump address to the 497 Boot ROM. Platform code can then program the jump address with 498 psci_warmboot_entrypoint during cold boot. 499#. The platform has some mechanism to program the reset address using 500 the PROGRAMMABLE_RESET_ADDRESS feature. Platform code can then 501 program the reset address with psci_warmboot_entrypoint during 502 cold boot, bypassing the boot ROM for warm boot. 503 504In the last 2 cases, no part of BL2 needs to remain resident at 505runtime. In the first 2 cases, we expect the Boot ROM to be able to 506differentiate between warm and cold boot, to avoid loading BL2 again 507during warm boot. 508 509This functionality can be tested with FVP loading the image directly 510in memory and changing the address where the system jumps at reset. 511For example: 512 513 -C cluster0.cpu0.RVBAR=0x4022000 514 --data cluster0.cpu0=bl2.bin@0x4022000 515 516With this configuration, FVP is like a platform of the first case, 517where the Boot ROM jumps always to the same address. For simplification, 518BL32 is loaded in DRAM in this case, to avoid other images reclaiming 519BL2 memory. 520 521 522AArch64 BL31 523~~~~~~~~~~~~ 524 525The image for this stage is loaded by BL2 and BL1 passes control to BL31 at 526EL3. BL31 executes solely in trusted SRAM. BL31 is linked against and 527loaded at a platform-specific base address (more information can be found later 528in this document). The functionality implemented by BL31 is as follows. 529 530Architectural initialization 531^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 532 533Currently, BL31 performs a similar architectural initialization to BL1 as 534far as system register settings are concerned. Since BL1 code resides in ROM, 535architectural initialization in BL31 allows override of any previous 536initialization done by BL1. 537 538BL31 initializes the per-CPU data framework, which provides a cache of 539frequently accessed per-CPU data optimised for fast, concurrent manipulation 540on different CPUs. This buffer includes pointers to per-CPU contexts, crash 541buffer, CPU reset and power down operations, PSCI data, platform data and so on. 542 543It then replaces the exception vectors populated by BL1 with its own. BL31 544exception vectors implement more elaborate support for handling SMCs since this 545is the only mechanism to access the runtime services implemented by BL31 (PSCI 546for example). BL31 checks each SMC for validity as specified by the 547`SMC Calling Convention PDD`_ before passing control to the required SMC 548handler routine. 549 550BL31 programs the ``CNTFRQ_EL0`` register with the clock frequency of the system 551counter, which is provided by the platform. 552 553Platform initialization 554^^^^^^^^^^^^^^^^^^^^^^^ 555 556BL31 performs detailed platform initialization, which enables normal world 557software to function correctly. 558 559On Arm platforms, this consists of the following: 560 561- Initialize the console. 562- Configure the Interconnect to enable hardware coherency. 563- Enable the MMU and map the memory it needs to access. 564- Initialize the generic interrupt controller. 565- Initialize the power controller device. 566- Detect the system topology. 567 568Runtime services initialization 569^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 570 571BL31 is responsible for initializing the runtime services. One of them is PSCI. 572 573As part of the PSCI initializations, BL31 detects the system topology. It also 574initializes the data structures that implement the state machine used to track 575the state of power domain nodes. The state can be one of ``OFF``, ``RUN`` or 576``RETENTION``. All secondary CPUs are initially in the ``OFF`` state. The cluster 577that the primary CPU belongs to is ``ON``; any other cluster is ``OFF``. It also 578initializes the locks that protect them. BL31 accesses the state of a CPU or 579cluster immediately after reset and before the data cache is enabled in the 580warm boot path. It is not currently possible to use 'exclusive' based spinlocks, 581therefore BL31 uses locks based on Lamport's Bakery algorithm instead. 582 583The runtime service framework and its initialization is described in more 584detail in the "EL3 runtime services framework" section below. 585 586Details about the status of the PSCI implementation are provided in the 587"Power State Coordination Interface" section below. 588 589AArch64 BL32 (Secure-EL1 Payload) image initialization 590^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 591 592If a BL32 image is present then there must be a matching Secure-EL1 Payload 593Dispatcher (SPD) service (see later for details). During initialization 594that service must register a function to carry out initialization of BL32 595once the runtime services are fully initialized. BL31 invokes such a 596registered function to initialize BL32 before running BL33. This initialization 597is not necessary for AArch32 SPs. 598 599Details on BL32 initialization and the SPD's role are described in the 600:ref:`firmware_design_sel1_spd` section below. 601 602BL33 (Non-trusted Firmware) execution 603^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 604 605EL3 Runtime Software initializes the EL2 or EL1 processor context for normal- 606world cold boot, ensuring that no secure state information finds its way into 607the non-secure execution state. EL3 Runtime Software uses the entrypoint 608information provided by BL2 to jump to the Non-trusted firmware image (BL33) 609at the highest available Exception Level (EL2 if available, otherwise EL1). 610 611Using alternative Trusted Boot Firmware in place of BL1 & BL2 (AArch64 only) 612~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 613 614Some platforms have existing implementations of Trusted Boot Firmware that 615would like to use TF-A BL31 for the EL3 Runtime Software. To enable this 616firmware architecture it is important to provide a fully documented and stable 617interface between the Trusted Boot Firmware and BL31. 618 619Future changes to the BL31 interface will be done in a backwards compatible 620way, and this enables these firmware components to be independently enhanced/ 621updated to develop and exploit new functionality. 622 623Required CPU state when calling ``bl31_entrypoint()`` during cold boot 624^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 625 626This function must only be called by the primary CPU. 627 628On entry to this function the calling primary CPU must be executing in AArch64 629EL3, little-endian data access, and all interrupt sources masked: 630 631:: 632 633 PSTATE.EL = 3 634 PSTATE.RW = 1 635 PSTATE.DAIF = 0xf 636 SCTLR_EL3.EE = 0 637 638X0 and X1 can be used to pass information from the Trusted Boot Firmware to the 639platform code in BL31: 640 641:: 642 643 X0 : Reserved for common TF-A information 644 X1 : Platform specific information 645 646BL31 zero-init sections (e.g. ``.bss``) should not contain valid data on entry, 647these will be zero filled prior to invoking platform setup code. 648 649Use of the X0 and X1 parameters 650''''''''''''''''''''''''''''''' 651 652The parameters are platform specific and passed from ``bl31_entrypoint()`` to 653``bl31_early_platform_setup()``. The value of these parameters is never directly 654used by the common BL31 code. 655 656The convention is that ``X0`` conveys information regarding the BL31, BL32 and 657BL33 images from the Trusted Boot firmware and ``X1`` can be used for other 658platform specific purpose. This convention allows platforms which use TF-A's 659BL1 and BL2 images to transfer additional platform specific information from 660Secure Boot without conflicting with future evolution of TF-A using ``X0`` to 661pass a ``bl31_params`` structure. 662 663BL31 common and SPD initialization code depends on image and entrypoint 664information about BL33 and BL32, which is provided via BL31 platform APIs. 665This information is required until the start of execution of BL33. This 666information can be provided in a platform defined manner, e.g. compiled into 667the platform code in BL31, or provided in a platform defined memory location 668by the Trusted Boot firmware, or passed from the Trusted Boot Firmware via the 669Cold boot Initialization parameters. This data may need to be cleaned out of 670the CPU caches if it is provided by an earlier boot stage and then accessed by 671BL31 platform code before the caches are enabled. 672 673TF-A's BL2 implementation passes a ``bl31_params`` structure in 674``X0`` and the Arm development platforms interpret this in the BL31 platform 675code. 676 677MMU, Data caches & Coherency 678'''''''''''''''''''''''''''' 679 680BL31 does not depend on the enabled state of the MMU, data caches or 681interconnect coherency on entry to ``bl31_entrypoint()``. If these are disabled 682on entry, these should be enabled during ``bl31_plat_arch_setup()``. 683 684Data structures used in the BL31 cold boot interface 685'''''''''''''''''''''''''''''''''''''''''''''''''''' 686 687These structures are designed to support compatibility and independent 688evolution of the structures and the firmware images. For example, a version of 689BL31 that can interpret the BL3x image information from different versions of 690BL2, a platform that uses an extended entry_point_info structure to convey 691additional register information to BL31, or a ELF image loader that can convey 692more details about the firmware images. 693 694To support these scenarios the structures are versioned and sized, which enables 695BL31 to detect which information is present and respond appropriately. The 696``param_header`` is defined to capture this information: 697 698.. code:: c 699 700 typedef struct param_header { 701 uint8_t type; /* type of the structure */ 702 uint8_t version; /* version of this structure */ 703 uint16_t size; /* size of this structure in bytes */ 704 uint32_t attr; /* attributes: unused bits SBZ */ 705 } param_header_t; 706 707The structures using this format are ``entry_point_info``, ``image_info`` and 708``bl31_params``. The code that allocates and populates these structures must set 709the header fields appropriately, and the ``SET_PARAM_HEAD()`` a macro is defined 710to simplify this action. 711 712Required CPU state for BL31 Warm boot initialization 713^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 714 715When requesting a CPU power-on, or suspending a running CPU, TF-A provides 716the platform power management code with a Warm boot initialization 717entry-point, to be invoked by the CPU immediately after the reset handler. 718On entry to the Warm boot initialization function the calling CPU must be in 719AArch64 EL3, little-endian data access and all interrupt sources masked: 720 721:: 722 723 PSTATE.EL = 3 724 PSTATE.RW = 1 725 PSTATE.DAIF = 0xf 726 SCTLR_EL3.EE = 0 727 728The PSCI implementation will initialize the processor state and ensure that the 729platform power management code is then invoked as required to initialize all 730necessary system, cluster and CPU resources. 731 732AArch32 EL3 Runtime Software entrypoint interface 733~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 734 735To enable this firmware architecture it is important to provide a fully 736documented and stable interface between the Trusted Boot Firmware and the 737AArch32 EL3 Runtime Software. 738 739Future changes to the entrypoint interface will be done in a backwards 740compatible way, and this enables these firmware components to be independently 741enhanced/updated to develop and exploit new functionality. 742 743Required CPU state when entering during cold boot 744^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 745 746This function must only be called by the primary CPU. 747 748On entry to this function the calling primary CPU must be executing in AArch32 749EL3, little-endian data access, and all interrupt sources masked: 750 751:: 752 753 PSTATE.AIF = 0x7 754 SCTLR.EE = 0 755 756R0 and R1 are used to pass information from the Trusted Boot Firmware to the 757platform code in AArch32 EL3 Runtime Software: 758 759:: 760 761 R0 : Reserved for common TF-A information 762 R1 : Platform specific information 763 764Use of the R0 and R1 parameters 765''''''''''''''''''''''''''''''' 766 767The parameters are platform specific and the convention is that ``R0`` conveys 768information regarding the BL3x images from the Trusted Boot firmware and ``R1`` 769can be used for other platform specific purpose. This convention allows 770platforms which use TF-A's BL1 and BL2 images to transfer additional platform 771specific information from Secure Boot without conflicting with future 772evolution of TF-A using ``R0`` to pass a ``bl_params`` structure. 773 774The AArch32 EL3 Runtime Software is responsible for entry into BL33. This 775information can be obtained in a platform defined manner, e.g. compiled into 776the AArch32 EL3 Runtime Software, or provided in a platform defined memory 777location by the Trusted Boot firmware, or passed from the Trusted Boot Firmware 778via the Cold boot Initialization parameters. This data may need to be cleaned 779out of the CPU caches if it is provided by an earlier boot stage and then 780accessed by AArch32 EL3 Runtime Software before the caches are enabled. 781 782When using AArch32 EL3 Runtime Software, the Arm development platforms pass a 783``bl_params`` structure in ``R0`` from BL2 to be interpreted by AArch32 EL3 Runtime 784Software platform code. 785 786MMU, Data caches & Coherency 787'''''''''''''''''''''''''''' 788 789AArch32 EL3 Runtime Software must not depend on the enabled state of the MMU, 790data caches or interconnect coherency in its entrypoint. They must be explicitly 791enabled if required. 792 793Data structures used in cold boot interface 794''''''''''''''''''''''''''''''''''''''''''' 795 796The AArch32 EL3 Runtime Software cold boot interface uses ``bl_params`` instead 797of ``bl31_params``. The ``bl_params`` structure is based on the convention 798described in AArch64 BL31 cold boot interface section. 799 800Required CPU state for warm boot initialization 801^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 802 803When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3 804Runtime Software must ensure execution of a warm boot initialization entrypoint. 805If TF-A BL1 is used and the PROGRAMMABLE_RESET_ADDRESS build flag is false, 806then AArch32 EL3 Runtime Software must ensure that BL1 branches to the warm 807boot entrypoint by arranging for the BL1 platform function, 808plat_get_my_entrypoint(), to return a non-zero value. 809 810In this case, the warm boot entrypoint must be in AArch32 EL3, little-endian 811data access and all interrupt sources masked: 812 813:: 814 815 PSTATE.AIF = 0x7 816 SCTLR.EE = 0 817 818The warm boot entrypoint may be implemented by using TF-A 819``psci_warmboot_entrypoint()`` function. In that case, the platform must fulfil 820the pre-requisites mentioned in the 821:ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`. 822 823EL3 runtime services framework 824------------------------------ 825 826Software executing in the non-secure state and in the secure state at exception 827levels lower than EL3 will request runtime services using the Secure Monitor 828Call (SMC) instruction. These requests will follow the convention described in 829the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function 830identifiers to each SMC request and describes how arguments are passed and 831returned. 832 833The EL3 runtime services framework enables the development of services by 834different providers that can be easily integrated into final product firmware. 835The following sections describe the framework which facilitates the 836registration, initialization and use of runtime services in EL3 Runtime 837Software (BL31). 838 839The design of the runtime services depends heavily on the concepts and 840definitions described in the `SMCCC`_, in particular SMC Function IDs, Owning 841Entity Numbers (OEN), Fast and Yielding calls, and the SMC32 and SMC64 calling 842conventions. Please refer to that document for more detailed explanation of 843these terms. 844 845The following runtime services are expected to be implemented first. They have 846not all been instantiated in the current implementation. 847 848#. Standard service calls 849 850 This service is for management of the entire system. The Power State 851 Coordination Interface (`PSCI`_) is the first set of standard service calls 852 defined by Arm (see PSCI section later). 853 854#. Secure-EL1 Payload Dispatcher service 855 856 If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then 857 it also requires a *Secure Monitor* at EL3 to switch the EL1 processor 858 context between the normal world (EL1/EL2) and trusted world (Secure-EL1). 859 The Secure Monitor will make these world switches in response to SMCs. The 860 `SMCCC`_ provides for such SMCs with the Trusted OS Call and Trusted 861 Application Call OEN ranges. 862 863 The interface between the EL3 Runtime Software and the Secure-EL1 Payload is 864 not defined by the `SMCCC`_ or any other standard. As a result, each 865 Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime 866 service - within TF-A this service is referred to as the Secure-EL1 Payload 867 Dispatcher (SPD). 868 869 TF-A provides a Test Secure-EL1 Payload (TSP) and its associated Dispatcher 870 (TSPD). Details of SPD design and TSP/TSPD operation are described in the 871 :ref:`firmware_design_sel1_spd` section below. 872 873#. CPU implementation service 874 875 This service will provide an interface to CPU implementation specific 876 services for a given platform e.g. access to processor errata workarounds. 877 This service is currently unimplemented. 878 879Additional services for Arm Architecture, SiP and OEM calls can be implemented. 880Each implemented service handles a range of SMC function identifiers as 881described in the `SMCCC`_. 882 883Registration 884~~~~~~~~~~~~ 885 886A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying 887the name of the service, the range of OENs covered, the type of service and 888initialization and call handler functions. This macro instantiates a ``const struct rt_svc_desc`` for the service with these details (see ``runtime_svc.h``). 889This structure is allocated in a special ELF section ``rt_svc_descs``, enabling 890the framework to find all service descriptors included into BL31. 891 892The specific service for a SMC Function is selected based on the OEN and call 893type of the Function ID, and the framework uses that information in the service 894descriptor to identify the handler for the SMC Call. 895 896The service descriptors do not include information to identify the precise set 897of SMC function identifiers supported by this service implementation, the 898security state from which such calls are valid nor the capability to support 89964-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately 900to these aspects of a SMC call is the responsibility of the service 901implementation, the framework is focused on integration of services from 902different providers and minimizing the time taken by the framework before the 903service handler is invoked. 904 905Details of the parameters, requirements and behavior of the initialization and 906call handling functions are provided in the following sections. 907 908Initialization 909~~~~~~~~~~~~~~ 910 911``runtime_svc_init()`` in ``runtime_svc.c`` initializes the runtime services 912framework running on the primary CPU during cold boot as part of the BL31 913initialization. This happens prior to initializing a Trusted OS and running 914Normal world boot firmware that might in turn use these services. 915Initialization involves validating each of the declared runtime service 916descriptors, calling the service initialization function and populating the 917index used for runtime lookup of the service. 918 919The BL31 linker script collects all of the declared service descriptors into a 920single array and defines symbols that allow the framework to locate and traverse 921the array, and determine its size. 922 923The framework does basic validation of each descriptor to halt firmware 924initialization if service declaration errors are detected. The framework does 925not check descriptors for the following error conditions, and may behave in an 926unpredictable manner under such scenarios: 927 928#. Overlapping OEN ranges 929#. Multiple descriptors for the same range of OENs and ``call_type`` 930#. Incorrect range of owning entity numbers for a given ``call_type`` 931 932Once validated, the service ``init()`` callback is invoked. This function carries 933out any essential EL3 initialization before servicing requests. The ``init()`` 934function is only invoked on the primary CPU during cold boot. If the service 935uses per-CPU data this must either be initialized for all CPUs during this call, 936or be done lazily when a CPU first issues an SMC call to that service. If 937``init()`` returns anything other than ``0``, this is treated as an initialization 938error and the service is ignored: this does not cause the firmware to halt. 939 940The OEN and call type fields present in the SMC Function ID cover a total of 941128 distinct services, but in practice a single descriptor can cover a range of 942OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a 943service handler, the framework uses an array of 128 indices that map every 944distinct OEN/call-type combination either to one of the declared services or to 945indicate the service is not handled. This ``rt_svc_descs_indices[]`` array is 946populated for all of the OENs covered by a service after the service ``init()`` 947function has reported success. So a service that fails to initialize will never 948have it's ``handle()`` function invoked. 949 950The following figure shows how the ``rt_svc_descs_indices[]`` index maps the SMC 951Function ID call type and OEN onto a specific service handler in the 952``rt_svc_descs[]`` array. 953 954|Image 1| 955 956Handling an SMC 957~~~~~~~~~~~~~~~ 958 959When the EL3 runtime services framework receives a Secure Monitor Call, the SMC 960Function ID is passed in W0 from the lower exception level (as per the 961`SMCCC`_). If the calling register width is AArch32, it is invalid to invoke an 962SMC Function which indicates the SMC64 calling convention: such calls are 963ignored and return the Unknown SMC Function Identifier result code ``0xFFFFFFFF`` 964in R0/X0. 965 966Bit[31] (fast/yielding call) and bits[29:24] (owning entity number) of the SMC 967Function ID are combined to index into the ``rt_svc_descs_indices[]`` array. The 968resulting value might indicate a service that has no handler, in this case the 969framework will also report an Unknown SMC Function ID. Otherwise, the value is 970used as a further index into the ``rt_svc_descs[]`` array to locate the required 971service and handler. 972 973The service's ``handle()`` callback is provided with five of the SMC parameters 974directly, the others are saved into memory for retrieval (if needed) by the 975handler. The handler is also provided with an opaque ``handle`` for use with the 976supporting library for parameter retrieval, setting return values and context 977manipulation; and with ``flags`` indicating the security state of the caller. The 978framework finally sets up the execution stack for the handler, and invokes the 979services ``handle()`` function. 980 981On return from the handler the result registers are populated in X0-X7 as needed 982before restoring the stack and CPU state and returning from the original SMC. 983 984Exception Handling Framework 985---------------------------- 986 987Please refer to the `Exception Handling Framework`_ document. 988 989Power State Coordination Interface 990---------------------------------- 991 992TODO: Provide design walkthrough of PSCI implementation. 993 994The PSCI v1.1 specification categorizes APIs as optional and mandatory. All the 995mandatory APIs in PSCI v1.1, PSCI v1.0 and in PSCI v0.2 draft specification 996`Power State Coordination Interface PDD`_ are implemented. The table lists 997the PSCI v1.1 APIs and their support in generic code. 998 999An API implementation might have a dependency on platform code e.g. CPU_SUSPEND 1000requires the platform to export a part of the implementation. Hence the level 1001of support of the mandatory APIs depends upon the support exported by the 1002platform port as well. The Juno and FVP (all variants) platforms export all the 1003required support. 1004 1005+-----------------------------+-------------+-------------------------------+ 1006| PSCI v1.1 API | Supported | Comments | 1007+=============================+=============+===============================+ 1008| ``PSCI_VERSION`` | Yes | The version returned is 1.1 | 1009+-----------------------------+-------------+-------------------------------+ 1010| ``CPU_SUSPEND`` | Yes\* | | 1011+-----------------------------+-------------+-------------------------------+ 1012| ``CPU_OFF`` | Yes\* | | 1013+-----------------------------+-------------+-------------------------------+ 1014| ``CPU_ON`` | Yes\* | | 1015+-----------------------------+-------------+-------------------------------+ 1016| ``AFFINITY_INFO`` | Yes | | 1017+-----------------------------+-------------+-------------------------------+ 1018| ``MIGRATE`` | Yes\*\* | | 1019+-----------------------------+-------------+-------------------------------+ 1020| ``MIGRATE_INFO_TYPE`` | Yes\*\* | | 1021+-----------------------------+-------------+-------------------------------+ 1022| ``MIGRATE_INFO_CPU`` | Yes\*\* | | 1023+-----------------------------+-------------+-------------------------------+ 1024| ``SYSTEM_OFF`` | Yes\* | | 1025+-----------------------------+-------------+-------------------------------+ 1026| ``SYSTEM_RESET`` | Yes\* | | 1027+-----------------------------+-------------+-------------------------------+ 1028| ``PSCI_FEATURES`` | Yes | | 1029+-----------------------------+-------------+-------------------------------+ 1030| ``CPU_FREEZE`` | No | | 1031+-----------------------------+-------------+-------------------------------+ 1032| ``CPU_DEFAULT_SUSPEND`` | No | | 1033+-----------------------------+-------------+-------------------------------+ 1034| ``NODE_HW_STATE`` | Yes\* | | 1035+-----------------------------+-------------+-------------------------------+ 1036| ``SYSTEM_SUSPEND`` | Yes\* | | 1037+-----------------------------+-------------+-------------------------------+ 1038| ``PSCI_SET_SUSPEND_MODE`` | No | | 1039+-----------------------------+-------------+-------------------------------+ 1040| ``PSCI_STAT_RESIDENCY`` | Yes\* | | 1041+-----------------------------+-------------+-------------------------------+ 1042| ``PSCI_STAT_COUNT`` | Yes\* | | 1043+-----------------------------+-------------+-------------------------------+ 1044| ``SYSTEM_RESET2`` | Yes\* | | 1045+-----------------------------+-------------+-------------------------------+ 1046| ``MEM_PROTECT`` | Yes\* | | 1047+-----------------------------+-------------+-------------------------------+ 1048| ``MEM_PROTECT_CHECK_RANGE`` | Yes\* | | 1049+-----------------------------+-------------+-------------------------------+ 1050 1051\*Note : These PSCI APIs require platform power management hooks to be 1052registered with the generic PSCI code to be supported. 1053 1054\*\*Note : These PSCI APIs require appropriate Secure Payload Dispatcher 1055hooks to be registered with the generic PSCI code to be supported. 1056 1057The PSCI implementation in TF-A is a library which can be integrated with 1058AArch64 or AArch32 EL3 Runtime Software for Armv8-A systems. A guide to 1059integrating PSCI library with AArch32 EL3 Runtime Software can be found 1060at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`. 1061 1062.. _firmware_design_sel1_spd: 1063 1064Secure-EL1 Payloads and Dispatchers 1065----------------------------------- 1066 1067On a production system that includes a Trusted OS running in Secure-EL1/EL0, 1068the Trusted OS is coupled with a companion runtime service in the BL31 1069firmware. This service is responsible for the initialisation of the Trusted 1070OS and all communications with it. The Trusted OS is the BL32 stage of the 1071boot flow in TF-A. The firmware will attempt to locate, load and execute a 1072BL32 image. 1073 1074TF-A uses a more general term for the BL32 software that runs at Secure-EL1 - 1075the *Secure-EL1 Payload* - as it is not always a Trusted OS. 1076 1077TF-A provides a Test Secure-EL1 Payload (TSP) and a Test Secure-EL1 Payload 1078Dispatcher (TSPD) service as an example of how a Trusted OS is supported on a 1079production system using the Runtime Services Framework. On such a system, the 1080Test BL32 image and service are replaced by the Trusted OS and its dispatcher 1081service. The TF-A build system expects that the dispatcher will define the 1082build flag ``NEED_BL32`` to enable it to include the BL32 in the build either 1083as a binary or to compile from source depending on whether the ``BL32`` build 1084option is specified or not. 1085 1086The TSP runs in Secure-EL1. It is designed to demonstrate synchronous 1087communication with the normal-world software running in EL1/EL2. Communication 1088is initiated by the normal-world software 1089 1090- either directly through a Fast SMC (as defined in the `SMCCC`_) 1091 1092- or indirectly through a `PSCI`_ SMC. The `PSCI`_ implementation in turn 1093 informs the TSPD about the requested power management operation. This allows 1094 the TSP to prepare for or respond to the power state change 1095 1096The TSPD service is responsible for. 1097 1098- Initializing the TSP 1099 1100- Routing requests and responses between the secure and the non-secure 1101 states during the two types of communications just described 1102 1103Initializing a BL32 Image 1104~~~~~~~~~~~~~~~~~~~~~~~~~ 1105 1106The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing 1107the BL32 image. It needs access to the information passed by BL2 to BL31 to do 1108so. This is provided by: 1109 1110.. code:: c 1111 1112 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t); 1113 1114which returns a reference to the ``entry_point_info`` structure corresponding to 1115the image which will be run in the specified security state. The SPD uses this 1116API to get entry point information for the SECURE image, BL32. 1117 1118In the absence of a BL32 image, BL31 passes control to the normal world 1119bootloader image (BL33). When the BL32 image is present, it is typical 1120that the SPD wants control to be passed to BL32 first and then later to BL33. 1121 1122To do this the SPD has to register a BL32 initialization function during 1123initialization of the SPD service. The BL32 initialization function has this 1124prototype: 1125 1126.. code:: c 1127 1128 int32_t init(void); 1129 1130and is registered using the ``bl31_register_bl32_init()`` function. 1131 1132TF-A supports two approaches for the SPD to pass control to BL32 before 1133returning through EL3 and running the non-trusted firmware (BL33): 1134 1135#. In the BL32 setup function, use ``bl31_set_next_image_type()`` to 1136 request that the exit from ``bl31_main()`` is to the BL32 entrypoint in 1137 Secure-EL1. BL31 will exit to BL32 using the asynchronous method by 1138 calling ``bl31_prepare_next_image_entry()`` and ``el3_exit()``. 1139 1140 When the BL32 has completed initialization at Secure-EL1, it returns to 1141 BL31 by issuing an SMC, using a Function ID allocated to the SPD. On 1142 receipt of this SMC, the SPD service handler should switch the CPU context 1143 from trusted to normal world and use the ``bl31_set_next_image_type()`` and 1144 ``bl31_prepare_next_image_entry()`` functions to set up the initial return to 1145 the normal world firmware BL33. On return from the handler the framework 1146 will exit to EL2 and run BL33. 1147 1148#. The BL32 setup function registers an initialization function using 1149 ``bl31_register_bl32_init()`` which provides a SPD-defined mechanism to 1150 invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32 1151 entrypoint. 1152 1153 .. note:: 1154 The Test SPD service included with TF-A provides one implementation 1155 of such a mechanism. 1156 1157 On completion BL32 returns control to BL31 via a SMC, and on receipt the 1158 SPD service handler invokes the synchronous call return mechanism to return 1159 to the BL32 initialization function. On return from this function, 1160 ``bl31_main()`` will set up the return to the normal world firmware BL33 and 1161 continue the boot process in the normal world. 1162 1163Crash Reporting in BL31 1164----------------------- 1165 1166BL31 implements a scheme for reporting the processor state when an unhandled 1167exception is encountered. The reporting mechanism attempts to preserve all the 1168register contents and report it via a dedicated UART (PL011 console). BL31 1169reports the general purpose, EL3, Secure EL1 and some EL2 state registers. 1170 1171A dedicated per-CPU crash stack is maintained by BL31 and this is retrieved via 1172the per-CPU pointer cache. The implementation attempts to minimise the memory 1173required for this feature. The file ``crash_reporting.S`` contains the 1174implementation for crash reporting. 1175 1176The sample crash output is shown below. 1177 1178:: 1179 1180 x0 :0x000000004F00007C 1181 x1 :0x0000000007FFFFFF 1182 x2 :0x0000000004014D50 1183 x3 :0x0000000000000000 1184 x4 :0x0000000088007998 1185 x5 :0x00000000001343AC 1186 x6 :0x0000000000000016 1187 x7 :0x00000000000B8A38 1188 x8 :0x00000000001343AC 1189 x9 :0x00000000000101A8 1190 x10 :0x0000000000000002 1191 x11 :0x000000000000011C 1192 x12 :0x00000000FEFDC644 1193 x13 :0x00000000FED93FFC 1194 x14 :0x0000000000247950 1195 x15 :0x00000000000007A2 1196 x16 :0x00000000000007A4 1197 x17 :0x0000000000247950 1198 x18 :0x0000000000000000 1199 x19 :0x00000000FFFFFFFF 1200 x20 :0x0000000004014D50 1201 x21 :0x000000000400A38C 1202 x22 :0x0000000000247950 1203 x23 :0x0000000000000010 1204 x24 :0x0000000000000024 1205 x25 :0x00000000FEFDC868 1206 x26 :0x00000000FEFDC86A 1207 x27 :0x00000000019EDEDC 1208 x28 :0x000000000A7CFDAA 1209 x29 :0x0000000004010780 1210 x30 :0x000000000400F004 1211 scr_el3 :0x0000000000000D3D 1212 sctlr_el3 :0x0000000000C8181F 1213 cptr_el3 :0x0000000000000000 1214 tcr_el3 :0x0000000080803520 1215 daif :0x00000000000003C0 1216 mair_el3 :0x00000000000004FF 1217 spsr_el3 :0x00000000800003CC 1218 elr_el3 :0x000000000400C0CC 1219 ttbr0_el3 :0x00000000040172A0 1220 esr_el3 :0x0000000096000210 1221 sp_el3 :0x0000000004014D50 1222 far_el3 :0x000000004F00007C 1223 spsr_el1 :0x0000000000000000 1224 elr_el1 :0x0000000000000000 1225 spsr_abt :0x0000000000000000 1226 spsr_und :0x0000000000000000 1227 spsr_irq :0x0000000000000000 1228 spsr_fiq :0x0000000000000000 1229 sctlr_el1 :0x0000000030C81807 1230 actlr_el1 :0x0000000000000000 1231 cpacr_el1 :0x0000000000300000 1232 csselr_el1 :0x0000000000000002 1233 sp_el1 :0x0000000004028800 1234 esr_el1 :0x0000000000000000 1235 ttbr0_el1 :0x000000000402C200 1236 ttbr1_el1 :0x0000000000000000 1237 mair_el1 :0x00000000000004FF 1238 amair_el1 :0x0000000000000000 1239 tcr_el1 :0x0000000000003520 1240 tpidr_el1 :0x0000000000000000 1241 tpidr_el0 :0x0000000000000000 1242 tpidrro_el0 :0x0000000000000000 1243 dacr32_el2 :0x0000000000000000 1244 ifsr32_el2 :0x0000000000000000 1245 par_el1 :0x0000000000000000 1246 far_el1 :0x0000000000000000 1247 afsr0_el1 :0x0000000000000000 1248 afsr1_el1 :0x0000000000000000 1249 contextidr_el1 :0x0000000000000000 1250 vbar_el1 :0x0000000004027000 1251 cntp_ctl_el0 :0x0000000000000000 1252 cntp_cval_el0 :0x0000000000000000 1253 cntv_ctl_el0 :0x0000000000000000 1254 cntv_cval_el0 :0x0000000000000000 1255 cntkctl_el1 :0x0000000000000000 1256 sp_el0 :0x0000000004010780 1257 1258Guidelines for Reset Handlers 1259----------------------------- 1260 1261TF-A implements a framework that allows CPU and platform ports to perform 1262actions very early after a CPU is released from reset in both the cold and warm 1263boot paths. This is done by calling the ``reset_handler()`` function in both 1264the BL1 and BL31 images. It in turn calls the platform and CPU specific reset 1265handling functions. 1266 1267Details for implementing a CPU specific reset handler can be found in 1268Section 8. Details for implementing a platform specific reset handler can be 1269found in the :ref:`Porting Guide` (see the ``plat_reset_handler()`` function). 1270 1271When adding functionality to a reset handler, keep in mind that if a different 1272reset handling behavior is required between the first and the subsequent 1273invocations of the reset handling code, this should be detected at runtime. 1274In other words, the reset handler should be able to detect whether an action has 1275already been performed and act as appropriate. Possible courses of actions are, 1276e.g. skip the action the second time, or undo/redo it. 1277 1278Configuring secure interrupts 1279----------------------------- 1280 1281The GIC driver is responsible for performing initial configuration of secure 1282interrupts on the platform. To this end, the platform is expected to provide the 1283GIC driver (either GICv2 or GICv3, as selected by the platform) with the 1284interrupt configuration during the driver initialisation. 1285 1286Secure interrupt configuration are specified in an array of secure interrupt 1287properties. In this scheme, in both GICv2 and GICv3 driver data structures, the 1288``interrupt_props`` member points to an array of interrupt properties. Each 1289element of the array specifies the interrupt number and its attributes 1290(priority, group, configuration). Each element of the array shall be populated 1291by the macro ``INTR_PROP_DESC()``. The macro takes the following arguments: 1292 1293- 10-bit interrupt number, 1294 1295- 8-bit interrupt priority, 1296 1297- Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``, 1298 ``INTR_TYPE_NS``), 1299 1300- Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or 1301 ``GIC_INTR_CFG_EDGE``). 1302 1303.. _firmware_design_cpu_ops_fwk: 1304 1305CPU specific operations framework 1306--------------------------------- 1307 1308Certain aspects of the Armv8-A architecture are implementation defined, 1309that is, certain behaviours are not architecturally defined, but must be 1310defined and documented by individual processor implementations. TF-A 1311implements a framework which categorises the common implementation defined 1312behaviours and allows a processor to export its implementation of that 1313behaviour. The categories are: 1314 1315#. Processor specific reset sequence. 1316 1317#. Processor specific power down sequences. 1318 1319#. Processor specific register dumping as a part of crash reporting. 1320 1321#. Errata status reporting. 1322 1323Each of the above categories fulfils a different requirement. 1324 1325#. allows any processor specific initialization before the caches and MMU 1326 are turned on, like implementation of errata workarounds, entry into 1327 the intra-cluster coherency domain etc. 1328 1329#. allows each processor to implement the power down sequence mandated in 1330 its Technical Reference Manual (TRM). 1331 1332#. allows a processor to provide additional information to the developer 1333 in the event of a crash, for example Cortex-A53 has registers which 1334 can expose the data cache contents. 1335 1336#. allows a processor to define a function that inspects and reports the status 1337 of all errata workarounds on that processor. 1338 1339Please note that only 2. is mandated by the TRM. 1340 1341The CPU specific operations framework scales to accommodate a large number of 1342different CPUs during power down and reset handling. The platform can specify 1343any CPU optimization it wants to enable for each CPU. It can also specify 1344the CPU errata workarounds to be applied for each CPU type during reset 1345handling by defining CPU errata compile time macros. Details on these macros 1346can be found in the :ref:`Arm CPU Specific Build Macros` document. 1347 1348The CPU specific operations framework depends on the ``cpu_ops`` structure which 1349needs to be exported for each type of CPU in the platform. It is defined in 1350``include/lib/cpus/aarch64/cpu_macros.S`` and has the following fields : ``midr``, 1351``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and 1352``cpu_reg_dump()``. 1353 1354The CPU specific files in ``lib/cpus`` export a ``cpu_ops`` data structure with 1355suitable handlers for that CPU. For example, ``lib/cpus/aarch64/cortex_a53.S`` 1356exports the ``cpu_ops`` for Cortex-A53 CPU. According to the platform 1357configuration, these CPU specific files must be included in the build by 1358the platform makefile. The generic CPU specific operations framework code exists 1359in ``lib/cpus/aarch64/cpu_helpers.S``. 1360 1361CPU specific Reset Handling 1362~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1363 1364After a reset, the state of the CPU when it calls generic reset handler is: 1365MMU turned off, both instruction and data caches turned off and not part 1366of any coherency domain. 1367 1368The BL entrypoint code first invokes the ``plat_reset_handler()`` to allow 1369the platform to perform any system initialization required and any system 1370errata workarounds that needs to be applied. The ``get_cpu_ops_ptr()`` reads 1371the current CPU midr, finds the matching ``cpu_ops`` entry in the ``cpu_ops`` 1372array and returns it. Note that only the part number and implementer fields 1373in midr are used to find the matching ``cpu_ops`` entry. The ``reset_func()`` in 1374the returned ``cpu_ops`` is then invoked which executes the required reset 1375handling for that CPU and also any errata workarounds enabled by the platform. 1376This function must preserve the values of general purpose registers x20 to x29. 1377 1378Refer to Section "Guidelines for Reset Handlers" for general guidelines 1379regarding placement of code in a reset handler. 1380 1381CPU specific power down sequence 1382~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1383 1384During the BL31 initialization sequence, the pointer to the matching ``cpu_ops`` 1385entry is stored in per-CPU data by ``init_cpu_ops()`` so that it can be quickly 1386retrieved during power down sequences. 1387 1388Various CPU drivers register handlers to perform power down at certain power 1389levels for that specific CPU. The PSCI service, upon receiving a power down 1390request, determines the highest power level at which to execute power down 1391sequence for a particular CPU. It uses the ``prepare_cpu_pwr_dwn()`` function to 1392pick the right power down handler for the requested level. The function 1393retrieves ``cpu_ops`` pointer member of per-CPU data, and from that, further 1394retrieves ``cpu_pwr_down_ops`` array, and indexes into the required level. If the 1395requested power level is higher than what a CPU driver supports, the handler 1396registered for highest level is invoked. 1397 1398At runtime the platform hooks for power down are invoked by the PSCI service to 1399perform platform specific operations during a power down sequence, for example 1400turning off CCI coherency during a cluster power down. 1401 1402CPU specific register reporting during crash 1403~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1404 1405If the crash reporting is enabled in BL31, when a crash occurs, the crash 1406reporting framework calls ``do_cpu_reg_dump`` which retrieves the matching 1407``cpu_ops`` using ``get_cpu_ops_ptr()`` function. The ``cpu_reg_dump()`` in 1408``cpu_ops`` is invoked, which then returns the CPU specific register values to 1409be reported and a pointer to the ASCII list of register names in a format 1410expected by the crash reporting framework. 1411 1412.. _firmware_design_cpu_errata_reporting: 1413 1414CPU errata status reporting 1415~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1416 1417Errata workarounds for CPUs supported in TF-A are applied during both cold and 1418warm boots, shortly after reset. Individual Errata workarounds are enabled as 1419build options. Some errata workarounds have potential run-time implications; 1420therefore some are enabled by default, others not. Platform ports shall 1421override build options to enable or disable errata as appropriate. The CPU 1422drivers take care of applying errata workarounds that are enabled and applicable 1423to a given CPU. Refer to :ref:`arm_cpu_macros_errata_workarounds` for more 1424information. 1425 1426Functions in CPU drivers that apply errata workaround must follow the 1427conventions listed below. 1428 1429The errata workaround must be authored as two separate functions: 1430 1431- One that checks for errata. This function must determine whether that errata 1432 applies to the current CPU. Typically this involves matching the current 1433 CPUs revision and variant against a value that's known to be affected by the 1434 errata. If the function determines that the errata applies to this CPU, it 1435 must return ``ERRATA_APPLIES``; otherwise, it must return 1436 ``ERRATA_NOT_APPLIES``. The utility functions ``cpu_get_rev_var`` and 1437 ``cpu_rev_var_ls`` functions may come in handy for this purpose. 1438 1439For an errata identified as ``E``, the check function must be named 1440``check_errata_E``. 1441 1442This function will be invoked at different times, both from assembly and from 1443C run time. Therefore it must follow AAPCS, and must not use stack. 1444 1445- Another one that applies the errata workaround. This function would call the 1446 check function described above, and applies errata workaround if required. 1447 1448CPU drivers that apply errata workaround can optionally implement an assembly 1449function that report the status of errata workarounds pertaining to that CPU. 1450For a driver that registers the CPU, for example, ``cpux`` via ``declare_cpu_ops`` 1451macro, the errata reporting function, if it exists, must be named 1452``cpux_errata_report``. This function will always be called with MMU enabled; it 1453must follow AAPCS and may use stack. 1454 1455In a debug build of TF-A, on a CPU that comes out of reset, both BL1 and the 1456runtime firmware (BL31 in AArch64, and BL32 in AArch32) will invoke errata 1457status reporting function, if one exists, for that type of CPU. 1458 1459To report the status of each errata workaround, the function shall use the 1460assembler macro ``report_errata``, passing it: 1461 1462- The build option that enables the errata; 1463 1464- The name of the CPU: this must be the same identifier that CPU driver 1465 registered itself with, using ``declare_cpu_ops``; 1466 1467- And the errata identifier: the identifier must match what's used in the 1468 errata's check function described above. 1469 1470The errata status reporting function will be called once per CPU type/errata 1471combination during the software's active life time. 1472 1473It's expected that whenever an errata workaround is submitted to TF-A, the 1474errata reporting function is appropriately extended to report its status as 1475well. 1476 1477Reporting the status of errata workaround is for informational purpose only; it 1478has no functional significance. 1479 1480Memory layout of BL images 1481-------------------------- 1482 1483Each bootloader image can be divided in 2 parts: 1484 1485- the static contents of the image. These are data actually stored in the 1486 binary on the disk. In the ELF terminology, they are called ``PROGBITS`` 1487 sections; 1488 1489- the run-time contents of the image. These are data that don't occupy any 1490 space in the binary on the disk. The ELF binary just contains some 1491 metadata indicating where these data will be stored at run-time and the 1492 corresponding sections need to be allocated and initialized at run-time. 1493 In the ELF terminology, they are called ``NOBITS`` sections. 1494 1495All PROGBITS sections are grouped together at the beginning of the image, 1496followed by all NOBITS sections. This is true for all TF-A images and it is 1497governed by the linker scripts. This ensures that the raw binary images are 1498as small as possible. If a NOBITS section was inserted in between PROGBITS 1499sections then the resulting binary file would contain zero bytes in place of 1500this NOBITS section, making the image unnecessarily bigger. Smaller images 1501allow faster loading from the FIP to the main memory. 1502 1503Linker scripts and symbols 1504~~~~~~~~~~~~~~~~~~~~~~~~~~ 1505 1506Each bootloader stage image layout is described by its own linker script. The 1507linker scripts export some symbols into the program symbol table. Their values 1508correspond to particular addresses. TF-A code can refer to these symbols to 1509figure out the image memory layout. 1510 1511Linker symbols follow the following naming convention in TF-A. 1512 1513- ``__<SECTION>_START__`` 1514 1515 Start address of a given section named ``<SECTION>``. 1516 1517- ``__<SECTION>_END__`` 1518 1519 End address of a given section named ``<SECTION>``. If there is an alignment 1520 constraint on the section's end address then ``__<SECTION>_END__`` corresponds 1521 to the end address of the section's actual contents, rounded up to the right 1522 boundary. Refer to the value of ``__<SECTION>_UNALIGNED_END__`` to know the 1523 actual end address of the section's contents. 1524 1525- ``__<SECTION>_UNALIGNED_END__`` 1526 1527 End address of a given section named ``<SECTION>`` without any padding or 1528 rounding up due to some alignment constraint. 1529 1530- ``__<SECTION>_SIZE__`` 1531 1532 Size (in bytes) of a given section named ``<SECTION>``. If there is an 1533 alignment constraint on the section's end address then ``__<SECTION>_SIZE__`` 1534 corresponds to the size of the section's actual contents, rounded up to the 1535 right boundary. In other words, ``__<SECTION>_SIZE__ = __<SECTION>_END__ - _<SECTION>_START__``. Refer to the value of ``__<SECTION>_UNALIGNED_SIZE__`` 1536 to know the actual size of the section's contents. 1537 1538- ``__<SECTION>_UNALIGNED_SIZE__`` 1539 1540 Size (in bytes) of a given section named ``<SECTION>`` without any padding or 1541 rounding up due to some alignment constraint. In other words, 1542 ``__<SECTION>_UNALIGNED_SIZE__ = __<SECTION>_UNALIGNED_END__ - __<SECTION>_START__``. 1543 1544Some of the linker symbols are mandatory as TF-A code relies on them to be 1545defined. They are listed in the following subsections. Some of them must be 1546provided for each bootloader stage and some are specific to a given bootloader 1547stage. 1548 1549The linker scripts define some extra, optional symbols. They are not actually 1550used by any code but they help in understanding the bootloader images' memory 1551layout as they are easy to spot in the link map files. 1552 1553Common linker symbols 1554^^^^^^^^^^^^^^^^^^^^^ 1555 1556All BL images share the following requirements: 1557 1558- The BSS section must be zero-initialised before executing any C code. 1559- The coherent memory section (if enabled) must be zero-initialised as well. 1560- The MMU setup code needs to know the extents of the coherent and read-only 1561 memory regions to set the right memory attributes. When 1562 ``SEPARATE_CODE_AND_RODATA=1``, it needs to know more specifically how the 1563 read-only memory region is divided between code and data. 1564 1565The following linker symbols are defined for this purpose: 1566 1567- ``__BSS_START__`` 1568- ``__BSS_SIZE__`` 1569- ``__COHERENT_RAM_START__`` Must be aligned on a page-size boundary. 1570- ``__COHERENT_RAM_END__`` Must be aligned on a page-size boundary. 1571- ``__COHERENT_RAM_UNALIGNED_SIZE__`` 1572- ``__RO_START__`` 1573- ``__RO_END__`` 1574- ``__TEXT_START__`` 1575- ``__TEXT_END__`` 1576- ``__RODATA_START__`` 1577- ``__RODATA_END__`` 1578 1579BL1's linker symbols 1580^^^^^^^^^^^^^^^^^^^^ 1581 1582BL1 being the ROM image, it has additional requirements. BL1 resides in ROM and 1583it is entirely executed in place but it needs some read-write memory for its 1584mutable data. Its ``.data`` section (i.e. its allocated read-write data) must be 1585relocated from ROM to RAM before executing any C code. 1586 1587The following additional linker symbols are defined for BL1: 1588 1589- ``__BL1_ROM_END__`` End address of BL1's ROM contents, covering its code 1590 and ``.data`` section in ROM. 1591- ``__DATA_ROM_START__`` Start address of the ``.data`` section in ROM. Must be 1592 aligned on a 16-byte boundary. 1593- ``__DATA_RAM_START__`` Address in RAM where the ``.data`` section should be 1594 copied over. Must be aligned on a 16-byte boundary. 1595- ``__DATA_SIZE__`` Size of the ``.data`` section (in ROM or RAM). 1596- ``__BL1_RAM_START__`` Start address of BL1 read-write data. 1597- ``__BL1_RAM_END__`` End address of BL1 read-write data. 1598 1599How to choose the right base addresses for each bootloader stage image 1600~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1601 1602There is currently no support for dynamic image loading in TF-A. This means 1603that all bootloader images need to be linked against their ultimate runtime 1604locations and the base addresses of each image must be chosen carefully such 1605that images don't overlap each other in an undesired way. As the code grows, 1606the base addresses might need adjustments to cope with the new memory layout. 1607 1608The memory layout is completely specific to the platform and so there is no 1609general recipe for choosing the right base addresses for each bootloader image. 1610However, there are tools to aid in understanding the memory layout. These are 1611the link map files: ``build/<platform>/<build-type>/bl<x>/bl<x>.map``, with ``<x>`` 1612being the stage bootloader. They provide a detailed view of the memory usage of 1613each image. Among other useful information, they provide the end address of 1614each image. 1615 1616- ``bl1.map`` link map file provides ``__BL1_RAM_END__`` address. 1617- ``bl2.map`` link map file provides ``__BL2_END__`` address. 1618- ``bl31.map`` link map file provides ``__BL31_END__`` address. 1619- ``bl32.map`` link map file provides ``__BL32_END__`` address. 1620 1621For each bootloader image, the platform code must provide its start address 1622as well as a limit address that it must not overstep. The latter is used in the 1623linker scripts to check that the image doesn't grow past that address. If that 1624happens, the linker will issue a message similar to the following: 1625 1626:: 1627 1628 aarch64-none-elf-ld: BLx has exceeded its limit. 1629 1630Additionally, if the platform memory layout implies some image overlaying like 1631on FVP, BL31 and TSP need to know the limit address that their PROGBITS 1632sections must not overstep. The platform code must provide those. 1633 1634TF-A does not provide any mechanism to verify at boot time that the memory 1635to load a new image is free to prevent overwriting a previously loaded image. 1636The platform must specify the memory available in the system for all the 1637relevant BL images to be loaded. 1638 1639For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will 1640return the region defined by the platform where BL1 intends to load BL2. The 1641``load_image()`` function performs bounds check for the image size based on the 1642base and maximum image size provided by the platforms. Platforms must take 1643this behaviour into account when defining the base/size for each of the images. 1644 1645Memory layout on Arm development platforms 1646^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1647 1648The following list describes the memory layout on the Arm development platforms: 1649 1650- A 4KB page of shared memory is used for communication between Trusted 1651 Firmware and the platform's power controller. This is located at the base of 1652 Trusted SRAM. The amount of Trusted SRAM available to load the bootloader 1653 images is reduced by the size of the shared memory. 1654 1655 The shared memory is used to store the CPUs' entrypoint mailbox. On Juno, 1656 this is also used for the MHU payload when passing messages to and from the 1657 SCP. 1658 1659- Another 4 KB page is reserved for passing memory layout between BL1 and BL2 1660 and also the dynamic firmware configurations. 1661 1662- On FVP, BL1 is originally sitting in the Trusted ROM at address ``0x0``. On 1663 Juno, BL1 resides in flash memory at address ``0x0BEC0000``. BL1 read-write 1664 data are relocated to the top of Trusted SRAM at runtime. 1665 1666- BL2 is loaded below BL1 RW 1667 1668- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP_MIN), 1669 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will 1670 overwrite BL1 R/W data and BL2. This implies that BL1 global variables 1671 remain valid only until execution reaches the EL3 Runtime Software entry 1672 point during a cold boot. 1673 1674- On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory 1675 region and transferred to the SCP before being overwritten by EL3 Runtime 1676 Software. 1677 1678- BL32 (for AArch64) can be loaded in one of the following locations: 1679 1680 - Trusted SRAM 1681 - Trusted DRAM (FVP only) 1682 - Secure region of DRAM (top 16MB of DRAM configured by the TrustZone 1683 controller) 1684 1685 When BL32 (for AArch64) is loaded into Trusted SRAM, it is loaded below 1686 BL31. 1687 1688The location of the BL32 image will result in different memory maps. This is 1689illustrated for both FVP and Juno in the following diagrams, using the TSP as 1690an example. 1691 1692.. note:: 1693 Loading the BL32 image in TZC secured DRAM doesn't change the memory 1694 layout of the other images in Trusted SRAM. 1695 1696CONFIG section in memory layouts shown below contains: 1697 1698:: 1699 1700 +--------------------+ 1701 |bl2_mem_params_descs| 1702 |--------------------| 1703 | fw_configs | 1704 +--------------------+ 1705 1706``bl2_mem_params_descs`` contains parameters passed from BL2 to next the 1707BL image during boot. 1708 1709``fw_configs`` includes soc_fw_config, tos_fw_config and tb_fw_config. 1710 1711**FVP with TSP in Trusted SRAM with firmware configs :** 1712(These diagrams only cover the AArch64 case) 1713 1714:: 1715 1716 DRAM 1717 0xffffffff +----------+ 1718 : : 1719 |----------| 1720 |HW_CONFIG | 1721 0x83000000 |----------| (non-secure) 1722 | | 1723 0x80000000 +----------+ 1724 1725 Trusted SRAM 1726 0x04040000 +----------+ loaded by BL2 +----------------+ 1727 | BL1 (rw) | <<<<<<<<<<<<< | | 1728 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1729 | BL2 | <<<<<<<<<<<<< | | 1730 |----------| <<<<<<<<<<<<< |----------------| 1731 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1732 | | <<<<<<<<<<<<< |----------------| 1733 | | <<<<<<<<<<<<< | BL32 | 1734 0x04002000 +----------+ +----------------+ 1735 | CONFIG | 1736 0x04001000 +----------+ 1737 | Shared | 1738 0x04000000 +----------+ 1739 1740 Trusted ROM 1741 0x04000000 +----------+ 1742 | BL1 (ro) | 1743 0x00000000 +----------+ 1744 1745**FVP with TSP in Trusted DRAM with firmware configs (default option):** 1746 1747:: 1748 1749 DRAM 1750 0xffffffff +--------------+ 1751 : : 1752 |--------------| 1753 | HW_CONFIG | 1754 0x83000000 |--------------| (non-secure) 1755 | | 1756 0x80000000 +--------------+ 1757 1758 Trusted DRAM 1759 0x08000000 +--------------+ 1760 | BL32 | 1761 0x06000000 +--------------+ 1762 1763 Trusted SRAM 1764 0x04040000 +--------------+ loaded by BL2 +----------------+ 1765 | BL1 (rw) | <<<<<<<<<<<<< | | 1766 |--------------| <<<<<<<<<<<<< | BL31 NOBITS | 1767 | BL2 | <<<<<<<<<<<<< | | 1768 |--------------| <<<<<<<<<<<<< |----------------| 1769 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1770 | | +----------------+ 1771 +--------------+ 1772 | CONFIG | 1773 0x04001000 +--------------+ 1774 | Shared | 1775 0x04000000 +--------------+ 1776 1777 Trusted ROM 1778 0x04000000 +--------------+ 1779 | BL1 (ro) | 1780 0x00000000 +--------------+ 1781 1782**FVP with TSP in TZC-Secured DRAM with firmware configs :** 1783 1784:: 1785 1786 DRAM 1787 0xffffffff +----------+ 1788 | BL32 | (secure) 1789 0xff000000 +----------+ 1790 | | 1791 |----------| 1792 |HW_CONFIG | 1793 0x83000000 |----------| (non-secure) 1794 | | 1795 0x80000000 +----------+ 1796 1797 Trusted SRAM 1798 0x04040000 +----------+ loaded by BL2 +----------------+ 1799 | BL1 (rw) | <<<<<<<<<<<<< | | 1800 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1801 | BL2 | <<<<<<<<<<<<< | | 1802 |----------| <<<<<<<<<<<<< |----------------| 1803 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1804 | | +----------------+ 1805 0x04002000 +----------+ 1806 | CONFIG | 1807 0x04001000 +----------+ 1808 | Shared | 1809 0x04000000 +----------+ 1810 1811 Trusted ROM 1812 0x04000000 +----------+ 1813 | BL1 (ro) | 1814 0x00000000 +----------+ 1815 1816**Juno with BL32 in Trusted SRAM :** 1817 1818:: 1819 1820 Flash0 1821 0x0C000000 +----------+ 1822 : : 1823 0x0BED0000 |----------| 1824 | BL1 (ro) | 1825 0x0BEC0000 |----------| 1826 : : 1827 0x08000000 +----------+ BL31 is loaded 1828 after SCP_BL2 has 1829 Trusted SRAM been sent to SCP 1830 0x04040000 +----------+ loaded by BL2 +----------------+ 1831 | BL1 (rw) | <<<<<<<<<<<<< | | 1832 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1833 | BL2 | <<<<<<<<<<<<< | | 1834 |----------| <<<<<<<<<<<<< |----------------| 1835 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 1836 |----------| <<<<<<<<<<<<< |----------------| 1837 | | <<<<<<<<<<<<< | BL32 | 1838 | | +----------------+ 1839 | | 1840 0x04001000 +----------+ 1841 | MHU | 1842 0x04000000 +----------+ 1843 1844**Juno with BL32 in TZC-secured DRAM :** 1845 1846:: 1847 1848 DRAM 1849 0xFFE00000 +----------+ 1850 | BL32 | (secure) 1851 0xFF000000 |----------| 1852 | | 1853 : : (non-secure) 1854 | | 1855 0x80000000 +----------+ 1856 1857 Flash0 1858 0x0C000000 +----------+ 1859 : : 1860 0x0BED0000 |----------| 1861 | BL1 (ro) | 1862 0x0BEC0000 |----------| 1863 : : 1864 0x08000000 +----------+ BL31 is loaded 1865 after SCP_BL2 has 1866 Trusted SRAM been sent to SCP 1867 0x04040000 +----------+ loaded by BL2 +----------------+ 1868 | BL1 (rw) | <<<<<<<<<<<<< | | 1869 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1870 | BL2 | <<<<<<<<<<<<< | | 1871 |----------| <<<<<<<<<<<<< |----------------| 1872 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 1873 |----------| +----------------+ 1874 0x04001000 +----------+ 1875 | MHU | 1876 0x04000000 +----------+ 1877 1878.. _firmware_design_fip: 1879 1880Firmware Image Package (FIP) 1881---------------------------- 1882 1883Using a Firmware Image Package (FIP) allows for packing bootloader images (and 1884potentially other payloads) into a single archive that can be loaded by TF-A 1885from non-volatile platform storage. A driver to load images from a FIP has 1886been added to the storage layer and allows a package to be read from supported 1887platform storage. A tool to create Firmware Image Packages is also provided 1888and described below. 1889 1890Firmware Image Package layout 1891~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1892 1893The FIP layout consists of a table of contents (ToC) followed by payload data. 1894The ToC itself has a header followed by one or more table entries. The ToC is 1895terminated by an end marker entry, and since the size of the ToC is 0 bytes, 1896the offset equals the total size of the FIP file. All ToC entries describe some 1897payload data that has been appended to the end of the binary package. With the 1898information provided in the ToC entry the corresponding payload data can be 1899retrieved. 1900 1901:: 1902 1903 ------------------ 1904 | ToC Header | 1905 |----------------| 1906 | ToC Entry 0 | 1907 |----------------| 1908 | ToC Entry 1 | 1909 |----------------| 1910 | ToC End Marker | 1911 |----------------| 1912 | | 1913 | Data 0 | 1914 | | 1915 |----------------| 1916 | | 1917 | Data 1 | 1918 | | 1919 ------------------ 1920 1921The ToC header and entry formats are described in the header file 1922``include/tools_share/firmware_image_package.h``. This file is used by both the 1923tool and TF-A. 1924 1925The ToC header has the following fields: 1926 1927:: 1928 1929 `name`: The name of the ToC. This is currently used to validate the header. 1930 `serial_number`: A non-zero number provided by the creation tool 1931 `flags`: Flags associated with this data. 1932 Bits 0-31: Reserved 1933 Bits 32-47: Platform defined 1934 Bits 48-63: Reserved 1935 1936A ToC entry has the following fields: 1937 1938:: 1939 1940 `uuid`: All files are referred to by a pre-defined Universally Unique 1941 IDentifier [UUID] . The UUIDs are defined in 1942 `include/tools_share/firmware_image_package.h`. The platform translates 1943 the requested image name into the corresponding UUID when accessing the 1944 package. 1945 `offset_address`: The offset address at which the corresponding payload data 1946 can be found. The offset is calculated from the ToC base address. 1947 `size`: The size of the corresponding payload data in bytes. 1948 `flags`: Flags associated with this entry. None are yet defined. 1949 1950Firmware Image Package creation tool 1951~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1952 1953The FIP creation tool can be used to pack specified images into a binary 1954package that can be loaded by TF-A from platform storage. The tool currently 1955only supports packing bootloader images. Additional image definitions can be 1956added to the tool as required. 1957 1958The tool can be found in ``tools/fiptool``. 1959 1960Loading from a Firmware Image Package (FIP) 1961~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1962 1963The Firmware Image Package (FIP) driver can load images from a binary package on 1964non-volatile platform storage. For the Arm development platforms, this is 1965currently NOR FLASH. 1966 1967Bootloader images are loaded according to the platform policy as specified by 1968the function ``plat_get_image_source()``. For the Arm development platforms, this 1969means the platform will attempt to load images from a Firmware Image Package 1970located at the start of NOR FLASH0. 1971 1972The Arm development platforms' policy is to only allow loading of a known set of 1973images. The platform policy can be modified to allow additional images. 1974 1975Use of coherent memory in TF-A 1976------------------------------ 1977 1978There might be loss of coherency when physical memory with mismatched 1979shareability, cacheability and memory attributes is accessed by multiple CPUs 1980(refer to section B2.9 of `Arm ARM`_ for more details). This possibility occurs 1981in TF-A during power up/down sequences when coherency, MMU and caches are 1982turned on/off incrementally. 1983 1984TF-A defines coherent memory as a region of memory with Device nGnRE attributes 1985in the translation tables. The translation granule size in TF-A is 4KB. This 1986is the smallest possible size of the coherent memory region. 1987 1988By default, all data structures which are susceptible to accesses with 1989mismatched attributes from various CPUs are allocated in a coherent memory 1990region (refer to section 2.1 of :ref:`Porting Guide`). The coherent memory 1991region accesses are Outer Shareable, non-cacheable and they can be accessed with 1992the Device nGnRE attributes when the MMU is turned on. Hence, at the expense of 1993at least an extra page of memory, TF-A is able to work around coherency issues 1994due to mismatched memory attributes. 1995 1996The alternative to the above approach is to allocate the susceptible data 1997structures in Normal WriteBack WriteAllocate Inner shareable memory. This 1998approach requires the data structures to be designed so that it is possible to 1999work around the issue of mismatched memory attributes by performing software 2000cache maintenance on them. 2001 2002Disabling the use of coherent memory in TF-A 2003~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2004 2005It might be desirable to avoid the cost of allocating coherent memory on 2006platforms which are memory constrained. TF-A enables inclusion of coherent 2007memory in firmware images through the build flag ``USE_COHERENT_MEM``. 2008This flag is enabled by default. It can be disabled to choose the second 2009approach described above. 2010 2011The below sections analyze the data structures allocated in the coherent memory 2012region and the changes required to allocate them in normal memory. 2013 2014Coherent memory usage in PSCI implementation 2015~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2016 2017The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain 2018tree information for state management of power domains. By default, this data 2019structure is allocated in the coherent memory region in TF-A because it can be 2020accessed by multiple CPUs, either with caches enabled or disabled. 2021 2022.. code:: c 2023 2024 typedef struct non_cpu_pwr_domain_node { 2025 /* 2026 * Index of the first CPU power domain node level 0 which has this node 2027 * as its parent. 2028 */ 2029 unsigned int cpu_start_idx; 2030 2031 /* 2032 * Number of CPU power domains which are siblings of the domain indexed 2033 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx 2034 * -> cpu_start_idx + ncpus' have this node as their parent. 2035 */ 2036 unsigned int ncpus; 2037 2038 /* 2039 * Index of the parent power domain node. 2040 */ 2041 unsigned int parent_node; 2042 2043 plat_local_state_t local_state; 2044 2045 unsigned char level; 2046 2047 /* For indexing the psci_lock array*/ 2048 unsigned char lock_index; 2049 } non_cpu_pd_node_t; 2050 2051In order to move this data structure to normal memory, the use of each of its 2052fields must be analyzed. Fields like ``cpu_start_idx``, ``ncpus``, ``parent_node`` 2053``level`` and ``lock_index`` are only written once during cold boot. Hence removing 2054them from coherent memory involves only doing a clean and invalidate of the 2055cache lines after these fields are written. 2056 2057The field ``local_state`` can be concurrently accessed by multiple CPUs in 2058different cache states. A Lamport's Bakery lock ``psci_locks`` is used to ensure 2059mutual exclusion to this field and a clean and invalidate is needed after it 2060is written. 2061 2062Bakery lock data 2063~~~~~~~~~~~~~~~~ 2064 2065The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory 2066and is accessed by multiple CPUs with mismatched attributes. ``bakery_lock_t`` is 2067defined as follows: 2068 2069.. code:: c 2070 2071 typedef struct bakery_lock { 2072 /* 2073 * The lock_data is a bit-field of 2 members: 2074 * Bit[0] : choosing. This field is set when the CPU is 2075 * choosing its bakery number. 2076 * Bits[1 - 15] : number. This is the bakery number allocated. 2077 */ 2078 volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS]; 2079 } bakery_lock_t; 2080 2081It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU 2082fields can be read by all CPUs but only written to by the owning CPU. 2083 2084Depending upon the data cache line size, the per-CPU fields of the 2085``bakery_lock_t`` structure for multiple CPUs may exist on a single cache line. 2086These per-CPU fields can be read and written during lock contention by multiple 2087CPUs with mismatched memory attributes. Since these fields are a part of the 2088lock implementation, they do not have access to any other locking primitive to 2089safeguard against the resulting coherency issues. As a result, simple software 2090cache maintenance is not enough to allocate them in coherent memory. Consider 2091the following example. 2092 2093CPU0 updates its per-CPU field with data cache enabled. This write updates a 2094local cache line which contains a copy of the fields for other CPUs as well. Now 2095CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache 2096disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of 2097its field in any other cache line in the system. This operation will invalidate 2098the update made by CPU0 as well. 2099 2100To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure 2101has been redesigned. The changes utilise the characteristic of Lamport's Bakery 2102algorithm mentioned earlier. The bakery_lock structure only allocates the memory 2103for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks 2104needed for a CPU into a section ``bakery_lock``. The linker allocates the memory 2105for other cores by using the total size allocated for the bakery_lock section 2106and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to 2107perform software cache maintenance on the lock data structure without running 2108into coherency issues associated with mismatched attributes. 2109 2110The bakery lock data structure ``bakery_info_t`` is defined for use when 2111``USE_COHERENT_MEM`` is disabled as follows: 2112 2113.. code:: c 2114 2115 typedef struct bakery_info { 2116 /* 2117 * The lock_data is a bit-field of 2 members: 2118 * Bit[0] : choosing. This field is set when the CPU is 2119 * choosing its bakery number. 2120 * Bits[1 - 15] : number. This is the bakery number allocated. 2121 */ 2122 volatile uint16_t lock_data; 2123 } bakery_info_t; 2124 2125The ``bakery_info_t`` represents a single per-CPU field of one lock and 2126the combination of corresponding ``bakery_info_t`` structures for all CPUs in the 2127system represents the complete bakery lock. The view in memory for a system 2128with n bakery locks are: 2129 2130:: 2131 2132 bakery_lock section start 2133 |----------------| 2134 | `bakery_info_t`| <-- Lock_0 per-CPU field 2135 | Lock_0 | for CPU0 2136 |----------------| 2137 | `bakery_info_t`| <-- Lock_1 per-CPU field 2138 | Lock_1 | for CPU0 2139 |----------------| 2140 | .... | 2141 |----------------| 2142 | `bakery_info_t`| <-- Lock_N per-CPU field 2143 | Lock_N | for CPU0 2144 ------------------ 2145 | XXXXX | 2146 | Padding to | 2147 | next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate 2148 | Granule | continuous memory for remaining CPUs. 2149 ------------------ 2150 | `bakery_info_t`| <-- Lock_0 per-CPU field 2151 | Lock_0 | for CPU1 2152 |----------------| 2153 | `bakery_info_t`| <-- Lock_1 per-CPU field 2154 | Lock_1 | for CPU1 2155 |----------------| 2156 | .... | 2157 |----------------| 2158 | `bakery_info_t`| <-- Lock_N per-CPU field 2159 | Lock_N | for CPU1 2160 ------------------ 2161 | XXXXX | 2162 | Padding to | 2163 | next Cache WB | 2164 | Granule | 2165 ------------------ 2166 2167Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an 2168operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1 2169``bakery_lock`` section need to be fetched and appropriate cache operations need 2170to be performed for each access. 2171 2172On Arm Platforms, bakery locks are used in psci (``psci_locks``) and power controller 2173driver (``arm_lock``). 2174 2175Non Functional Impact of removing coherent memory 2176~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2177 2178Removal of the coherent memory region leads to the additional software overhead 2179of performing cache maintenance for the affected data structures. However, since 2180the memory where the data structures are allocated is cacheable, the overhead is 2181mostly mitigated by an increase in performance. 2182 2183There is however a performance impact for bakery locks, due to: 2184 2185- Additional cache maintenance operations, and 2186- Multiple cache line reads for each lock operation, since the bakery locks 2187 for each CPU are distributed across different cache lines. 2188 2189The implementation has been optimized to minimize this additional overhead. 2190Measurements indicate that when bakery locks are allocated in Normal memory, the 2191minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas 2192in Device memory the same is 2 micro seconds. The measurements were done on the 2193Juno Arm development platform. 2194 2195As mentioned earlier, almost a page of memory can be saved by disabling 2196``USE_COHERENT_MEM``. Each platform needs to consider these trade-offs to decide 2197whether coherent memory should be used. If a platform disables 2198``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can 2199optionally define macro ``PLAT_PERCPU_BAKERY_LOCK_SIZE`` (see the 2200:ref:`Porting Guide`). Refer to the reference platform code for examples. 2201 2202Isolating code and read-only data on separate memory pages 2203---------------------------------------------------------- 2204 2205In the Armv8-A VMSA, translation table entries include fields that define the 2206properties of the target memory region, such as its access permissions. The 2207smallest unit of memory that can be addressed by a translation table entry is 2208a memory page. Therefore, if software needs to set different permissions on two 2209memory regions then it needs to map them using different memory pages. 2210 2211The default memory layout for each BL image is as follows: 2212 2213:: 2214 2215 | ... | 2216 +-------------------+ 2217 | Read-write data | 2218 +-------------------+ Page boundary 2219 | <Padding> | 2220 +-------------------+ 2221 | Exception vectors | 2222 +-------------------+ 2 KB boundary 2223 | <Padding> | 2224 +-------------------+ 2225 | Read-only data | 2226 +-------------------+ 2227 | Code | 2228 +-------------------+ BLx_BASE 2229 2230.. note:: 2231 The 2KB alignment for the exception vectors is an architectural 2232 requirement. 2233 2234The read-write data start on a new memory page so that they can be mapped with 2235read-write permissions, whereas the code and read-only data below are configured 2236as read-only. 2237 2238However, the read-only data are not aligned on a page boundary. They are 2239contiguous to the code. Therefore, the end of the code section and the beginning 2240of the read-only data one might share a memory page. This forces both to be 2241mapped with the same memory attributes. As the code needs to be executable, this 2242means that the read-only data stored on the same memory page as the code are 2243executable as well. This could potentially be exploited as part of a security 2244attack. 2245 2246TF provides the build flag ``SEPARATE_CODE_AND_RODATA`` to isolate the code and 2247read-only data on separate memory pages. This in turn allows independent control 2248of the access permissions for the code and read-only data. In this case, 2249platform code gets a finer-grained view of the image layout and can 2250appropriately map the code region as executable and the read-only data as 2251execute-never. 2252 2253This has an impact on memory footprint, as padding bytes need to be introduced 2254between the code and read-only data to ensure the segregation of the two. To 2255limit the memory cost, this flag also changes the memory layout such that the 2256code and exception vectors are now contiguous, like so: 2257 2258:: 2259 2260 | ... | 2261 +-------------------+ 2262 | Read-write data | 2263 +-------------------+ Page boundary 2264 | <Padding> | 2265 +-------------------+ 2266 | Read-only data | 2267 +-------------------+ Page boundary 2268 | <Padding> | 2269 +-------------------+ 2270 | Exception vectors | 2271 +-------------------+ 2 KB boundary 2272 | <Padding> | 2273 +-------------------+ 2274 | Code | 2275 +-------------------+ BLx_BASE 2276 2277With this more condensed memory layout, the separation of read-only data will 2278add zero or one page to the memory footprint of each BL image. Each platform 2279should consider the trade-off between memory footprint and security. 2280 2281This build flag is disabled by default, minimising memory footprint. On Arm 2282platforms, it is enabled. 2283 2284Publish and Subscribe Framework 2285------------------------------- 2286 2287The Publish and Subscribe Framework allows EL3 components to define and publish 2288events, to which other EL3 components can subscribe. 2289 2290The following macros are provided by the framework: 2291 2292- ``REGISTER_PUBSUB_EVENT(event)``: Defines an event, and takes one argument, 2293 the event name, which must be a valid C identifier. All calls to 2294 ``REGISTER_PUBSUB_EVENT`` macro must be placed in the file 2295 ``pubsub_events.h``. 2296 2297- ``PUBLISH_EVENT_ARG(event, arg)``: Publishes a defined event, by iterating 2298 subscribed handlers and calling them in turn. The handlers will be passed the 2299 parameter ``arg``. The expected use-case is to broadcast an event. 2300 2301- ``PUBLISH_EVENT(event)``: Like ``PUBLISH_EVENT_ARG``, except that the value 2302 ``NULL`` is passed to subscribed handlers. 2303 2304- ``SUBSCRIBE_TO_EVENT(event, handler)``: Registers the ``handler`` to 2305 subscribe to ``event``. The handler will be executed whenever the ``event`` 2306 is published. 2307 2308- ``for_each_subscriber(event, subscriber)``: Iterates through all handlers 2309 subscribed for ``event``. ``subscriber`` must be a local variable of type 2310 ``pubsub_cb_t *``, and will point to each subscribed handler in turn during 2311 iteration. This macro can be used for those patterns that none of the 2312 ``PUBLISH_EVENT_*()`` macros cover. 2313 2314Publishing an event that wasn't defined using ``REGISTER_PUBSUB_EVENT`` will 2315result in build error. Subscribing to an undefined event however won't. 2316 2317Subscribed handlers must be of type ``pubsub_cb_t``, with following function 2318signature: 2319 2320.. code:: c 2321 2322 typedef void* (*pubsub_cb_t)(const void *arg); 2323 2324There may be arbitrary number of handlers registered to the same event. The 2325order in which subscribed handlers are notified when that event is published is 2326not defined. Subscribed handlers may be executed in any order; handlers should 2327not assume any relative ordering amongst them. 2328 2329Publishing an event on a PE will result in subscribed handlers executing on that 2330PE only; it won't cause handlers to execute on a different PE. 2331 2332Note that publishing an event on a PE blocks until all the subscribed handlers 2333finish executing on the PE. 2334 2335TF-A generic code publishes and subscribes to some events within. Platform 2336ports are discouraged from subscribing to them. These events may be withdrawn, 2337renamed, or have their semantics altered in the future. Platforms may however 2338register, publish, and subscribe to platform-specific events. 2339 2340Publish and Subscribe Example 2341~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2342 2343A publisher that wants to publish event ``foo`` would: 2344 2345- Define the event ``foo`` in the ``pubsub_events.h``. 2346 2347 .. code:: c 2348 2349 REGISTER_PUBSUB_EVENT(foo); 2350 2351- Depending on the nature of event, use one of ``PUBLISH_EVENT_*()`` macros to 2352 publish the event at the appropriate path and time of execution. 2353 2354A subscriber that wants to subscribe to event ``foo`` published above would 2355implement: 2356 2357.. code:: c 2358 2359 void *foo_handler(const void *arg) 2360 { 2361 void *result; 2362 2363 /* Do handling ... */ 2364 2365 return result; 2366 } 2367 2368 SUBSCRIBE_TO_EVENT(foo, foo_handler); 2369 2370 2371Reclaiming the BL31 initialization code 2372~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2373 2374A significant amount of the code used for the initialization of BL31 is never 2375needed again after boot time. In order to reduce the runtime memory 2376footprint, the memory used for this code can be reclaimed after initialization 2377has finished and be used for runtime data. 2378 2379The build option ``RECLAIM_INIT_CODE`` can be set to mark this boot time code 2380with a ``.text.init.*`` attribute which can be filtered and placed suitably 2381within the BL image for later reclamation by the platform. The platform can 2382specify the filter and the memory region for this init section in BL31 via the 2383plat.ld.S linker script. For example, on the FVP, this section is placed 2384overlapping the secondary CPU stacks so that after the cold boot is done, this 2385memory can be reclaimed for the stacks. The init memory section is initially 2386mapped with ``RO``, ``EXECUTE`` attributes. After BL31 initialization has 2387completed, the FVP changes the attributes of this section to ``RW``, 2388``EXECUTE_NEVER`` allowing it to be used for runtime data. The memory attributes 2389are changed within the ``bl31_plat_runtime_setup`` platform hook. The init 2390section section can be reclaimed for any data which is accessed after cold 2391boot initialization and it is upto the platform to make the decision. 2392 2393.. _firmware_design_pmf: 2394 2395Performance Measurement Framework 2396--------------------------------- 2397 2398The Performance Measurement Framework (PMF) facilitates collection of 2399timestamps by registered services and provides interfaces to retrieve them 2400from within TF-A. A platform can choose to expose appropriate SMCs to 2401retrieve these collected timestamps. 2402 2403By default, the global physical counter is used for the timestamp 2404value and is read via ``CNTPCT_EL0``. The framework allows to retrieve 2405timestamps captured by other CPUs. 2406 2407Timestamp identifier format 2408~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2409 2410A PMF timestamp is uniquely identified across the system via the 2411timestamp ID or ``tid``. The ``tid`` is composed as follows: 2412 2413:: 2414 2415 Bits 0-7: The local timestamp identifier. 2416 Bits 8-9: Reserved. 2417 Bits 10-15: The service identifier. 2418 Bits 16-31: Reserved. 2419 2420#. The service identifier. Each PMF service is identified by a 2421 service name and a service identifier. Both the service name and 2422 identifier are unique within the system as a whole. 2423 2424#. The local timestamp identifier. This identifier is unique within a given 2425 service. 2426 2427Registering a PMF service 2428~~~~~~~~~~~~~~~~~~~~~~~~~ 2429 2430To register a PMF service, the ``PMF_REGISTER_SERVICE()`` macro from ``pmf.h`` 2431is used. The arguments required are the service name, the service ID, 2432the total number of local timestamps to be captured and a set of flags. 2433 2434The ``flags`` field can be specified as a bitwise-OR of the following values: 2435 2436:: 2437 2438 PMF_STORE_ENABLE: The timestamp is stored in memory for later retrieval. 2439 PMF_DUMP_ENABLE: The timestamp is dumped on the serial console. 2440 2441The ``PMF_REGISTER_SERVICE()`` reserves memory to store captured 2442timestamps in a PMF specific linker section at build time. 2443Additionally, it defines necessary functions to capture and 2444retrieve a particular timestamp for the given service at runtime. 2445 2446The macro ``PMF_REGISTER_SERVICE()`` only enables capturing PMF timestamps 2447from within TF-A. In order to retrieve timestamps from outside of TF-A, the 2448``PMF_REGISTER_SERVICE_SMC()`` macro must be used instead. This macro 2449accepts the same set of arguments as the ``PMF_REGISTER_SERVICE()`` 2450macro but additionally supports retrieving timestamps using SMCs. 2451 2452Capturing a timestamp 2453~~~~~~~~~~~~~~~~~~~~~ 2454 2455PMF timestamps are stored in a per-service timestamp region. On a 2456system with multiple CPUs, each timestamp is captured and stored 2457in a per-CPU cache line aligned memory region. 2458 2459Having registered the service, the ``PMF_CAPTURE_TIMESTAMP()`` macro can be 2460used to capture a timestamp at the location where it is used. The macro 2461takes the service name, a local timestamp identifier and a flag as arguments. 2462 2463The ``flags`` field argument can be zero, or ``PMF_CACHE_MAINT`` which 2464instructs PMF to do cache maintenance following the capture. Cache 2465maintenance is required if any of the service's timestamps are captured 2466with data cache disabled. 2467 2468To capture a timestamp in assembly code, the caller should use 2469``pmf_calc_timestamp_addr`` macro (defined in ``pmf_asm_macros.S``) to 2470calculate the address of where the timestamp would be stored. The 2471caller should then read ``CNTPCT_EL0`` register to obtain the timestamp 2472and store it at the determined address for later retrieval. 2473 2474Retrieving a timestamp 2475~~~~~~~~~~~~~~~~~~~~~~ 2476 2477From within TF-A, timestamps for individual CPUs can be retrieved using either 2478``PMF_GET_TIMESTAMP_BY_MPIDR()`` or ``PMF_GET_TIMESTAMP_BY_INDEX()`` macros. 2479These macros accept the CPU's MPIDR value, or its ordinal position 2480respectively. 2481 2482From outside TF-A, timestamps for individual CPUs can be retrieved by calling 2483into ``pmf_smc_handler()``. 2484 2485:: 2486 2487 Interface : pmf_smc_handler() 2488 Argument : unsigned int smc_fid, u_register_t x1, 2489 u_register_t x2, u_register_t x3, 2490 u_register_t x4, void *cookie, 2491 void *handle, u_register_t flags 2492 Return : uintptr_t 2493 2494 smc_fid: Holds the SMC identifier which is either `PMF_SMC_GET_TIMESTAMP_32` 2495 when the caller of the SMC is running in AArch32 mode 2496 or `PMF_SMC_GET_TIMESTAMP_64` when the caller is running in AArch64 mode. 2497 x1: Timestamp identifier. 2498 x2: The `mpidr` of the CPU for which the timestamp has to be retrieved. 2499 This can be the `mpidr` of a different core to the one initiating 2500 the SMC. In that case, service specific cache maintenance may be 2501 required to ensure the updated copy of the timestamp is returned. 2502 x3: A flags value that is either 0 or `PMF_CACHE_MAINT`. If 2503 `PMF_CACHE_MAINT` is passed, then the PMF code will perform a 2504 cache invalidate before reading the timestamp. This ensures 2505 an updated copy is returned. 2506 2507The remaining arguments, ``x4``, ``cookie``, ``handle`` and ``flags`` are unused 2508in this implementation. 2509 2510PMF code structure 2511~~~~~~~~~~~~~~~~~~ 2512 2513#. ``pmf_main.c`` consists of core functions that implement service registration, 2514 initialization, storing, dumping and retrieving timestamps. 2515 2516#. ``pmf_smc.c`` contains the SMC handling for registered PMF services. 2517 2518#. ``pmf.h`` contains the public interface to Performance Measurement Framework. 2519 2520#. ``pmf_asm_macros.S`` consists of macros to facilitate capturing timestamps in 2521 assembly code. 2522 2523#. ``pmf_helpers.h`` is an internal header used by ``pmf.h``. 2524 2525Armv8-A Architecture Extensions 2526------------------------------- 2527 2528TF-A makes use of Armv8-A Architecture Extensions where applicable. This 2529section lists the usage of Architecture Extensions, and build flags 2530controlling them. 2531 2532In general, and unless individually mentioned, the build options 2533``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` select the Architecture Extension to 2534target when building TF-A. Subsequent Arm Architecture Extensions are backward 2535compatible with previous versions. 2536 2537The build system only requires that ``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` have a 2538valid numeric value. These build options only control whether or not 2539Architecture Extension-specific code is included in the build. Otherwise, TF-A 2540targets the base Armv8.0-A architecture; i.e. as if ``ARM_ARCH_MAJOR`` == 8 2541and ``ARM_ARCH_MINOR`` == 0, which are also their respective default values. 2542 2543.. seealso:: :ref:`Build Options` 2544 2545For details on the Architecture Extension and available features, please refer 2546to the respective Architecture Extension Supplement. 2547 2548Armv8.1-A 2549~~~~~~~~~ 2550 2551This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when 2552``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` >= 1. 2553 2554- By default, a load-/store-exclusive instruction pair is used to implement 2555 spinlocks. The ``USE_SPINLOCK_CAS`` build option when set to 1 selects the 2556 spinlock implementation using the ARMv8.1-LSE Compare and Swap instruction. 2557 Notice this instruction is only available in AArch64 execution state, so 2558 the option is only available to AArch64 builds. 2559 2560Armv8.2-A 2561~~~~~~~~~ 2562 2563- The presence of ARMv8.2-TTCNP is detected at runtime. When it is present, the 2564 Common not Private (TTBRn_ELx.CnP) bit is enabled to indicate that multiple 2565 Processing Elements in the same Inner Shareable domain use the same 2566 translation table entries for a given stage of translation for a particular 2567 translation regime. 2568 2569Armv8.3-A 2570~~~~~~~~~ 2571 2572- Pointer authentication features of Armv8.3-A are unconditionally enabled in 2573 the Non-secure world so that lower ELs are allowed to use them without 2574 causing a trap to EL3. 2575 2576 In order to enable the Secure world to use it, ``CTX_INCLUDE_PAUTH_REGS`` 2577 must be set to 1. This will add all pointer authentication system registers 2578 to the context that is saved when doing a world switch. 2579 2580 The TF-A itself has support for pointer authentication at runtime 2581 that can be enabled by setting ``BRANCH_PROTECTION`` option to non-zero and 2582 ``CTX_INCLUDE_PAUTH_REGS`` to 1. This enables pointer authentication in BL1, 2583 BL2, BL31, and the TSP if it is used. 2584 2585 These options are experimental features. 2586 2587 Note that Pointer Authentication is enabled for Non-secure world irrespective 2588 of the value of these build flags if the CPU supports it. 2589 2590 If ``ARM_ARCH_MAJOR == 8`` and ``ARM_ARCH_MINOR >= 3`` the code footprint of 2591 enabling PAuth is lower because the compiler will use the optimized 2592 PAuth instructions rather than the backwards-compatible ones. 2593 2594Armv8.5-A 2595~~~~~~~~~ 2596 2597- Branch Target Identification feature is selected by ``BRANCH_PROTECTION`` 2598 option set to 1. This option defaults to 0 and this is an experimental 2599 feature. 2600 2601- Memory Tagging Extension feature is unconditionally enabled for both worlds 2602 (at EL0 and S-EL0) if it is only supported at EL0. If instead it is 2603 implemented at all ELs, it is unconditionally enabled for only the normal 2604 world. To enable it for the secure world as well, the build option 2605 ``CTX_INCLUDE_MTE_REGS`` is required. If the hardware does not implement 2606 MTE support at all, it is always disabled, no matter what build options 2607 are used. 2608 2609Armv7-A 2610~~~~~~~ 2611 2612This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 7. 2613 2614There are several Armv7-A extensions available. Obviously the TrustZone 2615extension is mandatory to support the TF-A bootloader and runtime services. 2616 2617Platform implementing an Armv7-A system can to define from its target 2618Cortex-A architecture through ``ARM_CORTEX_A<X> = yes`` in their 2619``platform.mk`` script. For example ``ARM_CORTEX_A15=yes`` for a 2620Cortex-A15 target. 2621 2622Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support. 2623Note that using neon at runtime has constraints on non secure world context. 2624TF-A does not yet provide VFP context management. 2625 2626Directive ``ARM_CORTEX_A<x>`` and ``ARM_WITH_NEON`` are used to set 2627the toolchain target architecture directive. 2628 2629Platform may choose to not define straight the toolchain target architecture 2630directive by defining ``MARCH32_DIRECTIVE``. 2631I.e: 2632 2633.. code:: make 2634 2635 MARCH32_DIRECTIVE := -mach=armv7-a 2636 2637Code Structure 2638-------------- 2639 2640TF-A code is logically divided between the three boot loader stages mentioned 2641in the previous sections. The code is also divided into the following 2642categories (present as directories in the source code): 2643 2644- **Platform specific.** Choice of architecture specific code depends upon 2645 the platform. 2646- **Common code.** This is platform and architecture agnostic code. 2647- **Library code.** This code comprises of functionality commonly used by all 2648 other code. The PSCI implementation and other EL3 runtime frameworks reside 2649 as Library components. 2650- **Stage specific.** Code specific to a boot stage. 2651- **Drivers.** 2652- **Services.** EL3 runtime services (eg: SPD). Specific SPD services 2653 reside in the ``services/spd`` directory (e.g. ``services/spd/tspd``). 2654 2655Each boot loader stage uses code from one or more of the above mentioned 2656categories. Based upon the above, the code layout looks like this: 2657 2658:: 2659 2660 Directory Used by BL1? Used by BL2? Used by BL31? 2661 bl1 Yes No No 2662 bl2 No Yes No 2663 bl31 No No Yes 2664 plat Yes Yes Yes 2665 drivers Yes No Yes 2666 common Yes Yes Yes 2667 lib Yes Yes Yes 2668 services No No Yes 2669 2670The build system provides a non configurable build option IMAGE_BLx for each 2671boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE_BL1 will be 2672defined by the build system. This enables TF-A to compile certain code only 2673for specific boot loader stages 2674 2675All assembler files have the ``.S`` extension. The linker source files for each 2676boot stage have the extension ``.ld.S``. These are processed by GCC to create the 2677linker scripts which have the extension ``.ld``. 2678 2679FDTs provide a description of the hardware platform and are used by the Linux 2680kernel at boot time. These can be found in the ``fdts`` directory. 2681 2682.. rubric:: References 2683 2684- `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D)`_ 2685 2686- `Power State Coordination Interface PDD`_ 2687 2688- `SMC Calling Convention PDD`_ 2689 2690- :ref:`Interrupt Management Framework` 2691 2692-------------- 2693 2694*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.* 2695 2696.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2697.. _SMCCC: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf 2698.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2699.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2700.. _Arm ARM: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0487a.e/index.html 2701.. _SMC Calling Convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf 2702.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a 2703 2704.. |Image 1| image:: ../resources/diagrams/rt-svc-descs-layout.png 2705
