1Firmware Design 2=============== 3 4Trusted Firmware-A (TF-A) implements a subset of the Trusted Board Boot 5Requirements (TBBR) Platform Design Document (PDD) for Arm reference 6platforms. 7 8The TBB sequence starts when the platform is powered on and runs up 9to the stage where it hands-off control to firmware running in the normal 10world in DRAM. This is the cold boot path. 11 12TF-A also implements the `Power State Coordination Interface PDD`_ as a 13runtime service. PSCI is the interface from normal world software to firmware 14implementing power management use-cases (for example, secondary CPU boot, 15hotplug and idle). Normal world software can access TF-A runtime services via 16the Arm SMC (Secure Monitor Call) instruction. The SMC instruction must be 17used as mandated by the SMC Calling Convention (`SMCCC`_). 18 19TF-A implements a framework for configuring and managing interrupts generated 20in either security state. The details of the interrupt management framework 21and its design can be found in :ref:`Interrupt Management Framework`. 22 23TF-A also implements a library for setting up and managing the translation 24tables. The details of this library can be found in 25:ref:`Translation (XLAT) Tables Library`. 26 27TF-A can be built to support either AArch64 or AArch32 execution state. 28.. note:: 29 30 The descriptions in this chapter are for the Arm TrustZone architecture. 31 For changes to the firmware design for the 32 `Arm Confidential Compute Architecture (Arm CCA)`_ please refer to the 33 chapter :ref:`Realm Management Extension (RME)`. 34 35Cold boot 36--------- 37 38The cold boot path starts when the platform is physically turned on. If 39``COLD_BOOT_SINGLE_CPU=0``, one of the CPUs released from reset is chosen as the 40primary CPU, and the remaining CPUs are considered secondary CPUs. The primary 41CPU is chosen through platform-specific means. The cold boot path is mainly 42executed by the primary CPU, other than essential CPU initialization executed by 43all CPUs. The secondary CPUs are kept in a safe platform-specific state until 44the primary CPU has performed enough initialization to boot them. 45 46Refer to the :ref:`CPU Reset` for more information on the effect of the 47``COLD_BOOT_SINGLE_CPU`` platform build option. 48 49The cold boot path in this implementation of TF-A depends on the execution 50state. For AArch64, it is divided into five steps (in order of execution): 51 52- Boot Loader stage 1 (BL1) *AP Trusted ROM* 53- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 54- Boot Loader stage 3-1 (BL31) *EL3 Runtime Software* 55- Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional) 56- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 57 58For AArch32, it is divided into four steps (in order of execution): 59 60- Boot Loader stage 1 (BL1) *AP Trusted ROM* 61- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 62- Boot Loader stage 3-2 (BL32) *EL3 Runtime Software* 63- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 64 65Arm development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a 66combination of the following types of memory regions. Each bootloader stage uses 67one or more of these memory regions. 68 69- Regions accessible from both non-secure and secure states. For example, 70 non-trusted SRAM, ROM and DRAM. 71- Regions accessible from only the secure state. For example, trusted SRAM and 72 ROM. The FVPs also implement the trusted DRAM which is statically 73 configured. Additionally, the Base FVPs and Juno development platform 74 configure the TrustZone Controller (TZC) to create a region in the DRAM 75 which is accessible only from the secure state. 76 77The sections below provide the following details: 78 79- dynamic configuration of Boot Loader stages 80- initialization and execution of the first three stages during cold boot 81- specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for 82 AArch32) entrypoint requirements for use by alternative Trusted Boot 83 Firmware in place of the provided BL1 and BL2 84 85Dynamic Configuration during cold boot 86~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 87 88Each of the Boot Loader stages may be dynamically configured if required by the 89platform. The Boot Loader stage may optionally specify a firmware 90configuration file and/or hardware configuration file as listed below: 91 92- FW_CONFIG - The firmware configuration file. Holds properties shared across 93 all BLx images. 94 An example is the "dtb-registry" node, which contains the information about 95 the other device tree configurations (load-address, size, image_id). 96- HW_CONFIG - The hardware configuration file. Can be shared by all Boot Loader 97 stages and also by the Normal World Rich OS. 98- TB_FW_CONFIG - Trusted Boot Firmware configuration file. Shared between BL1 99 and BL2. 100- SOC_FW_CONFIG - SoC Firmware configuration file. Used by BL31. 101- TOS_FW_CONFIG - Trusted OS Firmware configuration file. Used by Trusted OS 102 (BL32). 103- NT_FW_CONFIG - Non Trusted Firmware configuration file. Used by Non-trusted 104 firmware (BL33). 105 106The Arm development platforms use the Flattened Device Tree format for the 107dynamic configuration files. 108 109Each Boot Loader stage can pass up to 4 arguments via registers to the next 110stage. BL2 passes the list of the next images to execute to the *EL3 Runtime 111Software* (BL31 for AArch64 and BL32 for AArch32) via `arg0`. All the other 112arguments are platform defined. The Arm development platforms use the following 113convention: 114 115- BL1 passes the address of a meminfo_t structure to BL2 via ``arg1``. This 116 structure contains the memory layout available to BL2. 117- When dynamic configuration files are present, the firmware configuration for 118 the next Boot Loader stage is populated in the first available argument and 119 the generic hardware configuration is passed the next available argument. 120 For example, 121 122 - FW_CONFIG is loaded by BL1, then its address is passed in ``arg0`` to BL2. 123 - TB_FW_CONFIG address is retrieved by BL2 from FW_CONFIG device tree. 124 - If HW_CONFIG is loaded by BL1, then its address is passed in ``arg2`` to 125 BL2. Note, ``arg1`` is already used for meminfo_t. 126 - If SOC_FW_CONFIG is loaded by BL2, then its address is passed in ``arg1`` 127 to BL31. Note, ``arg0`` is used to pass the list of executable images. 128 - Similarly, if HW_CONFIG is loaded by BL1 or BL2, then its address is 129 passed in ``arg2`` to BL31. 130 - For other BL3x images, if the firmware configuration file is loaded by 131 BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded 132 then its address is passed in ``arg1``. 133 - In case of the Arm FVP platform, FW_CONFIG address passed in ``arg1`` to 134 BL31/SP_MIN, and the SOC_FW_CONFIG and HW_CONFIG details are retrieved 135 from FW_CONFIG device tree. 136 137BL1 138~~~ 139 140This stage begins execution from the platform's reset vector at EL3. The reset 141address is platform dependent but it is usually located in a Trusted ROM area. 142The BL1 data section is copied to trusted SRAM at runtime. 143 144On the Arm development platforms, BL1 code starts execution from the reset 145vector defined by the constant ``BL1_RO_BASE``. The BL1 data section is copied 146to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``. 147 148The functionality implemented by this stage is as follows. 149 150Determination of boot path 151^^^^^^^^^^^^^^^^^^^^^^^^^^ 152 153Whenever a CPU is released from reset, BL1 needs to distinguish between a warm 154boot and a cold boot. This is done using platform-specific mechanisms (see the 155``plat_get_my_entrypoint()`` function in the :ref:`Porting Guide`). In the case 156of a warm boot, a CPU is expected to continue execution from a separate 157entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe 158platform-specific state (see the ``plat_secondary_cold_boot_setup()`` function in 159the :ref:`Porting Guide`) while the primary CPU executes the remaining cold boot 160path as described in the following sections. 161 162This step only applies when ``PROGRAMMABLE_RESET_ADDRESS=0``. Refer to the 163:ref:`CPU Reset` for more information on the effect of the 164``PROGRAMMABLE_RESET_ADDRESS`` platform build option. 165 166Architectural initialization 167^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 168 169BL1 performs minimal architectural initialization as follows. 170 171- Exception vectors 172 173 BL1 sets up simple exception vectors for both synchronous and asynchronous 174 exceptions. The default behavior upon receiving an exception is to populate 175 a status code in the general purpose register ``X0/R0`` and call the 176 ``plat_report_exception()`` function (see the :ref:`Porting Guide`). The 177 status code is one of: 178 179 For AArch64: 180 181 :: 182 183 0x0 : Synchronous exception from Current EL with SP_EL0 184 0x1 : IRQ exception from Current EL with SP_EL0 185 0x2 : FIQ exception from Current EL with SP_EL0 186 0x3 : System Error exception from Current EL with SP_EL0 187 0x4 : Synchronous exception from Current EL with SP_ELx 188 0x5 : IRQ exception from Current EL with SP_ELx 189 0x6 : FIQ exception from Current EL with SP_ELx 190 0x7 : System Error exception from Current EL with SP_ELx 191 0x8 : Synchronous exception from Lower EL using aarch64 192 0x9 : IRQ exception from Lower EL using aarch64 193 0xa : FIQ exception from Lower EL using aarch64 194 0xb : System Error exception from Lower EL using aarch64 195 0xc : Synchronous exception from Lower EL using aarch32 196 0xd : IRQ exception from Lower EL using aarch32 197 0xe : FIQ exception from Lower EL using aarch32 198 0xf : System Error exception from Lower EL using aarch32 199 200 For AArch32: 201 202 :: 203 204 0x10 : User mode 205 0x11 : FIQ mode 206 0x12 : IRQ mode 207 0x13 : SVC mode 208 0x16 : Monitor mode 209 0x17 : Abort mode 210 0x1a : Hypervisor mode 211 0x1b : Undefined mode 212 0x1f : System mode 213 214 The ``plat_report_exception()`` implementation on the Arm FVP port programs 215 the Versatile Express System LED register in the following format to 216 indicate the occurrence of an unexpected exception: 217 218 :: 219 220 SYS_LED[0] - Security state (Secure=0/Non-Secure=1) 221 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0) 222 For AArch32 it is always 0x0 223 SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value 224 of the status code 225 226 A write to the LED register reflects in the System LEDs (S6LED0..7) in the 227 CLCD window of the FVP. 228 229 BL1 does not expect to receive any exceptions other than the SMC exception. 230 For the latter, BL1 installs a simple stub. The stub expects to receive a 231 limited set of SMC types (determined by their function IDs in the general 232 purpose register ``X0/R0``): 233 234 - ``BL1_SMC_RUN_IMAGE``: This SMC is raised by BL2 to make BL1 pass control 235 to EL3 Runtime Software. 236 - All SMCs listed in section "BL1 SMC Interface" in the :ref:`Firmware Update (FWU)` 237 Design Guide are supported for AArch64 only. These SMCs are currently 238 not supported when BL1 is built for AArch32. 239 240 Any other SMC leads to an assertion failure. 241 242- CPU initialization 243 244 BL1 calls the ``reset_handler()`` function which in turn calls the CPU 245 specific reset handler function (see the section: "CPU specific operations 246 framework"). 247 248- Control register setup (for AArch64) 249 250 - ``SCTLR_EL3``. Instruction cache is enabled by setting the ``SCTLR_EL3.I`` 251 bit. Alignment and stack alignment checking is enabled by setting the 252 ``SCTLR_EL3.A`` and ``SCTLR_EL3.SA`` bits. Exception endianness is set to 253 little-endian by clearing the ``SCTLR_EL3.EE`` bit. 254 255 - ``SCR_EL3``. The register width of the next lower exception level is set 256 to AArch64 by setting the ``SCR.RW`` bit. The ``SCR.EA`` bit is set to trap 257 both External Aborts and SError Interrupts in EL3. The ``SCR.SIF`` bit is 258 also set to disable instruction fetches from Non-secure memory when in 259 secure state. 260 261 - ``CPTR_EL3``. Accesses to the ``CPACR_EL1`` register from EL1 or EL2, or the 262 ``CPTR_EL2`` register from EL2 are configured to not trap to EL3 by 263 clearing the ``CPTR_EL3.TCPAC`` bit. Access to the trace functionality is 264 configured not to trap to EL3 by clearing the ``CPTR_EL3.TTA`` bit. 265 Instructions that access the registers associated with Floating Point 266 and Advanced SIMD execution are configured to not trap to EL3 by 267 clearing the ``CPTR_EL3.TFP`` bit. 268 269 - ``DAIF``. The SError interrupt is enabled by clearing the SError interrupt 270 mask bit. 271 272 - ``MDCR_EL3``. The trap controls, ``MDCR_EL3.TDOSA``, ``MDCR_EL3.TDA`` and 273 ``MDCR_EL3.TPM``, are set so that accesses to the registers they control 274 do not trap to EL3. AArch64 Secure self-hosted debug is disabled by 275 setting the ``MDCR_EL3.SDD`` bit. Also ``MDCR_EL3.SPD32`` is set to 276 disable AArch32 Secure self-hosted privileged debug from S-EL1. 277 278- Control register setup (for AArch32) 279 280 - ``SCTLR``. Instruction cache is enabled by setting the ``SCTLR.I`` bit. 281 Alignment checking is enabled by setting the ``SCTLR.A`` bit. 282 Exception endianness is set to little-endian by clearing the 283 ``SCTLR.EE`` bit. 284 285 - ``SCR``. The ``SCR.SIF`` bit is set to disable instruction fetches from 286 Non-secure memory when in secure state. 287 288 - ``CPACR``. Allow execution of Advanced SIMD instructions at PL0 and PL1, 289 by clearing the ``CPACR.ASEDIS`` bit. Access to the trace functionality 290 is configured not to trap to undefined mode by clearing the 291 ``CPACR.TRCDIS`` bit. 292 293 - ``NSACR``. Enable non-secure access to Advanced SIMD functionality and 294 system register access to implemented trace registers. 295 296 - ``FPEXC``. Enable access to the Advanced SIMD and floating-point 297 functionality from all Exception levels. 298 299 - ``CPSR.A``. The Asynchronous data abort interrupt is enabled by clearing 300 the Asynchronous data abort interrupt mask bit. 301 302 - ``SDCR``. The ``SDCR.SPD`` field is set to disable AArch32 Secure 303 self-hosted privileged debug. 304 305Platform initialization 306^^^^^^^^^^^^^^^^^^^^^^^ 307 308On Arm platforms, BL1 performs the following platform initializations: 309 310- Enable the Trusted Watchdog. 311- Initialize the console. 312- Configure the Interconnect to enable hardware coherency. 313- Enable the MMU and map the memory it needs to access. 314- Configure any required platform storage to load the next bootloader image 315 (BL2). 316- If the BL1 dynamic configuration file, ``TB_FW_CONFIG``, is available, then 317 load it to the platform defined address and make it available to BL2 via 318 ``arg0``. 319- Configure the system timer and program the `CNTFRQ_EL0` for use by NS-BL1U 320 and NS-BL2U firmware update images. 321 322Firmware Update detection and execution 323^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 324 325After performing platform setup, BL1 common code calls 326``bl1_plat_get_next_image_id()`` to determine if :ref:`Firmware Update (FWU)` is 327required or to proceed with the normal boot process. If the platform code 328returns ``BL2_IMAGE_ID`` then the normal boot sequence is executed as described 329in the next section, else BL1 assumes that :ref:`Firmware Update (FWU)` is 330required and execution passes to the first image in the 331:ref:`Firmware Update (FWU)` process. In either case, BL1 retrieves a descriptor 332of the next image by calling ``bl1_plat_get_image_desc()``. The image descriptor 333contains an ``entry_point_info_t`` structure, which BL1 uses to initialize the 334execution state of the next image. 335 336BL2 image load and execution 337^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 338 339In the normal boot flow, BL1 execution continues as follows: 340 341#. BL1 prints the following string from the primary CPU to indicate successful 342 execution of the BL1 stage: 343 344 :: 345 346 "Booting Trusted Firmware" 347 348#. BL1 loads a BL2 raw binary image from platform storage, at a 349 platform-specific base address. Prior to the load, BL1 invokes 350 ``bl1_plat_handle_pre_image_load()`` which allows the platform to update or 351 use the image information. If the BL2 image file is not present or if 352 there is not enough free trusted SRAM the following error message is 353 printed: 354 355 :: 356 357 "Failed to load BL2 firmware." 358 359#. BL1 invokes ``bl1_plat_handle_post_image_load()`` which again is intended 360 for platforms to take further action after image load. This function must 361 populate the necessary arguments for BL2, which may also include the memory 362 layout. Further description of the memory layout can be found later 363 in this document. 364 365#. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at 366 Secure SVC mode (for AArch32), starting from its load address. 367 368BL2 369~~~ 370 371BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure 372SVC mode (for AArch32) . BL2 is linked against and loaded at a platform-specific 373base address (more information can be found later in this document). 374The functionality implemented by BL2 is as follows. 375 376Architectural initialization 377^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 378 379For AArch64, BL2 performs the minimal architectural initialization required 380for subsequent stages of TF-A and normal world software. EL1 and EL0 are given 381access to Floating Point and Advanced SIMD registers by setting the 382``CPACR.FPEN`` bits. 383 384For AArch32, the minimal architectural initialization required for subsequent 385stages of TF-A and normal world software is taken care of in BL1 as both BL1 386and BL2 execute at PL1. 387 388Platform initialization 389^^^^^^^^^^^^^^^^^^^^^^^ 390 391On Arm platforms, BL2 performs the following platform initializations: 392 393- Initialize the console. 394- Configure any required platform storage to allow loading further bootloader 395 images. 396- Enable the MMU and map the memory it needs to access. 397- Perform platform security setup to allow access to controlled components. 398- Reserve some memory for passing information to the next bootloader image 399 EL3 Runtime Software and populate it. 400- Define the extents of memory available for loading each subsequent 401 bootloader image. 402- If BL1 has passed TB_FW_CONFIG dynamic configuration file in ``arg0``, 403 then parse it. 404 405Image loading in BL2 406^^^^^^^^^^^^^^^^^^^^ 407 408BL2 generic code loads the images based on the list of loadable images 409provided by the platform. BL2 passes the list of executable images 410provided by the platform to the next handover BL image. 411 412The list of loadable images provided by the platform may also contain 413dynamic configuration files. The files are loaded and can be parsed as 414needed in the ``bl2_plat_handle_post_image_load()`` function. These 415configuration files can be passed to next Boot Loader stages as arguments 416by updating the corresponding entrypoint information in this function. 417 418SCP_BL2 (System Control Processor Firmware) image load 419^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 420 421Some systems have a separate System Control Processor (SCP) for power, clock, 422reset and system control. BL2 loads the optional SCP_BL2 image from platform 423storage into a platform-specific region of secure memory. The subsequent 424handling of SCP_BL2 is platform specific. For example, on the Juno Arm 425development platform port the image is transferred into SCP's internal memory 426using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM 427memory. The SCP executes SCP_BL2 and signals to the Application Processor (AP) 428for BL2 execution to continue. 429 430EL3 Runtime Software image load 431^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 432 433BL2 loads the EL3 Runtime Software image from platform storage into a platform- 434specific address in trusted SRAM. If there is not enough memory to load the 435image or image is missing it leads to an assertion failure. 436 437AArch64 BL32 (Secure-EL1 Payload) image load 438^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 439 440BL2 loads the optional BL32 image from platform storage into a platform- 441specific region of secure memory. The image executes in the secure world. BL2 442relies on BL31 to pass control to the BL32 image, if present. Hence, BL2 443populates a platform-specific area of memory with the entrypoint/load-address 444of the BL32 image. The value of the Saved Processor Status Register (``SPSR``) 445for entry into BL32 is not determined by BL2, it is initialized by the 446Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for 447managing interaction with BL32. This information is passed to BL31. 448 449BL33 (Non-trusted Firmware) image load 450^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 451 452BL2 loads the BL33 image (e.g. UEFI or other test or boot software) from 453platform storage into non-secure memory as defined by the platform. 454 455BL2 relies on EL3 Runtime Software to pass control to BL33 once secure state 456initialization is complete. Hence, BL2 populates a platform-specific area of 457memory with the entrypoint and Saved Program Status Register (``SPSR``) of the 458normal world software image. The entrypoint is the load address of the BL33 459image. The ``SPSR`` is determined as specified in Section 5.13 of the 460`Power State Coordination Interface PDD`_. This information is passed to the 461EL3 Runtime Software. 462 463AArch64 BL31 (EL3 Runtime Software) execution 464^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 465 466BL2 execution continues as follows: 467 468#. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the 469 BL31 entrypoint. The exception is handled by the SMC exception handler 470 installed by BL1. 471 472#. BL1 turns off the MMU and flushes the caches. It clears the 473 ``SCTLR_EL3.M/I/C`` bits, flushes the data cache to the point of coherency 474 and invalidates the TLBs. 475 476#. BL1 passes control to BL31 at the specified entrypoint at EL3. 477 478Running BL2 at EL3 execution level 479~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 480 481Some platforms have a non-TF-A Boot ROM that expects the next boot stage 482to execute at EL3. On these platforms, TF-A BL1 is a waste of memory 483as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid 484this waste, a special mode enables BL2 to execute at EL3, which allows 485a non-TF-A Boot ROM to load and jump directly to BL2. This mode is selected 486when the build flag RESET_TO_BL2 is enabled. 487The main differences in this mode are: 488 489#. BL2 includes the reset code and the mailbox mechanism to differentiate 490 cold boot and warm boot. It runs at EL3 doing the arch 491 initialization required for EL3. 492 493#. BL2 does not receive the meminfo information from BL1 anymore. This 494 information can be passed by the Boot ROM or be internal to the 495 BL2 image. 496 497#. Since BL2 executes at EL3, BL2 jumps directly to the next image, 498 instead of invoking the RUN_IMAGE SMC call. 499 500 501We assume 3 different types of BootROM support on the platform: 502 503#. The Boot ROM always jumps to the same address, for both cold 504 and warm boot. In this case, we will need to keep a resident part 505 of BL2 whose memory cannot be reclaimed by any other image. The 506 linker script defines the symbols __TEXT_RESIDENT_START__ and 507 __TEXT_RESIDENT_END__ that allows the platform to configure 508 correctly the memory map. 509#. The platform has some mechanism to indicate the jump address to the 510 Boot ROM. Platform code can then program the jump address with 511 psci_warmboot_entrypoint during cold boot. 512#. The platform has some mechanism to program the reset address using 513 the PROGRAMMABLE_RESET_ADDRESS feature. Platform code can then 514 program the reset address with psci_warmboot_entrypoint during 515 cold boot, bypassing the boot ROM for warm boot. 516 517In the last 2 cases, no part of BL2 needs to remain resident at 518runtime. In the first 2 cases, we expect the Boot ROM to be able to 519differentiate between warm and cold boot, to avoid loading BL2 again 520during warm boot. 521 522This functionality can be tested with FVP loading the image directly 523in memory and changing the address where the system jumps at reset. 524For example: 525 526 -C cluster0.cpu0.RVBAR=0x4022000 527 --data cluster0.cpu0=bl2.bin@0x4022000 528 529With this configuration, FVP is like a platform of the first case, 530where the Boot ROM jumps always to the same address. For simplification, 531BL32 is loaded in DRAM in this case, to avoid other images reclaiming 532BL2 memory. 533 534 535AArch64 BL31 536~~~~~~~~~~~~ 537 538The image for this stage is loaded by BL2 and BL1 passes control to BL31 at 539EL3. BL31 executes solely in trusted SRAM. BL31 is linked against and 540loaded at a platform-specific base address (more information can be found later 541in this document). The functionality implemented by BL31 is as follows. 542 543Architectural initialization 544^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 545 546Currently, BL31 performs a similar architectural initialization to BL1 as 547far as system register settings are concerned. Since BL1 code resides in ROM, 548architectural initialization in BL31 allows override of any previous 549initialization done by BL1. 550 551BL31 initializes the per-CPU data framework, which provides a cache of 552frequently accessed per-CPU data optimised for fast, concurrent manipulation 553on different CPUs. This buffer includes pointers to per-CPU contexts, crash 554buffer, CPU reset and power down operations, PSCI data, platform data and so on. 555 556It then replaces the exception vectors populated by BL1 with its own. BL31 557exception vectors implement more elaborate support for handling SMCs since this 558is the only mechanism to access the runtime services implemented by BL31 (PSCI 559for example). BL31 checks each SMC for validity as specified by the 560`SMC Calling Convention`_ before passing control to the required SMC 561handler routine. 562 563BL31 programs the ``CNTFRQ_EL0`` register with the clock frequency of the system 564counter, which is provided by the platform. 565 566Platform initialization 567^^^^^^^^^^^^^^^^^^^^^^^ 568 569BL31 performs detailed platform initialization, which enables normal world 570software to function correctly. 571 572On Arm platforms, this consists of the following: 573 574- Initialize the console. 575- Configure the Interconnect to enable hardware coherency. 576- Enable the MMU and map the memory it needs to access. 577- Initialize the generic interrupt controller. 578- Initialize the power controller device. 579- Detect the system topology. 580 581Runtime services initialization 582^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 583 584BL31 is responsible for initializing the runtime services. One of them is PSCI. 585 586As part of the PSCI initializations, BL31 detects the system topology. It also 587initializes the data structures that implement the state machine used to track 588the state of power domain nodes. The state can be one of ``OFF``, ``RUN`` or 589``RETENTION``. All secondary CPUs are initially in the ``OFF`` state. The cluster 590that the primary CPU belongs to is ``ON``; any other cluster is ``OFF``. It also 591initializes the locks that protect them. BL31 accesses the state of a CPU or 592cluster immediately after reset and before the data cache is enabled in the 593warm boot path. It is not currently possible to use 'exclusive' based spinlocks, 594therefore BL31 uses locks based on Lamport's Bakery algorithm instead. 595 596The runtime service framework and its initialization is described in more 597detail in the "EL3 runtime services framework" section below. 598 599Details about the status of the PSCI implementation are provided in the 600"Power State Coordination Interface" section below. 601 602AArch64 BL32 (Secure-EL1 Payload) image initialization 603^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 604 605If a BL32 image is present then there must be a matching Secure-EL1 Payload 606Dispatcher (SPD) service (see later for details). During initialization 607that service must register a function to carry out initialization of BL32 608once the runtime services are fully initialized. BL31 invokes such a 609registered function to initialize BL32 before running BL33. This initialization 610is not necessary for AArch32 SPs. 611 612Details on BL32 initialization and the SPD's role are described in the 613:ref:`firmware_design_sel1_spd` section below. 614 615BL33 (Non-trusted Firmware) execution 616^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 617 618EL3 Runtime Software initializes the EL2 or EL1 processor context for normal- 619world cold boot, ensuring that no secure state information finds its way into 620the non-secure execution state. EL3 Runtime Software uses the entrypoint 621information provided by BL2 to jump to the Non-trusted firmware image (BL33) 622at the highest available Exception Level (EL2 if available, otherwise EL1). 623 624Using alternative Trusted Boot Firmware in place of BL1 & BL2 (AArch64 only) 625~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 626 627Some platforms have existing implementations of Trusted Boot Firmware that 628would like to use TF-A BL31 for the EL3 Runtime Software. To enable this 629firmware architecture it is important to provide a fully documented and stable 630interface between the Trusted Boot Firmware and BL31. 631 632Future changes to the BL31 interface will be done in a backwards compatible 633way, and this enables these firmware components to be independently enhanced/ 634updated to develop and exploit new functionality. 635 636Required CPU state when calling ``bl31_entrypoint()`` during cold boot 637^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 638 639This function must only be called by the primary CPU. 640 641On entry to this function the calling primary CPU must be executing in AArch64 642EL3, little-endian data access, and all interrupt sources masked: 643 644:: 645 646 PSTATE.EL = 3 647 PSTATE.RW = 1 648 PSTATE.DAIF = 0xf 649 SCTLR_EL3.EE = 0 650 651X0 and X1 can be used to pass information from the Trusted Boot Firmware to the 652platform code in BL31: 653 654:: 655 656 X0 : Reserved for common TF-A information 657 X1 : Platform specific information 658 659BL31 zero-init sections (e.g. ``.bss``) should not contain valid data on entry, 660these will be zero filled prior to invoking platform setup code. 661 662Use of the X0 and X1 parameters 663''''''''''''''''''''''''''''''' 664 665The parameters are platform specific and passed from ``bl31_entrypoint()`` to 666``bl31_early_platform_setup()``. The value of these parameters is never directly 667used by the common BL31 code. 668 669The convention is that ``X0`` conveys information regarding the BL31, BL32 and 670BL33 images from the Trusted Boot firmware and ``X1`` can be used for other 671platform specific purpose. This convention allows platforms which use TF-A's 672BL1 and BL2 images to transfer additional platform specific information from 673Secure Boot without conflicting with future evolution of TF-A using ``X0`` to 674pass a ``bl31_params`` structure. 675 676BL31 common and SPD initialization code depends on image and entrypoint 677information about BL33 and BL32, which is provided via BL31 platform APIs. 678This information is required until the start of execution of BL33. This 679information can be provided in a platform defined manner, e.g. compiled into 680the platform code in BL31, or provided in a platform defined memory location 681by the Trusted Boot firmware, or passed from the Trusted Boot Firmware via the 682Cold boot Initialization parameters. This data may need to be cleaned out of 683the CPU caches if it is provided by an earlier boot stage and then accessed by 684BL31 platform code before the caches are enabled. 685 686TF-A's BL2 implementation passes a ``bl31_params`` structure in 687``X0`` and the Arm development platforms interpret this in the BL31 platform 688code. 689 690MMU, Data caches & Coherency 691'''''''''''''''''''''''''''' 692 693BL31 does not depend on the enabled state of the MMU, data caches or 694interconnect coherency on entry to ``bl31_entrypoint()``. If these are disabled 695on entry, these should be enabled during ``bl31_plat_arch_setup()``. 696 697Data structures used in the BL31 cold boot interface 698'''''''''''''''''''''''''''''''''''''''''''''''''''' 699 700These structures are designed to support compatibility and independent 701evolution of the structures and the firmware images. For example, a version of 702BL31 that can interpret the BL3x image information from different versions of 703BL2, a platform that uses an extended entry_point_info structure to convey 704additional register information to BL31, or a ELF image loader that can convey 705more details about the firmware images. 706 707To support these scenarios the structures are versioned and sized, which enables 708BL31 to detect which information is present and respond appropriately. The 709``param_header`` is defined to capture this information: 710 711.. code:: c 712 713 typedef struct param_header { 714 uint8_t type; /* type of the structure */ 715 uint8_t version; /* version of this structure */ 716 uint16_t size; /* size of this structure in bytes */ 717 uint32_t attr; /* attributes: unused bits SBZ */ 718 } param_header_t; 719 720The structures using this format are ``entry_point_info``, ``image_info`` and 721``bl31_params``. The code that allocates and populates these structures must set 722the header fields appropriately, and the ``SET_PARAM_HEAD()`` a macro is defined 723to simplify this action. 724 725Required CPU state for BL31 Warm boot initialization 726^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 727 728When requesting a CPU power-on, or suspending a running CPU, TF-A provides 729the platform power management code with a Warm boot initialization 730entry-point, to be invoked by the CPU immediately after the reset handler. 731On entry to the Warm boot initialization function the calling CPU must be in 732AArch64 EL3, little-endian data access and all interrupt sources masked: 733 734:: 735 736 PSTATE.EL = 3 737 PSTATE.RW = 1 738 PSTATE.DAIF = 0xf 739 SCTLR_EL3.EE = 0 740 741The PSCI implementation will initialize the processor state and ensure that the 742platform power management code is then invoked as required to initialize all 743necessary system, cluster and CPU resources. 744 745AArch32 EL3 Runtime Software entrypoint interface 746~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 747 748To enable this firmware architecture it is important to provide a fully 749documented and stable interface between the Trusted Boot Firmware and the 750AArch32 EL3 Runtime Software. 751 752Future changes to the entrypoint interface will be done in a backwards 753compatible way, and this enables these firmware components to be independently 754enhanced/updated to develop and exploit new functionality. 755 756Required CPU state when entering during cold boot 757^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 758 759This function must only be called by the primary CPU. 760 761On entry to this function the calling primary CPU must be executing in AArch32 762EL3, little-endian data access, and all interrupt sources masked: 763 764:: 765 766 PSTATE.AIF = 0x7 767 SCTLR.EE = 0 768 769R0 and R1 are used to pass information from the Trusted Boot Firmware to the 770platform code in AArch32 EL3 Runtime Software: 771 772:: 773 774 R0 : Reserved for common TF-A information 775 R1 : Platform specific information 776 777Use of the R0 and R1 parameters 778''''''''''''''''''''''''''''''' 779 780The parameters are platform specific and the convention is that ``R0`` conveys 781information regarding the BL3x images from the Trusted Boot firmware and ``R1`` 782can be used for other platform specific purpose. This convention allows 783platforms which use TF-A's BL1 and BL2 images to transfer additional platform 784specific information from Secure Boot without conflicting with future 785evolution of TF-A using ``R0`` to pass a ``bl_params`` structure. 786 787The AArch32 EL3 Runtime Software is responsible for entry into BL33. This 788information can be obtained in a platform defined manner, e.g. compiled into 789the AArch32 EL3 Runtime Software, or provided in a platform defined memory 790location by the Trusted Boot firmware, or passed from the Trusted Boot Firmware 791via the Cold boot Initialization parameters. This data may need to be cleaned 792out of the CPU caches if it is provided by an earlier boot stage and then 793accessed by AArch32 EL3 Runtime Software before the caches are enabled. 794 795When using AArch32 EL3 Runtime Software, the Arm development platforms pass a 796``bl_params`` structure in ``R0`` from BL2 to be interpreted by AArch32 EL3 Runtime 797Software platform code. 798 799MMU, Data caches & Coherency 800'''''''''''''''''''''''''''' 801 802AArch32 EL3 Runtime Software must not depend on the enabled state of the MMU, 803data caches or interconnect coherency in its entrypoint. They must be explicitly 804enabled if required. 805 806Data structures used in cold boot interface 807''''''''''''''''''''''''''''''''''''''''''' 808 809The AArch32 EL3 Runtime Software cold boot interface uses ``bl_params`` instead 810of ``bl31_params``. The ``bl_params`` structure is based on the convention 811described in AArch64 BL31 cold boot interface section. 812 813Required CPU state for warm boot initialization 814^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 815 816When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3 817Runtime Software must ensure execution of a warm boot initialization entrypoint. 818If TF-A BL1 is used and the PROGRAMMABLE_RESET_ADDRESS build flag is false, 819then AArch32 EL3 Runtime Software must ensure that BL1 branches to the warm 820boot entrypoint by arranging for the BL1 platform function, 821plat_get_my_entrypoint(), to return a non-zero value. 822 823In this case, the warm boot entrypoint must be in AArch32 EL3, little-endian 824data access and all interrupt sources masked: 825 826:: 827 828 PSTATE.AIF = 0x7 829 SCTLR.EE = 0 830 831The warm boot entrypoint may be implemented by using TF-A 832``psci_warmboot_entrypoint()`` function. In that case, the platform must fulfil 833the pre-requisites mentioned in the 834:ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`. 835 836EL3 runtime services framework 837------------------------------ 838 839Software executing in the non-secure state and in the secure state at exception 840levels lower than EL3 will request runtime services using the Secure Monitor 841Call (SMC) instruction. These requests will follow the convention described in 842the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function 843identifiers to each SMC request and describes how arguments are passed and 844returned. 845 846The EL3 runtime services framework enables the development of services by 847different providers that can be easily integrated into final product firmware. 848The following sections describe the framework which facilitates the 849registration, initialization and use of runtime services in EL3 Runtime 850Software (BL31). 851 852The design of the runtime services depends heavily on the concepts and 853definitions described in the `SMCCC`_, in particular SMC Function IDs, Owning 854Entity Numbers (OEN), Fast and Yielding calls, and the SMC32 and SMC64 calling 855conventions. Please refer to that document for more detailed explanation of 856these terms. 857 858The following runtime services are expected to be implemented first. They have 859not all been instantiated in the current implementation. 860 861#. Standard service calls 862 863 This service is for management of the entire system. The Power State 864 Coordination Interface (`PSCI`_) is the first set of standard service calls 865 defined by Arm (see PSCI section later). 866 867#. Secure-EL1 Payload Dispatcher service 868 869 If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then 870 it also requires a *Secure Monitor* at EL3 to switch the EL1 processor 871 context between the normal world (EL1/EL2) and trusted world (Secure-EL1). 872 The Secure Monitor will make these world switches in response to SMCs. The 873 `SMCCC`_ provides for such SMCs with the Trusted OS Call and Trusted 874 Application Call OEN ranges. 875 876 The interface between the EL3 Runtime Software and the Secure-EL1 Payload is 877 not defined by the `SMCCC`_ or any other standard. As a result, each 878 Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime 879 service - within TF-A this service is referred to as the Secure-EL1 Payload 880 Dispatcher (SPD). 881 882 TF-A provides a Test Secure-EL1 Payload (TSP) and its associated Dispatcher 883 (TSPD). Details of SPD design and TSP/TSPD operation are described in the 884 :ref:`firmware_design_sel1_spd` section below. 885 886#. CPU implementation service 887 888 This service will provide an interface to CPU implementation specific 889 services for a given platform e.g. access to processor errata workarounds. 890 This service is currently unimplemented. 891 892Additional services for Arm Architecture, SiP and OEM calls can be implemented. 893Each implemented service handles a range of SMC function identifiers as 894described in the `SMCCC`_. 895 896Registration 897~~~~~~~~~~~~ 898 899A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying 900the name of the service, the range of OENs covered, the type of service and 901initialization and call handler functions. This macro instantiates a ``const struct rt_svc_desc`` for the service with these details (see ``runtime_svc.h``). 902This structure is allocated in a special ELF section ``.rt_svc_descs``, enabling 903the framework to find all service descriptors included into BL31. 904 905The specific service for a SMC Function is selected based on the OEN and call 906type of the Function ID, and the framework uses that information in the service 907descriptor to identify the handler for the SMC Call. 908 909The service descriptors do not include information to identify the precise set 910of SMC function identifiers supported by this service implementation, the 911security state from which such calls are valid nor the capability to support 91264-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately 913to these aspects of a SMC call is the responsibility of the service 914implementation, the framework is focused on integration of services from 915different providers and minimizing the time taken by the framework before the 916service handler is invoked. 917 918Details of the parameters, requirements and behavior of the initialization and 919call handling functions are provided in the following sections. 920 921Initialization 922~~~~~~~~~~~~~~ 923 924``runtime_svc_init()`` in ``runtime_svc.c`` initializes the runtime services 925framework running on the primary CPU during cold boot as part of the BL31 926initialization. This happens prior to initializing a Trusted OS and running 927Normal world boot firmware that might in turn use these services. 928Initialization involves validating each of the declared runtime service 929descriptors, calling the service initialization function and populating the 930index used for runtime lookup of the service. 931 932The BL31 linker script collects all of the declared service descriptors into a 933single array and defines symbols that allow the framework to locate and traverse 934the array, and determine its size. 935 936The framework does basic validation of each descriptor to halt firmware 937initialization if service declaration errors are detected. The framework does 938not check descriptors for the following error conditions, and may behave in an 939unpredictable manner under such scenarios: 940 941#. Overlapping OEN ranges 942#. Multiple descriptors for the same range of OENs and ``call_type`` 943#. Incorrect range of owning entity numbers for a given ``call_type`` 944 945Once validated, the service ``init()`` callback is invoked. This function carries 946out any essential EL3 initialization before servicing requests. The ``init()`` 947function is only invoked on the primary CPU during cold boot. If the service 948uses per-CPU data this must either be initialized for all CPUs during this call, 949or be done lazily when a CPU first issues an SMC call to that service. If 950``init()`` returns anything other than ``0``, this is treated as an initialization 951error and the service is ignored: this does not cause the firmware to halt. 952 953The OEN and call type fields present in the SMC Function ID cover a total of 954128 distinct services, but in practice a single descriptor can cover a range of 955OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a 956service handler, the framework uses an array of 128 indices that map every 957distinct OEN/call-type combination either to one of the declared services or to 958indicate the service is not handled. This ``rt_svc_descs_indices[]`` array is 959populated for all of the OENs covered by a service after the service ``init()`` 960function has reported success. So a service that fails to initialize will never 961have it's ``handle()`` function invoked. 962 963The following figure shows how the ``rt_svc_descs_indices[]`` index maps the SMC 964Function ID call type and OEN onto a specific service handler in the 965``rt_svc_descs[]`` array. 966 967|Image 1| 968 969.. _handling-an-smc: 970 971Handling an SMC 972~~~~~~~~~~~~~~~ 973 974When the EL3 runtime services framework receives a Secure Monitor Call, the SMC 975Function ID is passed in W0 from the lower exception level (as per the 976`SMCCC`_). If the calling register width is AArch32, it is invalid to invoke an 977SMC Function which indicates the SMC64 calling convention: such calls are 978ignored and return the Unknown SMC Function Identifier result code ``0xFFFFFFFF`` 979in R0/X0. 980 981Bit[31] (fast/yielding call) and bits[29:24] (owning entity number) of the SMC 982Function ID are combined to index into the ``rt_svc_descs_indices[]`` array. The 983resulting value might indicate a service that has no handler, in this case the 984framework will also report an Unknown SMC Function ID. Otherwise, the value is 985used as a further index into the ``rt_svc_descs[]`` array to locate the required 986service and handler. 987 988The service's ``handle()`` callback is provided with five of the SMC parameters 989directly, the others are saved into memory for retrieval (if needed) by the 990handler. The handler is also provided with an opaque ``handle`` for use with the 991supporting library for parameter retrieval, setting return values and context 992manipulation. The ``flags`` parameter indicates the security state of the caller 993and the state of the SVE hint bit per the SMCCCv1.3. The framework finally sets 994up the execution stack for the handler, and invokes the services ``handle()`` 995function. 996 997On return from the handler the result registers are populated in X0-X7 as needed 998before restoring the stack and CPU state and returning from the original SMC. 999 1000Exception Handling Framework 1001---------------------------- 1002 1003Please refer to the :ref:`Exception Handling Framework` document. 1004 1005Power State Coordination Interface 1006---------------------------------- 1007 1008TODO: Provide design walkthrough of PSCI implementation. 1009 1010The PSCI v1.1 specification categorizes APIs as optional and mandatory. All the 1011mandatory APIs in PSCI v1.1, PSCI v1.0 and in PSCI v0.2 draft specification 1012`Power State Coordination Interface PDD`_ are implemented. The table lists 1013the PSCI v1.1 APIs and their support in generic code. 1014 1015An API implementation might have a dependency on platform code e.g. CPU_SUSPEND 1016requires the platform to export a part of the implementation. Hence the level 1017of support of the mandatory APIs depends upon the support exported by the 1018platform port as well. The Juno and FVP (all variants) platforms export all the 1019required support. 1020 1021+-----------------------------+-------------+-------------------------------+ 1022| PSCI v1.1 API | Supported | Comments | 1023+=============================+=============+===============================+ 1024| ``PSCI_VERSION`` | Yes | The version returned is 1.1 | 1025+-----------------------------+-------------+-------------------------------+ 1026| ``CPU_SUSPEND`` | Yes\* | | 1027+-----------------------------+-------------+-------------------------------+ 1028| ``CPU_OFF`` | Yes\* | | 1029+-----------------------------+-------------+-------------------------------+ 1030| ``CPU_ON`` | Yes\* | | 1031+-----------------------------+-------------+-------------------------------+ 1032| ``AFFINITY_INFO`` | Yes | | 1033+-----------------------------+-------------+-------------------------------+ 1034| ``MIGRATE`` | Yes\*\* | | 1035+-----------------------------+-------------+-------------------------------+ 1036| ``MIGRATE_INFO_TYPE`` | Yes\*\* | | 1037+-----------------------------+-------------+-------------------------------+ 1038| ``MIGRATE_INFO_CPU`` | Yes\*\* | | 1039+-----------------------------+-------------+-------------------------------+ 1040| ``SYSTEM_OFF`` | Yes\* | | 1041+-----------------------------+-------------+-------------------------------+ 1042| ``SYSTEM_RESET`` | Yes\* | | 1043+-----------------------------+-------------+-------------------------------+ 1044| ``PSCI_FEATURES`` | Yes | | 1045+-----------------------------+-------------+-------------------------------+ 1046| ``CPU_FREEZE`` | No | | 1047+-----------------------------+-------------+-------------------------------+ 1048| ``CPU_DEFAULT_SUSPEND`` | No | | 1049+-----------------------------+-------------+-------------------------------+ 1050| ``NODE_HW_STATE`` | Yes\* | | 1051+-----------------------------+-------------+-------------------------------+ 1052| ``SYSTEM_SUSPEND`` | Yes\* | | 1053+-----------------------------+-------------+-------------------------------+ 1054| ``PSCI_SET_SUSPEND_MODE`` | No | | 1055+-----------------------------+-------------+-------------------------------+ 1056| ``PSCI_STAT_RESIDENCY`` | Yes\* | | 1057+-----------------------------+-------------+-------------------------------+ 1058| ``PSCI_STAT_COUNT`` | Yes\* | | 1059+-----------------------------+-------------+-------------------------------+ 1060| ``SYSTEM_RESET2`` | Yes\* | | 1061+-----------------------------+-------------+-------------------------------+ 1062| ``MEM_PROTECT`` | Yes\* | | 1063+-----------------------------+-------------+-------------------------------+ 1064| ``MEM_PROTECT_CHECK_RANGE`` | Yes\* | | 1065+-----------------------------+-------------+-------------------------------+ 1066 1067\*Note : These PSCI APIs require platform power management hooks to be 1068registered with the generic PSCI code to be supported. 1069 1070\*\*Note : These PSCI APIs require appropriate Secure Payload Dispatcher 1071hooks to be registered with the generic PSCI code to be supported. 1072 1073The PSCI implementation in TF-A is a library which can be integrated with 1074AArch64 or AArch32 EL3 Runtime Software for Armv8-A systems. A guide to 1075integrating PSCI library with AArch32 EL3 Runtime Software can be found 1076at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`. 1077 1078.. _firmware_design_sel1_spd: 1079 1080Secure-EL1 Payloads and Dispatchers 1081----------------------------------- 1082 1083On a production system that includes a Trusted OS running in Secure-EL1/EL0, 1084the Trusted OS is coupled with a companion runtime service in the BL31 1085firmware. This service is responsible for the initialisation of the Trusted 1086OS and all communications with it. The Trusted OS is the BL32 stage of the 1087boot flow in TF-A. The firmware will attempt to locate, load and execute a 1088BL32 image. 1089 1090TF-A uses a more general term for the BL32 software that runs at Secure-EL1 - 1091the *Secure-EL1 Payload* - as it is not always a Trusted OS. 1092 1093TF-A provides a Test Secure-EL1 Payload (TSP) and a Test Secure-EL1 Payload 1094Dispatcher (TSPD) service as an example of how a Trusted OS is supported on a 1095production system using the Runtime Services Framework. On such a system, the 1096Test BL32 image and service are replaced by the Trusted OS and its dispatcher 1097service. The TF-A build system expects that the dispatcher will define the 1098build flag ``NEED_BL32`` to enable it to include the BL32 in the build either 1099as a binary or to compile from source depending on whether the ``BL32`` build 1100option is specified or not. 1101 1102The TSP runs in Secure-EL1. It is designed to demonstrate synchronous 1103communication with the normal-world software running in EL1/EL2. Communication 1104is initiated by the normal-world software 1105 1106- either directly through a Fast SMC (as defined in the `SMCCC`_) 1107 1108- or indirectly through a `PSCI`_ SMC. The `PSCI`_ implementation in turn 1109 informs the TSPD about the requested power management operation. This allows 1110 the TSP to prepare for or respond to the power state change 1111 1112The TSPD service is responsible for. 1113 1114- Initializing the TSP 1115 1116- Routing requests and responses between the secure and the non-secure 1117 states during the two types of communications just described 1118 1119Initializing a BL32 Image 1120~~~~~~~~~~~~~~~~~~~~~~~~~ 1121 1122The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing 1123the BL32 image. It needs access to the information passed by BL2 to BL31 to do 1124so. This is provided by: 1125 1126.. code:: c 1127 1128 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t); 1129 1130which returns a reference to the ``entry_point_info`` structure corresponding to 1131the image which will be run in the specified security state. The SPD uses this 1132API to get entry point information for the SECURE image, BL32. 1133 1134In the absence of a BL32 image, BL31 passes control to the normal world 1135bootloader image (BL33). When the BL32 image is present, it is typical 1136that the SPD wants control to be passed to BL32 first and then later to BL33. 1137 1138To do this the SPD has to register a BL32 initialization function during 1139initialization of the SPD service. The BL32 initialization function has this 1140prototype: 1141 1142.. code:: c 1143 1144 int32_t init(void); 1145 1146and is registered using the ``bl31_register_bl32_init()`` function. 1147 1148TF-A supports two approaches for the SPD to pass control to BL32 before 1149returning through EL3 and running the non-trusted firmware (BL33): 1150 1151#. In the BL32 setup function, use ``bl31_set_next_image_type()`` to 1152 request that the exit from ``bl31_main()`` is to the BL32 entrypoint in 1153 Secure-EL1. BL31 will exit to BL32 using the asynchronous method by 1154 calling ``bl31_prepare_next_image_entry()`` and ``el3_exit()``. 1155 1156 When the BL32 has completed initialization at Secure-EL1, it returns to 1157 BL31 by issuing an SMC, using a Function ID allocated to the SPD. On 1158 receipt of this SMC, the SPD service handler should switch the CPU context 1159 from trusted to normal world and use the ``bl31_set_next_image_type()`` and 1160 ``bl31_prepare_next_image_entry()`` functions to set up the initial return to 1161 the normal world firmware BL33. On return from the handler the framework 1162 will exit to EL2 and run BL33. 1163 1164#. The BL32 setup function registers an initialization function using 1165 ``bl31_register_bl32_init()`` which provides a SPD-defined mechanism to 1166 invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32 1167 entrypoint. 1168 1169 .. note:: 1170 The Test SPD service included with TF-A provides one implementation 1171 of such a mechanism. 1172 1173 On completion BL32 returns control to BL31 via a SMC, and on receipt the 1174 SPD service handler invokes the synchronous call return mechanism to return 1175 to the BL32 initialization function. On return from this function, 1176 ``bl31_main()`` will set up the return to the normal world firmware BL33 and 1177 continue the boot process in the normal world. 1178 1179Crash Reporting in BL31 1180----------------------- 1181 1182BL31 implements a scheme for reporting the processor state when an unhandled 1183exception is encountered. The reporting mechanism attempts to preserve all the 1184register contents and report it via a dedicated UART (PL011 console). BL31 1185reports the general purpose, EL3, Secure EL1 and some EL2 state registers. 1186 1187A dedicated per-CPU crash stack is maintained by BL31 and this is retrieved via 1188the per-CPU pointer cache. The implementation attempts to minimise the memory 1189required for this feature. The file ``crash_reporting.S`` contains the 1190implementation for crash reporting. 1191 1192The sample crash output is shown below. 1193 1194:: 1195 1196 x0 = 0x000000002a4a0000 1197 x1 = 0x0000000000000001 1198 x2 = 0x0000000000000002 1199 x3 = 0x0000000000000003 1200 x4 = 0x0000000000000004 1201 x5 = 0x0000000000000005 1202 x6 = 0x0000000000000006 1203 x7 = 0x0000000000000007 1204 x8 = 0x0000000000000008 1205 x9 = 0x0000000000000009 1206 x10 = 0x0000000000000010 1207 x11 = 0x0000000000000011 1208 x12 = 0x0000000000000012 1209 x13 = 0x0000000000000013 1210 x14 = 0x0000000000000014 1211 x15 = 0x0000000000000015 1212 x16 = 0x0000000000000016 1213 x17 = 0x0000000000000017 1214 x18 = 0x0000000000000018 1215 x19 = 0x0000000000000019 1216 x20 = 0x0000000000000020 1217 x21 = 0x0000000000000021 1218 x22 = 0x0000000000000022 1219 x23 = 0x0000000000000023 1220 x24 = 0x0000000000000024 1221 x25 = 0x0000000000000025 1222 x26 = 0x0000000000000026 1223 x27 = 0x0000000000000027 1224 x28 = 0x0000000000000028 1225 x29 = 0x0000000000000029 1226 x30 = 0x0000000088000b78 1227 scr_el3 = 0x000000000003073d 1228 sctlr_el3 = 0x00000000b0cd183f 1229 cptr_el3 = 0x0000000000000000 1230 tcr_el3 = 0x000000008080351c 1231 daif = 0x00000000000002c0 1232 mair_el3 = 0x00000000004404ff 1233 spsr_el3 = 0x0000000060000349 1234 elr_el3 = 0x0000000088000114 1235 ttbr0_el3 = 0x0000000004018201 1236 esr_el3 = 0x00000000be000000 1237 far_el3 = 0x0000000000000000 1238 spsr_el1 = 0x0000000000000000 1239 elr_el1 = 0x0000000000000000 1240 spsr_abt = 0x0000000000000000 1241 spsr_und = 0x0000000000000000 1242 spsr_irq = 0x0000000000000000 1243 spsr_fiq = 0x0000000000000000 1244 sctlr_el1 = 0x0000000030d00800 1245 actlr_el1 = 0x0000000000000000 1246 cpacr_el1 = 0x0000000000000000 1247 csselr_el1 = 0x0000000000000000 1248 sp_el1 = 0x0000000000000000 1249 esr_el1 = 0x0000000000000000 1250 ttbr0_el1 = 0x0000000000000000 1251 ttbr1_el1 = 0x0000000000000000 1252 mair_el1 = 0x0000000000000000 1253 amair_el1 = 0x0000000000000000 1254 tcr_el1 = 0x0000000000000000 1255 tpidr_el1 = 0x0000000000000000 1256 tpidr_el0 = 0x0000000000000000 1257 tpidrro_el0 = 0x0000000000000000 1258 par_el1 = 0x0000000000000000 1259 mpidr_el1 = 0x0000000080000000 1260 afsr0_el1 = 0x0000000000000000 1261 afsr1_el1 = 0x0000000000000000 1262 contextidr_el1 = 0x0000000000000000 1263 vbar_el1 = 0x0000000000000000 1264 cntp_ctl_el0 = 0x0000000000000000 1265 cntp_cval_el0 = 0x0000000000000000 1266 cntv_ctl_el0 = 0x0000000000000000 1267 cntv_cval_el0 = 0x0000000000000000 1268 cntkctl_el1 = 0x0000000000000000 1269 sp_el0 = 0x0000000004014940 1270 isr_el1 = 0x0000000000000000 1271 dacr32_el2 = 0x0000000000000000 1272 ifsr32_el2 = 0x0000000000000000 1273 icc_hppir0_el1 = 0x00000000000003ff 1274 icc_hppir1_el1 = 0x00000000000003ff 1275 icc_ctlr_el3 = 0x0000000000080400 1276 gicd_ispendr regs (Offsets 0x200-0x278) 1277 Offset Value 1278 0x200: 0x0000000000000000 1279 0x208: 0x0000000000000000 1280 0x210: 0x0000000000000000 1281 0x218: 0x0000000000000000 1282 0x220: 0x0000000000000000 1283 0x228: 0x0000000000000000 1284 0x230: 0x0000000000000000 1285 0x238: 0x0000000000000000 1286 0x240: 0x0000000000000000 1287 0x248: 0x0000000000000000 1288 0x250: 0x0000000000000000 1289 0x258: 0x0000000000000000 1290 0x260: 0x0000000000000000 1291 0x268: 0x0000000000000000 1292 0x270: 0x0000000000000000 1293 0x278: 0x0000000000000000 1294 1295Guidelines for Reset Handlers 1296----------------------------- 1297 1298TF-A implements a framework that allows CPU and platform ports to perform 1299actions very early after a CPU is released from reset in both the cold and warm 1300boot paths. This is done by calling the ``reset_handler()`` function in both 1301the BL1 and BL31 images. It in turn calls the platform and CPU specific reset 1302handling functions. 1303 1304Details for implementing a CPU specific reset handler can be found in 1305Section 8. Details for implementing a platform specific reset handler can be 1306found in the :ref:`Porting Guide` (see the ``plat_reset_handler()`` function). 1307 1308When adding functionality to a reset handler, keep in mind that if a different 1309reset handling behavior is required between the first and the subsequent 1310invocations of the reset handling code, this should be detected at runtime. 1311In other words, the reset handler should be able to detect whether an action has 1312already been performed and act as appropriate. Possible courses of actions are, 1313e.g. skip the action the second time, or undo/redo it. 1314 1315.. _configuring-secure-interrupts: 1316 1317Configuring secure interrupts 1318----------------------------- 1319 1320The GIC driver is responsible for performing initial configuration of secure 1321interrupts on the platform. To this end, the platform is expected to provide the 1322GIC driver (either GICv2 or GICv3, as selected by the platform) with the 1323interrupt configuration during the driver initialisation. 1324 1325Secure interrupt configuration are specified in an array of secure interrupt 1326properties. In this scheme, in both GICv2 and GICv3 driver data structures, the 1327``interrupt_props`` member points to an array of interrupt properties. Each 1328element of the array specifies the interrupt number and its attributes 1329(priority, group, configuration). Each element of the array shall be populated 1330by the macro ``INTR_PROP_DESC()``. The macro takes the following arguments: 1331 1332- 13-bit interrupt number, 1333 1334- 8-bit interrupt priority, 1335 1336- Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``, 1337 ``INTR_TYPE_NS``), 1338 1339- Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or 1340 ``GIC_INTR_CFG_EDGE``). 1341 1342.. _firmware_design_cpu_ops_fwk: 1343 1344CPU specific operations framework 1345--------------------------------- 1346 1347Certain aspects of the Armv8-A architecture are implementation defined, 1348that is, certain behaviours are not architecturally defined, but must be 1349defined and documented by individual processor implementations. TF-A 1350implements a framework which categorises the common implementation defined 1351behaviours and allows a processor to export its implementation of that 1352behaviour. The categories are: 1353 1354#. Processor specific reset sequence. 1355 1356#. Processor specific power down sequences. 1357 1358#. Processor specific register dumping as a part of crash reporting. 1359 1360#. Errata status reporting. 1361 1362Each of the above categories fulfils a different requirement. 1363 1364#. allows any processor specific initialization before the caches and MMU 1365 are turned on, like implementation of errata workarounds, entry into 1366 the intra-cluster coherency domain etc. 1367 1368#. allows each processor to implement the power down sequence mandated in 1369 its Technical Reference Manual (TRM). 1370 1371#. allows a processor to provide additional information to the developer 1372 in the event of a crash, for example Cortex-A53 has registers which 1373 can expose the data cache contents. 1374 1375#. allows a processor to define a function that inspects and reports the status 1376 of all errata workarounds on that processor. 1377 1378Please note that only 2. is mandated by the TRM. 1379 1380The CPU specific operations framework scales to accommodate a large number of 1381different CPUs during power down and reset handling. The platform can specify 1382any CPU optimization it wants to enable for each CPU. It can also specify 1383the CPU errata workarounds to be applied for each CPU type during reset 1384handling by defining CPU errata compile time macros. Details on these macros 1385can be found in the :ref:`Arm CPU Specific Build Macros` document. 1386 1387The CPU specific operations framework depends on the ``cpu_ops`` structure which 1388needs to be exported for each type of CPU in the platform. It is defined in 1389``include/lib/cpus/aarch64/cpu_macros.S`` and has the following fields : ``midr``, 1390``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and 1391``cpu_reg_dump()``. 1392 1393The CPU specific files in ``lib/cpus`` export a ``cpu_ops`` data structure with 1394suitable handlers for that CPU. For example, ``lib/cpus/aarch64/cortex_a53.S`` 1395exports the ``cpu_ops`` for Cortex-A53 CPU. According to the platform 1396configuration, these CPU specific files must be included in the build by 1397the platform makefile. The generic CPU specific operations framework code exists 1398in ``lib/cpus/aarch64/cpu_helpers.S``. 1399 1400CPU specific Reset Handling 1401~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1402 1403After a reset, the state of the CPU when it calls generic reset handler is: 1404MMU turned off, both instruction and data caches turned off and not part 1405of any coherency domain. 1406 1407The BL entrypoint code first invokes the ``plat_reset_handler()`` to allow 1408the platform to perform any system initialization required and any system 1409errata workarounds that needs to be applied. The ``get_cpu_ops_ptr()`` reads 1410the current CPU midr, finds the matching ``cpu_ops`` entry in the ``cpu_ops`` 1411array and returns it. Note that only the part number and implementer fields 1412in midr are used to find the matching ``cpu_ops`` entry. The ``reset_func()`` in 1413the returned ``cpu_ops`` is then invoked which executes the required reset 1414handling for that CPU and also any errata workarounds enabled by the platform. 1415This function must preserve the values of general purpose registers x20 to x29. 1416 1417Refer to Section "Guidelines for Reset Handlers" for general guidelines 1418regarding placement of code in a reset handler. 1419 1420CPU specific power down sequence 1421~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1422 1423During the BL31 initialization sequence, the pointer to the matching ``cpu_ops`` 1424entry is stored in per-CPU data by ``init_cpu_ops()`` so that it can be quickly 1425retrieved during power down sequences. 1426 1427Various CPU drivers register handlers to perform power down at certain power 1428levels for that specific CPU. The PSCI service, upon receiving a power down 1429request, determines the highest power level at which to execute power down 1430sequence for a particular CPU. It uses the ``prepare_cpu_pwr_dwn()`` function to 1431pick the right power down handler for the requested level. The function 1432retrieves ``cpu_ops`` pointer member of per-CPU data, and from that, further 1433retrieves ``cpu_pwr_down_ops`` array, and indexes into the required level. If the 1434requested power level is higher than what a CPU driver supports, the handler 1435registered for highest level is invoked. 1436 1437At runtime the platform hooks for power down are invoked by the PSCI service to 1438perform platform specific operations during a power down sequence, for example 1439turning off CCI coherency during a cluster power down. 1440 1441CPU specific register reporting during crash 1442~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1443 1444If the crash reporting is enabled in BL31, when a crash occurs, the crash 1445reporting framework calls ``do_cpu_reg_dump`` which retrieves the matching 1446``cpu_ops`` using ``get_cpu_ops_ptr()`` function. The ``cpu_reg_dump()`` in 1447``cpu_ops`` is invoked, which then returns the CPU specific register values to 1448be reported and a pointer to the ASCII list of register names in a format 1449expected by the crash reporting framework. 1450 1451.. _firmware_design_cpu_errata_reporting: 1452 1453CPU errata status reporting 1454~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1455 1456Errata workarounds for CPUs supported in TF-A are applied during both cold and 1457warm boots, shortly after reset. Individual Errata workarounds are enabled as 1458build options. Some errata workarounds have potential run-time implications; 1459therefore some are enabled by default, others not. Platform ports shall 1460override build options to enable or disable errata as appropriate. The CPU 1461drivers take care of applying errata workarounds that are enabled and applicable 1462to a given CPU. Refer to :ref:`arm_cpu_macros_errata_workarounds` for more 1463information. 1464 1465Functions in CPU drivers that apply errata workaround must follow the 1466conventions listed below. 1467 1468The errata workaround must be authored as two separate functions: 1469 1470- One that checks for errata. This function must determine whether that errata 1471 applies to the current CPU. Typically this involves matching the current 1472 CPUs revision and variant against a value that's known to be affected by the 1473 errata. If the function determines that the errata applies to this CPU, it 1474 must return ``ERRATA_APPLIES``; otherwise, it must return 1475 ``ERRATA_NOT_APPLIES``. The utility functions ``cpu_get_rev_var`` and 1476 ``cpu_rev_var_ls`` functions may come in handy for this purpose. 1477 1478For an errata identified as ``E``, the check function must be named 1479``check_errata_E``. 1480 1481This function will be invoked at different times, both from assembly and from 1482C run time. Therefore it must follow AAPCS, and must not use stack. 1483 1484- Another one that applies the errata workaround. This function would call the 1485 check function described above, and applies errata workaround if required. 1486 1487CPU drivers that apply errata workaround can optionally implement an assembly 1488function that report the status of errata workarounds pertaining to that CPU. 1489For a driver that registers the CPU, for example, ``cpux`` via ``declare_cpu_ops`` 1490macro, the errata reporting function, if it exists, must be named 1491``cpux_errata_report``. This function will always be called with MMU enabled; it 1492must follow AAPCS and may use stack. 1493 1494In a debug build of TF-A, on a CPU that comes out of reset, both BL1 and the 1495runtime firmware (BL31 in AArch64, and BL32 in AArch32) will invoke errata 1496status reporting function, if one exists, for that type of CPU. 1497 1498To report the status of each errata workaround, the function shall use the 1499assembler macro ``report_errata``, passing it: 1500 1501- The build option that enables the errata; 1502 1503- The name of the CPU: this must be the same identifier that CPU driver 1504 registered itself with, using ``declare_cpu_ops``; 1505 1506- And the errata identifier: the identifier must match what's used in the 1507 errata's check function described above. 1508 1509The errata status reporting function will be called once per CPU type/errata 1510combination during the software's active life time. 1511 1512It's expected that whenever an errata workaround is submitted to TF-A, the 1513errata reporting function is appropriately extended to report its status as 1514well. 1515 1516Reporting the status of errata workaround is for informational purpose only; it 1517has no functional significance. 1518 1519Memory layout of BL images 1520-------------------------- 1521 1522Each bootloader image can be divided in 2 parts: 1523 1524- the static contents of the image. These are data actually stored in the 1525 binary on the disk. In the ELF terminology, they are called ``PROGBITS`` 1526 sections; 1527 1528- the run-time contents of the image. These are data that don't occupy any 1529 space in the binary on the disk. The ELF binary just contains some 1530 metadata indicating where these data will be stored at run-time and the 1531 corresponding sections need to be allocated and initialized at run-time. 1532 In the ELF terminology, they are called ``NOBITS`` sections. 1533 1534All PROGBITS sections are grouped together at the beginning of the image, 1535followed by all NOBITS sections. This is true for all TF-A images and it is 1536governed by the linker scripts. This ensures that the raw binary images are 1537as small as possible. If a NOBITS section was inserted in between PROGBITS 1538sections then the resulting binary file would contain zero bytes in place of 1539this NOBITS section, making the image unnecessarily bigger. Smaller images 1540allow faster loading from the FIP to the main memory. 1541 1542For BL31, a platform can specify an alternate location for NOBITS sections 1543(other than immediately following PROGBITS sections) by setting 1544``SEPARATE_NOBITS_REGION`` to 1 and defining ``BL31_NOBITS_BASE`` and 1545``BL31_NOBITS_LIMIT``. 1546 1547Linker scripts and symbols 1548~~~~~~~~~~~~~~~~~~~~~~~~~~ 1549 1550Each bootloader stage image layout is described by its own linker script. The 1551linker scripts export some symbols into the program symbol table. Their values 1552correspond to particular addresses. TF-A code can refer to these symbols to 1553figure out the image memory layout. 1554 1555Linker symbols follow the following naming convention in TF-A. 1556 1557- ``__<SECTION>_START__`` 1558 1559 Start address of a given section named ``<SECTION>``. 1560 1561- ``__<SECTION>_END__`` 1562 1563 End address of a given section named ``<SECTION>``. If there is an alignment 1564 constraint on the section's end address then ``__<SECTION>_END__`` corresponds 1565 to the end address of the section's actual contents, rounded up to the right 1566 boundary. Refer to the value of ``__<SECTION>_UNALIGNED_END__`` to know the 1567 actual end address of the section's contents. 1568 1569- ``__<SECTION>_UNALIGNED_END__`` 1570 1571 End address of a given section named ``<SECTION>`` without any padding or 1572 rounding up due to some alignment constraint. 1573 1574- ``__<SECTION>_SIZE__`` 1575 1576 Size (in bytes) of a given section named ``<SECTION>``. If there is an 1577 alignment constraint on the section's end address then ``__<SECTION>_SIZE__`` 1578 corresponds to the size of the section's actual contents, rounded up to the 1579 right boundary. In other words, ``__<SECTION>_SIZE__ = __<SECTION>_END__ - _<SECTION>_START__``. Refer to the value of ``__<SECTION>_UNALIGNED_SIZE__`` 1580 to know the actual size of the section's contents. 1581 1582- ``__<SECTION>_UNALIGNED_SIZE__`` 1583 1584 Size (in bytes) of a given section named ``<SECTION>`` without any padding or 1585 rounding up due to some alignment constraint. In other words, 1586 ``__<SECTION>_UNALIGNED_SIZE__ = __<SECTION>_UNALIGNED_END__ - __<SECTION>_START__``. 1587 1588Some of the linker symbols are mandatory as TF-A code relies on them to be 1589defined. They are listed in the following subsections. Some of them must be 1590provided for each bootloader stage and some are specific to a given bootloader 1591stage. 1592 1593The linker scripts define some extra, optional symbols. They are not actually 1594used by any code but they help in understanding the bootloader images' memory 1595layout as they are easy to spot in the link map files. 1596 1597Common linker symbols 1598^^^^^^^^^^^^^^^^^^^^^ 1599 1600All BL images share the following requirements: 1601 1602- The BSS section must be zero-initialised before executing any C code. 1603- The coherent memory section (if enabled) must be zero-initialised as well. 1604- The MMU setup code needs to know the extents of the coherent and read-only 1605 memory regions to set the right memory attributes. When 1606 ``SEPARATE_CODE_AND_RODATA=1``, it needs to know more specifically how the 1607 read-only memory region is divided between code and data. 1608 1609The following linker symbols are defined for this purpose: 1610 1611- ``__BSS_START__`` 1612- ``__BSS_SIZE__`` 1613- ``__COHERENT_RAM_START__`` Must be aligned on a page-size boundary. 1614- ``__COHERENT_RAM_END__`` Must be aligned on a page-size boundary. 1615- ``__COHERENT_RAM_UNALIGNED_SIZE__`` 1616- ``__RO_START__`` 1617- ``__RO_END__`` 1618- ``__TEXT_START__`` 1619- ``__TEXT_END__`` 1620- ``__RODATA_START__`` 1621- ``__RODATA_END__`` 1622 1623BL1's linker symbols 1624^^^^^^^^^^^^^^^^^^^^ 1625 1626BL1 being the ROM image, it has additional requirements. BL1 resides in ROM and 1627it is entirely executed in place but it needs some read-write memory for its 1628mutable data. Its ``.data`` section (i.e. its allocated read-write data) must be 1629relocated from ROM to RAM before executing any C code. 1630 1631The following additional linker symbols are defined for BL1: 1632 1633- ``__BL1_ROM_END__`` End address of BL1's ROM contents, covering its code 1634 and ``.data`` section in ROM. 1635- ``__DATA_ROM_START__`` Start address of the ``.data`` section in ROM. Must be 1636 aligned on a 16-byte boundary. 1637- ``__DATA_RAM_START__`` Address in RAM where the ``.data`` section should be 1638 copied over. Must be aligned on a 16-byte boundary. 1639- ``__DATA_SIZE__`` Size of the ``.data`` section (in ROM or RAM). 1640- ``__BL1_RAM_START__`` Start address of BL1 read-write data. 1641- ``__BL1_RAM_END__`` End address of BL1 read-write data. 1642 1643How to choose the right base addresses for each bootloader stage image 1644~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1645 1646There is currently no support for dynamic image loading in TF-A. This means 1647that all bootloader images need to be linked against their ultimate runtime 1648locations and the base addresses of each image must be chosen carefully such 1649that images don't overlap each other in an undesired way. As the code grows, 1650the base addresses might need adjustments to cope with the new memory layout. 1651 1652The memory layout is completely specific to the platform and so there is no 1653general recipe for choosing the right base addresses for each bootloader image. 1654However, there are tools to aid in understanding the memory layout. These are 1655the link map files: ``build/<platform>/<build-type>/bl<x>/bl<x>.map``, with ``<x>`` 1656being the stage bootloader. They provide a detailed view of the memory usage of 1657each image. Among other useful information, they provide the end address of 1658each image. 1659 1660- ``bl1.map`` link map file provides ``__BL1_RAM_END__`` address. 1661- ``bl2.map`` link map file provides ``__BL2_END__`` address. 1662- ``bl31.map`` link map file provides ``__BL31_END__`` address. 1663- ``bl32.map`` link map file provides ``__BL32_END__`` address. 1664 1665For each bootloader image, the platform code must provide its start address 1666as well as a limit address that it must not overstep. The latter is used in the 1667linker scripts to check that the image doesn't grow past that address. If that 1668happens, the linker will issue a message similar to the following: 1669 1670:: 1671 1672 aarch64-none-elf-ld: BLx has exceeded its limit. 1673 1674Additionally, if the platform memory layout implies some image overlaying like 1675on FVP, BL31 and TSP need to know the limit address that their PROGBITS 1676sections must not overstep. The platform code must provide those. 1677 1678TF-A does not provide any mechanism to verify at boot time that the memory 1679to load a new image is free to prevent overwriting a previously loaded image. 1680The platform must specify the memory available in the system for all the 1681relevant BL images to be loaded. 1682 1683For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will 1684return the region defined by the platform where BL1 intends to load BL2. The 1685``load_image()`` function performs bounds check for the image size based on the 1686base and maximum image size provided by the platforms. Platforms must take 1687this behaviour into account when defining the base/size for each of the images. 1688 1689Memory layout on Arm development platforms 1690^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1691 1692The following list describes the memory layout on the Arm development platforms: 1693 1694- A 4KB page of shared memory is used for communication between Trusted 1695 Firmware and the platform's power controller. This is located at the base of 1696 Trusted SRAM. The amount of Trusted SRAM available to load the bootloader 1697 images is reduced by the size of the shared memory. 1698 1699 The shared memory is used to store the CPUs' entrypoint mailbox. On Juno, 1700 this is also used for the MHU payload when passing messages to and from the 1701 SCP. 1702 1703- Another 4 KB page is reserved for passing memory layout between BL1 and BL2 1704 and also the dynamic firmware configurations. 1705 1706- On FVP, BL1 is originally sitting in the Trusted ROM at address ``0x0``. On 1707 Juno, BL1 resides in flash memory at address ``0x0BEC0000``. BL1 read-write 1708 data are relocated to the top of Trusted SRAM at runtime. 1709 1710- BL2 is loaded below BL1 RW 1711 1712- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP_MIN), 1713 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will 1714 overwrite BL1 R/W data and BL2. This implies that BL1 global variables 1715 remain valid only until execution reaches the EL3 Runtime Software entry 1716 point during a cold boot. 1717 1718- On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory 1719 region and transferred to the SCP before being overwritten by EL3 Runtime 1720 Software. 1721 1722- BL32 (for AArch64) can be loaded in one of the following locations: 1723 1724 - Trusted SRAM 1725 - Trusted DRAM (FVP only) 1726 - Secure region of DRAM (top 16MB of DRAM configured by the TrustZone 1727 controller) 1728 1729 When BL32 (for AArch64) is loaded into Trusted SRAM, it is loaded below 1730 BL31. 1731 1732The location of the BL32 image will result in different memory maps. This is 1733illustrated for both FVP and Juno in the following diagrams, using the TSP as 1734an example. 1735 1736.. note:: 1737 Loading the BL32 image in TZC secured DRAM doesn't change the memory 1738 layout of the other images in Trusted SRAM. 1739 1740CONFIG section in memory layouts shown below contains: 1741 1742:: 1743 1744 +--------------------+ 1745 |bl2_mem_params_descs| 1746 |--------------------| 1747 | fw_configs | 1748 +--------------------+ 1749 1750``bl2_mem_params_descs`` contains parameters passed from BL2 to next the 1751BL image during boot. 1752 1753``fw_configs`` includes soc_fw_config, tos_fw_config, tb_fw_config and fw_config. 1754 1755**FVP with TSP in Trusted SRAM with firmware configs :** 1756(These diagrams only cover the AArch64 case) 1757 1758:: 1759 1760 DRAM 1761 0xffffffff +----------+ 1762 : : 1763 0x82100000 |----------| 1764 |HW_CONFIG | 1765 0x82000000 |----------| (non-secure) 1766 | | 1767 0x80000000 +----------+ 1768 1769 Trusted DRAM 1770 0x08000000 +----------+ 1771 |HW_CONFIG | 1772 0x07f00000 |----------| 1773 : : 1774 | | 1775 0x06000000 +----------+ 1776 1777 Trusted SRAM 1778 0x04040000 +----------+ loaded by BL2 +----------------+ 1779 | BL1 (rw) | <<<<<<<<<<<<< | | 1780 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1781 | BL2 | <<<<<<<<<<<<< | | 1782 |----------| <<<<<<<<<<<<< |----------------| 1783 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1784 | | <<<<<<<<<<<<< |----------------| 1785 | | <<<<<<<<<<<<< | BL32 | 1786 0x04003000 +----------+ +----------------+ 1787 | CONFIG | 1788 0x04001000 +----------+ 1789 | Shared | 1790 0x04000000 +----------+ 1791 1792 Trusted ROM 1793 0x04000000 +----------+ 1794 | BL1 (ro) | 1795 0x00000000 +----------+ 1796 1797**FVP with TSP in Trusted DRAM with firmware configs (default option):** 1798 1799:: 1800 1801 DRAM 1802 0xffffffff +--------------+ 1803 : : 1804 0x82100000 |--------------| 1805 | HW_CONFIG | 1806 0x82000000 |--------------| (non-secure) 1807 | | 1808 0x80000000 +--------------+ 1809 1810 Trusted DRAM 1811 0x08000000 +--------------+ 1812 | HW_CONFIG | 1813 0x07f00000 |--------------| 1814 : : 1815 | BL32 | 1816 0x06000000 +--------------+ 1817 1818 Trusted SRAM 1819 0x04040000 +--------------+ loaded by BL2 +----------------+ 1820 | BL1 (rw) | <<<<<<<<<<<<< | | 1821 |--------------| <<<<<<<<<<<<< | BL31 NOBITS | 1822 | BL2 | <<<<<<<<<<<<< | | 1823 |--------------| <<<<<<<<<<<<< |----------------| 1824 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1825 | | +----------------+ 1826 0x04003000 +--------------+ 1827 | CONFIG | 1828 0x04001000 +--------------+ 1829 | Shared | 1830 0x04000000 +--------------+ 1831 1832 Trusted ROM 1833 0x04000000 +--------------+ 1834 | BL1 (ro) | 1835 0x00000000 +--------------+ 1836 1837**FVP with TSP in TZC-Secured DRAM with firmware configs :** 1838 1839:: 1840 1841 DRAM 1842 0xffffffff +----------+ 1843 | BL32 | (secure) 1844 0xff000000 +----------+ 1845 | | 1846 0x82100000 |----------| 1847 |HW_CONFIG | 1848 0x82000000 |----------| (non-secure) 1849 | | 1850 0x80000000 +----------+ 1851 1852 Trusted DRAM 1853 0x08000000 +----------+ 1854 |HW_CONFIG | 1855 0x7f000000 |----------| 1856 : : 1857 | | 1858 0x06000000 +----------+ 1859 1860 Trusted SRAM 1861 0x04040000 +----------+ loaded by BL2 +----------------+ 1862 | BL1 (rw) | <<<<<<<<<<<<< | | 1863 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1864 | BL2 | <<<<<<<<<<<<< | | 1865 |----------| <<<<<<<<<<<<< |----------------| 1866 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1867 | | +----------------+ 1868 0x04003000 +----------+ 1869 | CONFIG | 1870 0x04001000 +----------+ 1871 | Shared | 1872 0x04000000 +----------+ 1873 1874 Trusted ROM 1875 0x04000000 +----------+ 1876 | BL1 (ro) | 1877 0x00000000 +----------+ 1878 1879**Juno with BL32 in Trusted SRAM :** 1880 1881:: 1882 1883 Flash0 1884 0x0C000000 +----------+ 1885 : : 1886 0x0BED0000 |----------| 1887 | BL1 (ro) | 1888 0x0BEC0000 |----------| 1889 : : 1890 0x08000000 +----------+ BL31 is loaded 1891 after SCP_BL2 has 1892 Trusted SRAM been sent to SCP 1893 0x04040000 +----------+ loaded by BL2 +----------------+ 1894 | BL1 (rw) | <<<<<<<<<<<<< | | 1895 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1896 | BL2 | <<<<<<<<<<<<< | | 1897 |----------| <<<<<<<<<<<<< |----------------| 1898 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 1899 | | <<<<<<<<<<<<< |----------------| 1900 | | <<<<<<<<<<<<< | BL32 | 1901 | | +----------------+ 1902 | | 1903 0x04001000 +----------+ 1904 | MHU | 1905 0x04000000 +----------+ 1906 1907**Juno with BL32 in TZC-secured DRAM :** 1908 1909:: 1910 1911 DRAM 1912 0xFFE00000 +----------+ 1913 | BL32 | (secure) 1914 0xFF000000 |----------| 1915 | | 1916 : : (non-secure) 1917 | | 1918 0x80000000 +----------+ 1919 1920 Flash0 1921 0x0C000000 +----------+ 1922 : : 1923 0x0BED0000 |----------| 1924 | BL1 (ro) | 1925 0x0BEC0000 |----------| 1926 : : 1927 0x08000000 +----------+ BL31 is loaded 1928 after SCP_BL2 has 1929 Trusted SRAM been sent to SCP 1930 0x04040000 +----------+ loaded by BL2 +----------------+ 1931 | BL1 (rw) | <<<<<<<<<<<<< | | 1932 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1933 | BL2 | <<<<<<<<<<<<< | | 1934 |----------| <<<<<<<<<<<<< |----------------| 1935 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 1936 | | +----------------+ 1937 0x04001000 +----------+ 1938 | MHU | 1939 0x04000000 +----------+ 1940 1941.. _firmware_design_fip: 1942 1943Firmware Image Package (FIP) 1944---------------------------- 1945 1946Using a Firmware Image Package (FIP) allows for packing bootloader images (and 1947potentially other payloads) into a single archive that can be loaded by TF-A 1948from non-volatile platform storage. A driver to load images from a FIP has 1949been added to the storage layer and allows a package to be read from supported 1950platform storage. A tool to create Firmware Image Packages is also provided 1951and described below. 1952 1953Firmware Image Package layout 1954~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1955 1956The FIP layout consists of a table of contents (ToC) followed by payload data. 1957The ToC itself has a header followed by one or more table entries. The ToC is 1958terminated by an end marker entry, and since the size of the ToC is 0 bytes, 1959the offset equals the total size of the FIP file. All ToC entries describe some 1960payload data that has been appended to the end of the binary package. With the 1961information provided in the ToC entry the corresponding payload data can be 1962retrieved. 1963 1964:: 1965 1966 ------------------ 1967 | ToC Header | 1968 |----------------| 1969 | ToC Entry 0 | 1970 |----------------| 1971 | ToC Entry 1 | 1972 |----------------| 1973 | ToC End Marker | 1974 |----------------| 1975 | | 1976 | Data 0 | 1977 | | 1978 |----------------| 1979 | | 1980 | Data 1 | 1981 | | 1982 ------------------ 1983 1984The ToC header and entry formats are described in the header file 1985``include/tools_share/firmware_image_package.h``. This file is used by both the 1986tool and TF-A. 1987 1988The ToC header has the following fields: 1989 1990:: 1991 1992 `name`: The name of the ToC. This is currently used to validate the header. 1993 `serial_number`: A non-zero number provided by the creation tool 1994 `flags`: Flags associated with this data. 1995 Bits 0-31: Reserved 1996 Bits 32-47: Platform defined 1997 Bits 48-63: Reserved 1998 1999A ToC entry has the following fields: 2000 2001:: 2002 2003 `uuid`: All files are referred to by a pre-defined Universally Unique 2004 IDentifier [UUID] . The UUIDs are defined in 2005 `include/tools_share/firmware_image_package.h`. The platform translates 2006 the requested image name into the corresponding UUID when accessing the 2007 package. 2008 `offset_address`: The offset address at which the corresponding payload data 2009 can be found. The offset is calculated from the ToC base address. 2010 `size`: The size of the corresponding payload data in bytes. 2011 `flags`: Flags associated with this entry. None are yet defined. 2012 2013Firmware Image Package creation tool 2014~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2015 2016The FIP creation tool can be used to pack specified images into a binary 2017package that can be loaded by TF-A from platform storage. The tool currently 2018only supports packing bootloader images. Additional image definitions can be 2019added to the tool as required. 2020 2021The tool can be found in ``tools/fiptool``. 2022 2023Loading from a Firmware Image Package (FIP) 2024~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2025 2026The Firmware Image Package (FIP) driver can load images from a binary package on 2027non-volatile platform storage. For the Arm development platforms, this is 2028currently NOR FLASH. 2029 2030Bootloader images are loaded according to the platform policy as specified by 2031the function ``plat_get_image_source()``. For the Arm development platforms, this 2032means the platform will attempt to load images from a Firmware Image Package 2033located at the start of NOR FLASH0. 2034 2035The Arm development platforms' policy is to only allow loading of a known set of 2036images. The platform policy can be modified to allow additional images. 2037 2038Use of coherent memory in TF-A 2039------------------------------ 2040 2041There might be loss of coherency when physical memory with mismatched 2042shareability, cacheability and memory attributes is accessed by multiple CPUs 2043(refer to section B2.9 of `Arm ARM`_ for more details). This possibility occurs 2044in TF-A during power up/down sequences when coherency, MMU and caches are 2045turned on/off incrementally. 2046 2047TF-A defines coherent memory as a region of memory with Device nGnRE attributes 2048in the translation tables. The translation granule size in TF-A is 4KB. This 2049is the smallest possible size of the coherent memory region. 2050 2051By default, all data structures which are susceptible to accesses with 2052mismatched attributes from various CPUs are allocated in a coherent memory 2053region (refer to section 2.1 of :ref:`Porting Guide`). The coherent memory 2054region accesses are Outer Shareable, non-cacheable and they can be accessed with 2055the Device nGnRE attributes when the MMU is turned on. Hence, at the expense of 2056at least an extra page of memory, TF-A is able to work around coherency issues 2057due to mismatched memory attributes. 2058 2059The alternative to the above approach is to allocate the susceptible data 2060structures in Normal WriteBack WriteAllocate Inner shareable memory. This 2061approach requires the data structures to be designed so that it is possible to 2062work around the issue of mismatched memory attributes by performing software 2063cache maintenance on them. 2064 2065Disabling the use of coherent memory in TF-A 2066~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2067 2068It might be desirable to avoid the cost of allocating coherent memory on 2069platforms which are memory constrained. TF-A enables inclusion of coherent 2070memory in firmware images through the build flag ``USE_COHERENT_MEM``. 2071This flag is enabled by default. It can be disabled to choose the second 2072approach described above. 2073 2074The below sections analyze the data structures allocated in the coherent memory 2075region and the changes required to allocate them in normal memory. 2076 2077Coherent memory usage in PSCI implementation 2078~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2079 2080The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain 2081tree information for state management of power domains. By default, this data 2082structure is allocated in the coherent memory region in TF-A because it can be 2083accessed by multiple CPUs, either with caches enabled or disabled. 2084 2085.. code:: c 2086 2087 typedef struct non_cpu_pwr_domain_node { 2088 /* 2089 * Index of the first CPU power domain node level 0 which has this node 2090 * as its parent. 2091 */ 2092 unsigned int cpu_start_idx; 2093 2094 /* 2095 * Number of CPU power domains which are siblings of the domain indexed 2096 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx 2097 * -> cpu_start_idx + ncpus' have this node as their parent. 2098 */ 2099 unsigned int ncpus; 2100 2101 /* 2102 * Index of the parent power domain node. 2103 */ 2104 unsigned int parent_node; 2105 2106 plat_local_state_t local_state; 2107 2108 unsigned char level; 2109 2110 /* For indexing the psci_lock array*/ 2111 unsigned char lock_index; 2112 } non_cpu_pd_node_t; 2113 2114In order to move this data structure to normal memory, the use of each of its 2115fields must be analyzed. Fields like ``cpu_start_idx``, ``ncpus``, ``parent_node`` 2116``level`` and ``lock_index`` are only written once during cold boot. Hence removing 2117them from coherent memory involves only doing a clean and invalidate of the 2118cache lines after these fields are written. 2119 2120The field ``local_state`` can be concurrently accessed by multiple CPUs in 2121different cache states. A Lamport's Bakery lock ``psci_locks`` is used to ensure 2122mutual exclusion to this field and a clean and invalidate is needed after it 2123is written. 2124 2125Bakery lock data 2126~~~~~~~~~~~~~~~~ 2127 2128The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory 2129and is accessed by multiple CPUs with mismatched attributes. ``bakery_lock_t`` is 2130defined as follows: 2131 2132.. code:: c 2133 2134 typedef struct bakery_lock { 2135 /* 2136 * The lock_data is a bit-field of 2 members: 2137 * Bit[0] : choosing. This field is set when the CPU is 2138 * choosing its bakery number. 2139 * Bits[1 - 15] : number. This is the bakery number allocated. 2140 */ 2141 volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS]; 2142 } bakery_lock_t; 2143 2144It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU 2145fields can be read by all CPUs but only written to by the owning CPU. 2146 2147Depending upon the data cache line size, the per-CPU fields of the 2148``bakery_lock_t`` structure for multiple CPUs may exist on a single cache line. 2149These per-CPU fields can be read and written during lock contention by multiple 2150CPUs with mismatched memory attributes. Since these fields are a part of the 2151lock implementation, they do not have access to any other locking primitive to 2152safeguard against the resulting coherency issues. As a result, simple software 2153cache maintenance is not enough to allocate them in coherent memory. Consider 2154the following example. 2155 2156CPU0 updates its per-CPU field with data cache enabled. This write updates a 2157local cache line which contains a copy of the fields for other CPUs as well. Now 2158CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache 2159disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of 2160its field in any other cache line in the system. This operation will invalidate 2161the update made by CPU0 as well. 2162 2163To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure 2164has been redesigned. The changes utilise the characteristic of Lamport's Bakery 2165algorithm mentioned earlier. The bakery_lock structure only allocates the memory 2166for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks 2167needed for a CPU into a section ``.bakery_lock``. The linker allocates the memory 2168for other cores by using the total size allocated for the bakery_lock section 2169and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to 2170perform software cache maintenance on the lock data structure without running 2171into coherency issues associated with mismatched attributes. 2172 2173The bakery lock data structure ``bakery_info_t`` is defined for use when 2174``USE_COHERENT_MEM`` is disabled as follows: 2175 2176.. code:: c 2177 2178 typedef struct bakery_info { 2179 /* 2180 * The lock_data is a bit-field of 2 members: 2181 * Bit[0] : choosing. This field is set when the CPU is 2182 * choosing its bakery number. 2183 * Bits[1 - 15] : number. This is the bakery number allocated. 2184 */ 2185 volatile uint16_t lock_data; 2186 } bakery_info_t; 2187 2188The ``bakery_info_t`` represents a single per-CPU field of one lock and 2189the combination of corresponding ``bakery_info_t`` structures for all CPUs in the 2190system represents the complete bakery lock. The view in memory for a system 2191with n bakery locks are: 2192 2193:: 2194 2195 .bakery_lock section start 2196 |----------------| 2197 | `bakery_info_t`| <-- Lock_0 per-CPU field 2198 | Lock_0 | for CPU0 2199 |----------------| 2200 | `bakery_info_t`| <-- Lock_1 per-CPU field 2201 | Lock_1 | for CPU0 2202 |----------------| 2203 | .... | 2204 |----------------| 2205 | `bakery_info_t`| <-- Lock_N per-CPU field 2206 | Lock_N | for CPU0 2207 ------------------ 2208 | XXXXX | 2209 | Padding to | 2210 | next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate 2211 | Granule | continuous memory for remaining CPUs. 2212 ------------------ 2213 | `bakery_info_t`| <-- Lock_0 per-CPU field 2214 | Lock_0 | for CPU1 2215 |----------------| 2216 | `bakery_info_t`| <-- Lock_1 per-CPU field 2217 | Lock_1 | for CPU1 2218 |----------------| 2219 | .... | 2220 |----------------| 2221 | `bakery_info_t`| <-- Lock_N per-CPU field 2222 | Lock_N | for CPU1 2223 ------------------ 2224 | XXXXX | 2225 | Padding to | 2226 | next Cache WB | 2227 | Granule | 2228 ------------------ 2229 2230Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an 2231operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1 2232``.bakery_lock`` section need to be fetched and appropriate cache operations need 2233to be performed for each access. 2234 2235On Arm Platforms, bakery locks are used in psci (``psci_locks``) and power controller 2236driver (``arm_lock``). 2237 2238Non Functional Impact of removing coherent memory 2239~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2240 2241Removal of the coherent memory region leads to the additional software overhead 2242of performing cache maintenance for the affected data structures. However, since 2243the memory where the data structures are allocated is cacheable, the overhead is 2244mostly mitigated by an increase in performance. 2245 2246There is however a performance impact for bakery locks, due to: 2247 2248- Additional cache maintenance operations, and 2249- Multiple cache line reads for each lock operation, since the bakery locks 2250 for each CPU are distributed across different cache lines. 2251 2252The implementation has been optimized to minimize this additional overhead. 2253Measurements indicate that when bakery locks are allocated in Normal memory, the 2254minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas 2255in Device memory the same is 2 micro seconds. The measurements were done on the 2256Juno Arm development platform. 2257 2258As mentioned earlier, almost a page of memory can be saved by disabling 2259``USE_COHERENT_MEM``. Each platform needs to consider these trade-offs to decide 2260whether coherent memory should be used. If a platform disables 2261``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can 2262optionally define macro ``PLAT_PERCPU_BAKERY_LOCK_SIZE`` (see the 2263:ref:`Porting Guide`). Refer to the reference platform code for examples. 2264 2265Isolating code and read-only data on separate memory pages 2266---------------------------------------------------------- 2267 2268In the Armv8-A VMSA, translation table entries include fields that define the 2269properties of the target memory region, such as its access permissions. The 2270smallest unit of memory that can be addressed by a translation table entry is 2271a memory page. Therefore, if software needs to set different permissions on two 2272memory regions then it needs to map them using different memory pages. 2273 2274The default memory layout for each BL image is as follows: 2275 2276:: 2277 2278 | ... | 2279 +-------------------+ 2280 | Read-write data | 2281 +-------------------+ Page boundary 2282 | <Padding> | 2283 +-------------------+ 2284 | Exception vectors | 2285 +-------------------+ 2 KB boundary 2286 | <Padding> | 2287 +-------------------+ 2288 | Read-only data | 2289 +-------------------+ 2290 | Code | 2291 +-------------------+ BLx_BASE 2292 2293.. note:: 2294 The 2KB alignment for the exception vectors is an architectural 2295 requirement. 2296 2297The read-write data start on a new memory page so that they can be mapped with 2298read-write permissions, whereas the code and read-only data below are configured 2299as read-only. 2300 2301However, the read-only data are not aligned on a page boundary. They are 2302contiguous to the code. Therefore, the end of the code section and the beginning 2303of the read-only data one might share a memory page. This forces both to be 2304mapped with the same memory attributes. As the code needs to be executable, this 2305means that the read-only data stored on the same memory page as the code are 2306executable as well. This could potentially be exploited as part of a security 2307attack. 2308 2309TF provides the build flag ``SEPARATE_CODE_AND_RODATA`` to isolate the code and 2310read-only data on separate memory pages. This in turn allows independent control 2311of the access permissions for the code and read-only data. In this case, 2312platform code gets a finer-grained view of the image layout and can 2313appropriately map the code region as executable and the read-only data as 2314execute-never. 2315 2316This has an impact on memory footprint, as padding bytes need to be introduced 2317between the code and read-only data to ensure the segregation of the two. To 2318limit the memory cost, this flag also changes the memory layout such that the 2319code and exception vectors are now contiguous, like so: 2320 2321:: 2322 2323 | ... | 2324 +-------------------+ 2325 | Read-write data | 2326 +-------------------+ Page boundary 2327 | <Padding> | 2328 +-------------------+ 2329 | Read-only data | 2330 +-------------------+ Page boundary 2331 | <Padding> | 2332 +-------------------+ 2333 | Exception vectors | 2334 +-------------------+ 2 KB boundary 2335 | <Padding> | 2336 +-------------------+ 2337 | Code | 2338 +-------------------+ BLx_BASE 2339 2340With this more condensed memory layout, the separation of read-only data will 2341add zero or one page to the memory footprint of each BL image. Each platform 2342should consider the trade-off between memory footprint and security. 2343 2344This build flag is disabled by default, minimising memory footprint. On Arm 2345platforms, it is enabled. 2346 2347Publish and Subscribe Framework 2348------------------------------- 2349 2350The Publish and Subscribe Framework allows EL3 components to define and publish 2351events, to which other EL3 components can subscribe. 2352 2353The following macros are provided by the framework: 2354 2355- ``REGISTER_PUBSUB_EVENT(event)``: Defines an event, and takes one argument, 2356 the event name, which must be a valid C identifier. All calls to 2357 ``REGISTER_PUBSUB_EVENT`` macro must be placed in the file 2358 ``pubsub_events.h``. 2359 2360- ``PUBLISH_EVENT_ARG(event, arg)``: Publishes a defined event, by iterating 2361 subscribed handlers and calling them in turn. The handlers will be passed the 2362 parameter ``arg``. The expected use-case is to broadcast an event. 2363 2364- ``PUBLISH_EVENT(event)``: Like ``PUBLISH_EVENT_ARG``, except that the value 2365 ``NULL`` is passed to subscribed handlers. 2366 2367- ``SUBSCRIBE_TO_EVENT(event, handler)``: Registers the ``handler`` to 2368 subscribe to ``event``. The handler will be executed whenever the ``event`` 2369 is published. 2370 2371- ``for_each_subscriber(event, subscriber)``: Iterates through all handlers 2372 subscribed for ``event``. ``subscriber`` must be a local variable of type 2373 ``pubsub_cb_t *``, and will point to each subscribed handler in turn during 2374 iteration. This macro can be used for those patterns that none of the 2375 ``PUBLISH_EVENT_*()`` macros cover. 2376 2377Publishing an event that wasn't defined using ``REGISTER_PUBSUB_EVENT`` will 2378result in build error. Subscribing to an undefined event however won't. 2379 2380Subscribed handlers must be of type ``pubsub_cb_t``, with following function 2381signature: 2382 2383.. code:: c 2384 2385 typedef void* (*pubsub_cb_t)(const void *arg); 2386 2387There may be arbitrary number of handlers registered to the same event. The 2388order in which subscribed handlers are notified when that event is published is 2389not defined. Subscribed handlers may be executed in any order; handlers should 2390not assume any relative ordering amongst them. 2391 2392Publishing an event on a PE will result in subscribed handlers executing on that 2393PE only; it won't cause handlers to execute on a different PE. 2394 2395Note that publishing an event on a PE blocks until all the subscribed handlers 2396finish executing on the PE. 2397 2398TF-A generic code publishes and subscribes to some events within. Platform 2399ports are discouraged from subscribing to them. These events may be withdrawn, 2400renamed, or have their semantics altered in the future. Platforms may however 2401register, publish, and subscribe to platform-specific events. 2402 2403Publish and Subscribe Example 2404~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2405 2406A publisher that wants to publish event ``foo`` would: 2407 2408- Define the event ``foo`` in the ``pubsub_events.h``. 2409 2410 .. code:: c 2411 2412 REGISTER_PUBSUB_EVENT(foo); 2413 2414- Depending on the nature of event, use one of ``PUBLISH_EVENT_*()`` macros to 2415 publish the event at the appropriate path and time of execution. 2416 2417A subscriber that wants to subscribe to event ``foo`` published above would 2418implement: 2419 2420.. code:: c 2421 2422 void *foo_handler(const void *arg) 2423 { 2424 void *result; 2425 2426 /* Do handling ... */ 2427 2428 return result; 2429 } 2430 2431 SUBSCRIBE_TO_EVENT(foo, foo_handler); 2432 2433 2434Reclaiming the BL31 initialization code 2435~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2436 2437A significant amount of the code used for the initialization of BL31 is never 2438needed again after boot time. In order to reduce the runtime memory 2439footprint, the memory used for this code can be reclaimed after initialization 2440has finished and be used for runtime data. 2441 2442The build option ``RECLAIM_INIT_CODE`` can be set to mark this boot time code 2443with a ``.text.init.*`` attribute which can be filtered and placed suitably 2444within the BL image for later reclamation by the platform. The platform can 2445specify the filter and the memory region for this init section in BL31 via the 2446plat.ld.S linker script. For example, on the FVP, this section is placed 2447overlapping the secondary CPU stacks so that after the cold boot is done, this 2448memory can be reclaimed for the stacks. The init memory section is initially 2449mapped with ``RO``, ``EXECUTE`` attributes. After BL31 initialization has 2450completed, the FVP changes the attributes of this section to ``RW``, 2451``EXECUTE_NEVER`` allowing it to be used for runtime data. The memory attributes 2452are changed within the ``bl31_plat_runtime_setup`` platform hook. The init 2453section section can be reclaimed for any data which is accessed after cold 2454boot initialization and it is upto the platform to make the decision. 2455 2456.. _firmware_design_pmf: 2457 2458Performance Measurement Framework 2459--------------------------------- 2460 2461The Performance Measurement Framework (PMF) facilitates collection of 2462timestamps by registered services and provides interfaces to retrieve them 2463from within TF-A. A platform can choose to expose appropriate SMCs to 2464retrieve these collected timestamps. 2465 2466By default, the global physical counter is used for the timestamp 2467value and is read via ``CNTPCT_EL0``. The framework allows to retrieve 2468timestamps captured by other CPUs. 2469 2470Timestamp identifier format 2471~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2472 2473A PMF timestamp is uniquely identified across the system via the 2474timestamp ID or ``tid``. The ``tid`` is composed as follows: 2475 2476:: 2477 2478 Bits 0-7: The local timestamp identifier. 2479 Bits 8-9: Reserved. 2480 Bits 10-15: The service identifier. 2481 Bits 16-31: Reserved. 2482 2483#. The service identifier. Each PMF service is identified by a 2484 service name and a service identifier. Both the service name and 2485 identifier are unique within the system as a whole. 2486 2487#. The local timestamp identifier. This identifier is unique within a given 2488 service. 2489 2490Registering a PMF service 2491~~~~~~~~~~~~~~~~~~~~~~~~~ 2492 2493To register a PMF service, the ``PMF_REGISTER_SERVICE()`` macro from ``pmf.h`` 2494is used. The arguments required are the service name, the service ID, 2495the total number of local timestamps to be captured and a set of flags. 2496 2497The ``flags`` field can be specified as a bitwise-OR of the following values: 2498 2499:: 2500 2501 PMF_STORE_ENABLE: The timestamp is stored in memory for later retrieval. 2502 PMF_DUMP_ENABLE: The timestamp is dumped on the serial console. 2503 2504The ``PMF_REGISTER_SERVICE()`` reserves memory to store captured 2505timestamps in a PMF specific linker section at build time. 2506Additionally, it defines necessary functions to capture and 2507retrieve a particular timestamp for the given service at runtime. 2508 2509The macro ``PMF_REGISTER_SERVICE()`` only enables capturing PMF timestamps 2510from within TF-A. In order to retrieve timestamps from outside of TF-A, the 2511``PMF_REGISTER_SERVICE_SMC()`` macro must be used instead. This macro 2512accepts the same set of arguments as the ``PMF_REGISTER_SERVICE()`` 2513macro but additionally supports retrieving timestamps using SMCs. 2514 2515Capturing a timestamp 2516~~~~~~~~~~~~~~~~~~~~~ 2517 2518PMF timestamps are stored in a per-service timestamp region. On a 2519system with multiple CPUs, each timestamp is captured and stored 2520in a per-CPU cache line aligned memory region. 2521 2522Having registered the service, the ``PMF_CAPTURE_TIMESTAMP()`` macro can be 2523used to capture a timestamp at the location where it is used. The macro 2524takes the service name, a local timestamp identifier and a flag as arguments. 2525 2526The ``flags`` field argument can be zero, or ``PMF_CACHE_MAINT`` which 2527instructs PMF to do cache maintenance following the capture. Cache 2528maintenance is required if any of the service's timestamps are captured 2529with data cache disabled. 2530 2531To capture a timestamp in assembly code, the caller should use 2532``pmf_calc_timestamp_addr`` macro (defined in ``pmf_asm_macros.S``) to 2533calculate the address of where the timestamp would be stored. The 2534caller should then read ``CNTPCT_EL0`` register to obtain the timestamp 2535and store it at the determined address for later retrieval. 2536 2537Retrieving a timestamp 2538~~~~~~~~~~~~~~~~~~~~~~ 2539 2540From within TF-A, timestamps for individual CPUs can be retrieved using either 2541``PMF_GET_TIMESTAMP_BY_MPIDR()`` or ``PMF_GET_TIMESTAMP_BY_INDEX()`` macros. 2542These macros accept the CPU's MPIDR value, or its ordinal position 2543respectively. 2544 2545From outside TF-A, timestamps for individual CPUs can be retrieved by calling 2546into ``pmf_smc_handler()``. 2547 2548:: 2549 2550 Interface : pmf_smc_handler() 2551 Argument : unsigned int smc_fid, u_register_t x1, 2552 u_register_t x2, u_register_t x3, 2553 u_register_t x4, void *cookie, 2554 void *handle, u_register_t flags 2555 Return : uintptr_t 2556 2557 smc_fid: Holds the SMC identifier which is either `PMF_SMC_GET_TIMESTAMP_32` 2558 when the caller of the SMC is running in AArch32 mode 2559 or `PMF_SMC_GET_TIMESTAMP_64` when the caller is running in AArch64 mode. 2560 x1: Timestamp identifier. 2561 x2: The `mpidr` of the CPU for which the timestamp has to be retrieved. 2562 This can be the `mpidr` of a different core to the one initiating 2563 the SMC. In that case, service specific cache maintenance may be 2564 required to ensure the updated copy of the timestamp is returned. 2565 x3: A flags value that is either 0 or `PMF_CACHE_MAINT`. If 2566 `PMF_CACHE_MAINT` is passed, then the PMF code will perform a 2567 cache invalidate before reading the timestamp. This ensures 2568 an updated copy is returned. 2569 2570The remaining arguments, ``x4``, ``cookie``, ``handle`` and ``flags`` are unused 2571in this implementation. 2572 2573PMF code structure 2574~~~~~~~~~~~~~~~~~~ 2575 2576#. ``pmf_main.c`` consists of core functions that implement service registration, 2577 initialization, storing, dumping and retrieving timestamps. 2578 2579#. ``pmf_smc.c`` contains the SMC handling for registered PMF services. 2580 2581#. ``pmf.h`` contains the public interface to Performance Measurement Framework. 2582 2583#. ``pmf_asm_macros.S`` consists of macros to facilitate capturing timestamps in 2584 assembly code. 2585 2586#. ``pmf_helpers.h`` is an internal header used by ``pmf.h``. 2587 2588Armv8-A Architecture Extensions 2589------------------------------- 2590 2591TF-A makes use of Armv8-A Architecture Extensions where applicable. This 2592section lists the usage of Architecture Extensions, and build flags 2593controlling them. 2594 2595In general, and unless individually mentioned, the build options 2596``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` select the Architecture Extension to 2597target when building TF-A. Subsequent Arm Architecture Extensions are backward 2598compatible with previous versions. 2599 2600The build system only requires that ``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` have a 2601valid numeric value. These build options only control whether or not 2602Architecture Extension-specific code is included in the build. Otherwise, TF-A 2603targets the base Armv8.0-A architecture; i.e. as if ``ARM_ARCH_MAJOR`` == 8 2604and ``ARM_ARCH_MINOR`` == 0, which are also their respective default values. 2605 2606.. seealso:: :ref:`Build Options` 2607 2608For details on the Architecture Extension and available features, please refer 2609to the respective Architecture Extension Supplement. 2610 2611Armv8.1-A 2612~~~~~~~~~ 2613 2614This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when 2615``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` >= 1. 2616 2617- By default, a load-/store-exclusive instruction pair is used to implement 2618 spinlocks. The ``USE_SPINLOCK_CAS`` build option when set to 1 selects the 2619 spinlock implementation using the ARMv8.1-LSE Compare and Swap instruction. 2620 Notice this instruction is only available in AArch64 execution state, so 2621 the option is only available to AArch64 builds. 2622 2623Armv8.2-A 2624~~~~~~~~~ 2625 2626- The presence of ARMv8.2-TTCNP is detected at runtime. When it is present, the 2627 Common not Private (TTBRn_ELx.CnP) bit is enabled to indicate that multiple 2628 Processing Elements in the same Inner Shareable domain use the same 2629 translation table entries for a given stage of translation for a particular 2630 translation regime. 2631 2632Armv8.3-A 2633~~~~~~~~~ 2634 2635- Pointer authentication features of Armv8.3-A are unconditionally enabled in 2636 the Non-secure world so that lower ELs are allowed to use them without 2637 causing a trap to EL3. 2638 2639 In order to enable the Secure world to use it, ``CTX_INCLUDE_PAUTH_REGS`` 2640 must be set to 1. This will add all pointer authentication system registers 2641 to the context that is saved when doing a world switch. 2642 2643 The TF-A itself has support for pointer authentication at runtime 2644 that can be enabled by setting ``BRANCH_PROTECTION`` option to non-zero and 2645 ``CTX_INCLUDE_PAUTH_REGS`` to 1. This enables pointer authentication in BL1, 2646 BL2, BL31, and the TSP if it is used. 2647 2648 Note that Pointer Authentication is enabled for Non-secure world irrespective 2649 of the value of these build flags if the CPU supports it. 2650 2651 If ``ARM_ARCH_MAJOR == 8`` and ``ARM_ARCH_MINOR >= 3`` the code footprint of 2652 enabling PAuth is lower because the compiler will use the optimized 2653 PAuth instructions rather than the backwards-compatible ones. 2654 2655Armv8.5-A 2656~~~~~~~~~ 2657 2658- Branch Target Identification feature is selected by ``BRANCH_PROTECTION`` 2659 option set to 1. This option defaults to 0. 2660 2661- Memory Tagging Extension feature is unconditionally enabled for both worlds 2662 (at EL0 and S-EL0) if it is only supported at EL0. If instead it is 2663 implemented at all ELs, it is unconditionally enabled for only the normal 2664 world. To enable it for the secure world as well, the build option 2665 ``CTX_INCLUDE_MTE_REGS`` is required. If the hardware does not implement 2666 MTE support at all, it is always disabled, no matter what build options 2667 are used. 2668 2669Armv7-A 2670~~~~~~~ 2671 2672This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 7. 2673 2674There are several Armv7-A extensions available. Obviously the TrustZone 2675extension is mandatory to support the TF-A bootloader and runtime services. 2676 2677Platform implementing an Armv7-A system can to define from its target 2678Cortex-A architecture through ``ARM_CORTEX_A<X> = yes`` in their 2679``platform.mk`` script. For example ``ARM_CORTEX_A15=yes`` for a 2680Cortex-A15 target. 2681 2682Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support. 2683Note that using neon at runtime has constraints on non secure world context. 2684TF-A does not yet provide VFP context management. 2685 2686Directive ``ARM_CORTEX_A<x>`` and ``ARM_WITH_NEON`` are used to set 2687the toolchain target architecture directive. 2688 2689Platform may choose to not define straight the toolchain target architecture 2690directive by defining ``MARCH32_DIRECTIVE``. 2691I.e: 2692 2693.. code:: make 2694 2695 MARCH32_DIRECTIVE := -mach=armv7-a 2696 2697Code Structure 2698-------------- 2699 2700TF-A code is logically divided between the three boot loader stages mentioned 2701in the previous sections. The code is also divided into the following 2702categories (present as directories in the source code): 2703 2704- **Platform specific.** Choice of architecture specific code depends upon 2705 the platform. 2706- **Common code.** This is platform and architecture agnostic code. 2707- **Library code.** This code comprises of functionality commonly used by all 2708 other code. The PSCI implementation and other EL3 runtime frameworks reside 2709 as Library components. 2710- **Stage specific.** Code specific to a boot stage. 2711- **Drivers.** 2712- **Services.** EL3 runtime services (eg: SPD). Specific SPD services 2713 reside in the ``services/spd`` directory (e.g. ``services/spd/tspd``). 2714 2715Each boot loader stage uses code from one or more of the above mentioned 2716categories. Based upon the above, the code layout looks like this: 2717 2718:: 2719 2720 Directory Used by BL1? Used by BL2? Used by BL31? 2721 bl1 Yes No No 2722 bl2 No Yes No 2723 bl31 No No Yes 2724 plat Yes Yes Yes 2725 drivers Yes No Yes 2726 common Yes Yes Yes 2727 lib Yes Yes Yes 2728 services No No Yes 2729 2730The build system provides a non configurable build option IMAGE_BLx for each 2731boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE_BL1 will be 2732defined by the build system. This enables TF-A to compile certain code only 2733for specific boot loader stages 2734 2735All assembler files have the ``.S`` extension. The linker source files for each 2736boot stage have the extension ``.ld.S``. These are processed by GCC to create the 2737linker scripts which have the extension ``.ld``. 2738 2739FDTs provide a description of the hardware platform and are used by the Linux 2740kernel at boot time. These can be found in the ``fdts`` directory. 2741 2742.. rubric:: References 2743 2744- `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D)`_ 2745 2746- `Power State Coordination Interface PDD`_ 2747 2748- `SMC Calling Convention`_ 2749 2750- :ref:`Interrupt Management Framework` 2751 2752-------------- 2753 2754*Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.* 2755 2756.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2757.. _SMCCC: https://developer.arm.com/docs/den0028/latest 2758.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2759.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2760.. _Arm ARM: https://developer.arm.com/docs/ddi0487/latest 2761.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest 2762.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a 2763.. _Arm Confidential Compute Architecture (Arm CCA): https://www.arm.com/why-arm/architecture/security-features/arm-confidential-compute-architecture 2764 2765.. |Image 1| image:: ../resources/diagrams/rt-svc-descs-layout.png 2766
