1Firmware Design 2=============== 3 4Trusted Firmware-A (TF-A) implements a subset of the Trusted Board Boot 5Requirements (TBBR) Platform Design Document (PDD) for Arm reference 6platforms. 7 8The TBB sequence starts when the platform is powered on and runs up 9to the stage where it hands-off control to firmware running in the normal 10world in DRAM. This is the cold boot path. 11 12TF-A also implements the `PSCI`_ as a runtime service. PSCI is the interface 13from normal world software to firmware implementing power management use-cases 14(for example, secondary CPU boot, hotplug and idle). Normal world software can 15access TF-A runtime services via the Arm SMC (Secure Monitor Call) instruction. 16The SMC instruction must be used as mandated by the SMC Calling Convention 17(`SMCCC`_). 18 19TF-A implements a framework for configuring and managing interrupts generated 20in either security state. The details of the interrupt management framework 21and its design can be found in :ref:`Interrupt Management Framework`. 22 23TF-A also implements a library for setting up and managing the translation 24tables. The details of this library can be found in 25:ref:`Translation (XLAT) Tables Library`. 26 27TF-A can be built to support either AArch64 or AArch32 execution state. 28 29.. note:: 30 The descriptions in this chapter are for the Arm TrustZone architecture. 31 For changes to the firmware design for the `Arm Confidential Compute 32 Architecture (Arm CCA)`_ please refer to the chapter :ref:`Realm Management 33 Extension (RME)`. 34 35Cold boot 36--------- 37 38The cold boot path starts when the platform is physically turned on. If 39``COLD_BOOT_SINGLE_CPU=0``, one of the CPUs released from reset is chosen as the 40primary CPU, and the remaining CPUs are considered secondary CPUs. The primary 41CPU is chosen through platform-specific means. The cold boot path is mainly 42executed by the primary CPU, other than essential CPU initialization executed by 43all CPUs. The secondary CPUs are kept in a safe platform-specific state until 44the primary CPU has performed enough initialization to boot them. 45 46Refer to the :ref:`CPU Reset` for more information on the effect of the 47``COLD_BOOT_SINGLE_CPU`` platform build option. 48 49The cold boot path in this implementation of TF-A depends on the execution 50state. For AArch64, it is divided into five steps (in order of execution): 51 52- Boot Loader stage 1 (BL1) *AP Trusted ROM* 53- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 54- Boot Loader stage 3-1 (BL31) *EL3 Runtime Software* 55- Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional) 56- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 57 58For AArch32, it is divided into four steps (in order of execution): 59 60- Boot Loader stage 1 (BL1) *AP Trusted ROM* 61- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 62- Boot Loader stage 3-2 (BL32) *EL3 Runtime Software* 63- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 64 65Arm development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a 66combination of the following types of memory regions. Each bootloader stage uses 67one or more of these memory regions. 68 69- Regions accessible from both non-secure and secure states. For example, 70 non-trusted SRAM, ROM and DRAM. 71- Regions accessible from only the secure state. For example, trusted SRAM and 72 ROM. The FVPs also implement the trusted DRAM which is statically 73 configured. Additionally, the Base FVPs and Juno development platform 74 configure the TrustZone Controller (TZC) to create a region in the DRAM 75 which is accessible only from the secure state. 76 77The sections below provide the following details: 78 79- dynamic configuration of Boot Loader stages 80- initialization and execution of the first three stages during cold boot 81- specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for 82 AArch32) entrypoint requirements for use by alternative Trusted Boot 83 Firmware in place of the provided BL1 and BL2 84 85Dynamic Configuration during cold boot 86~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 87 88Each of the Boot Loader stages may be dynamically configured if required by the 89platform. The Boot Loader stage may optionally specify a firmware 90configuration file and/or hardware configuration file as listed below: 91 92- FW_CONFIG - The firmware configuration file. Holds properties shared across 93 all BLx images. 94 An example is the "dtb-registry" node, which contains the information about 95 the other device tree configurations (load-address, size, image_id). 96- HW_CONFIG - The hardware configuration file. Can be shared by all Boot Loader 97 stages and also by the Normal World Rich OS. 98- TB_FW_CONFIG - Trusted Boot Firmware configuration file. Shared between BL1 99 and BL2. 100- SOC_FW_CONFIG - SoC Firmware configuration file. Used by BL31. 101- TOS_FW_CONFIG - Trusted OS Firmware configuration file. Used by Trusted OS 102 (BL32). 103- NT_FW_CONFIG - Non Trusted Firmware configuration file. Used by Non-trusted 104 firmware (BL33). 105 106The Arm development platforms use the Flattened Device Tree format for the 107dynamic configuration files. 108 109Each Boot Loader stage can pass up to 4 arguments via registers to the next 110stage. BL2 passes the list of the next images to execute to the *EL3 Runtime 111Software* (BL31 for AArch64 and BL32 for AArch32) via `arg0`. All the other 112arguments are platform defined. The Arm development platforms use the following 113convention: 114 115- BL1 passes the address of a meminfo_t structure to BL2 via ``arg1``. This 116 structure contains the memory layout available to BL2. 117- When dynamic configuration files are present, the firmware configuration for 118 the next Boot Loader stage is populated in the first available argument and 119 the generic hardware configuration is passed the next available argument. 120 For example, 121 122 - FW_CONFIG is loaded by BL1, then its address is passed in ``arg0`` to BL2. 123 - TB_FW_CONFIG address is retrieved by BL2 from FW_CONFIG device tree. 124 - If HW_CONFIG is loaded by BL1, then its address is passed in ``arg2`` to 125 BL2. Note, ``arg1`` is already used for meminfo_t. 126 - If SOC_FW_CONFIG is loaded by BL2, then its address is passed in ``arg1`` 127 to BL31. Note, ``arg0`` is used to pass the list of executable images. 128 - Similarly, if HW_CONFIG is loaded by BL1 or BL2, then its address is 129 passed in ``arg2`` to BL31. 130 - For other BL3x images, if the firmware configuration file is loaded by 131 BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded 132 then its address is passed in ``arg1``. 133 - In case SPMC_AT_EL3 is enabled, populate the BL32 image base, size and max 134 limit in the entry point information, since there is no platform function 135 to retrieve these in generic code. We choose ``arg2``, ``arg3`` and 136 ``arg4`` since the generic code uses ``arg1`` for stashing the SP manifest 137 size. The SPMC setup uses these arguments to update SP manifest with 138 actual SP's base address and it size. 139 - In case of the Arm FVP platform, FW_CONFIG address passed in ``arg1`` to 140 BL31/SP_MIN, and the SOC_FW_CONFIG and HW_CONFIG details are retrieved 141 from FW_CONFIG device tree. 142 143BL1 144~~~ 145 146This stage begins execution from the platform's reset vector at EL3. The reset 147address is platform dependent but it is usually located in a Trusted ROM area. 148The BL1 data section is copied to trusted SRAM at runtime. 149 150On the Arm development platforms, BL1 code starts execution from the reset 151vector defined by the constant ``BL1_RO_BASE``. The BL1 data section is copied 152to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``. 153 154The functionality implemented by this stage is as follows. 155 156Determination of boot path 157^^^^^^^^^^^^^^^^^^^^^^^^^^ 158 159Whenever a CPU is released from reset, BL1 needs to distinguish between a warm 160boot and a cold boot. This is done using platform-specific mechanisms (see the 161``plat_get_my_entrypoint()`` function in the :ref:`Porting Guide`). In the case 162of a warm boot, a CPU is expected to continue execution from a separate 163entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe 164platform-specific state (see the ``plat_secondary_cold_boot_setup()`` function in 165the :ref:`Porting Guide`) while the primary CPU executes the remaining cold boot 166path as described in the following sections. 167 168This step only applies when ``PROGRAMMABLE_RESET_ADDRESS=0``. Refer to the 169:ref:`CPU Reset` for more information on the effect of the 170``PROGRAMMABLE_RESET_ADDRESS`` platform build option. 171 172Architectural initialization 173^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 174 175BL1 performs minimal architectural initialization as follows. 176 177- Exception vectors 178 179 BL1 sets up simple exception vectors for both synchronous and asynchronous 180 exceptions. The default behavior upon receiving an exception is to populate 181 a status code in the general purpose register ``X0/R0`` and call the 182 ``plat_report_exception()`` function (see the :ref:`Porting Guide`). The 183 status code is one of: 184 185 For AArch64: 186 187 :: 188 189 0x0 : Synchronous exception from Current EL with SP_EL0 190 0x1 : IRQ exception from Current EL with SP_EL0 191 0x2 : FIQ exception from Current EL with SP_EL0 192 0x3 : System Error exception from Current EL with SP_EL0 193 0x4 : Synchronous exception from Current EL with SP_ELx 194 0x5 : IRQ exception from Current EL with SP_ELx 195 0x6 : FIQ exception from Current EL with SP_ELx 196 0x7 : System Error exception from Current EL with SP_ELx 197 0x8 : Synchronous exception from Lower EL using aarch64 198 0x9 : IRQ exception from Lower EL using aarch64 199 0xa : FIQ exception from Lower EL using aarch64 200 0xb : System Error exception from Lower EL using aarch64 201 0xc : Synchronous exception from Lower EL using aarch32 202 0xd : IRQ exception from Lower EL using aarch32 203 0xe : FIQ exception from Lower EL using aarch32 204 0xf : System Error exception from Lower EL using aarch32 205 206 For AArch32: 207 208 :: 209 210 0x10 : User mode 211 0x11 : FIQ mode 212 0x12 : IRQ mode 213 0x13 : SVC mode 214 0x16 : Monitor mode 215 0x17 : Abort mode 216 0x1a : Hypervisor mode 217 0x1b : Undefined mode 218 0x1f : System mode 219 220 The ``plat_report_exception()`` implementation on the Arm FVP port programs 221 the Versatile Express System LED register in the following format to 222 indicate the occurrence of an unexpected exception: 223 224 :: 225 226 SYS_LED[0] - Security state (Secure=0/Non-Secure=1) 227 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0) 228 For AArch32 it is always 0x0 229 SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value 230 of the status code 231 232 A write to the LED register reflects in the System LEDs (S6LED0..7) in the 233 CLCD window of the FVP. 234 235 BL1 does not expect to receive any exceptions other than the SMC exception. 236 For the latter, BL1 installs a simple stub. The stub expects to receive a 237 limited set of SMC types (determined by their function IDs in the general 238 purpose register ``X0/R0``): 239 240 - ``BL1_SMC_RUN_IMAGE``: This SMC is raised by BL2 to make BL1 pass control 241 to EL3 Runtime Software. 242 - All SMCs listed in section "BL1 SMC Interface" in the :ref:`Firmware Update (FWU)` 243 Design Guide are supported for AArch64 only. These SMCs are currently 244 not supported when BL1 is built for AArch32. 245 246 Any other SMC leads to an assertion failure. 247 248- CPU initialization 249 250 BL1 calls the ``reset_handler`` macro/function which in turn calls the CPU 251 specific reset handler function (see the section: "CPU specific operations 252 framework"). 253 254Platform initialization 255^^^^^^^^^^^^^^^^^^^^^^^ 256 257On Arm platforms, BL1 performs the following platform initializations: 258 259- Enable the Trusted Watchdog. 260- Initialize the console. 261- Configure the Interconnect to enable hardware coherency. 262- Enable the MMU and map the memory it needs to access. 263- Configure any required platform storage to load the next bootloader image 264 (BL2). 265- If the BL1 dynamic configuration file, ``TB_FW_CONFIG``, is available, then 266 load it to the platform defined address and make it available to BL2 via 267 ``arg0``. 268- Configure the system timer and program the `CNTFRQ_EL0` for use by NS-BL1U 269 and NS-BL2U firmware update images. 270 271Firmware Update detection and execution 272^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 273 274After performing platform setup, BL1 common code calls 275``bl1_plat_get_next_image_id()`` to determine if :ref:`Firmware Update (FWU)` is 276required or to proceed with the normal boot process. If the platform code 277returns ``BL2_IMAGE_ID`` then the normal boot sequence is executed as described 278in the next section, else BL1 assumes that :ref:`Firmware Update (FWU)` is 279required and execution passes to the first image in the 280:ref:`Firmware Update (FWU)` process. In either case, BL1 retrieves a descriptor 281of the next image by calling ``bl1_plat_get_image_desc()``. The image descriptor 282contains an ``entry_point_info_t`` structure, which BL1 uses to initialize the 283execution state of the next image. 284 285BL2 image load and execution 286^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 287 288In the normal boot flow, BL1 execution continues as follows: 289 290#. BL1 prints the following string from the primary CPU to indicate successful 291 execution of the BL1 stage: 292 293 :: 294 295 "Booting Trusted Firmware" 296 297#. BL1 loads a BL2 raw binary image from platform storage, at a 298 platform-specific base address. Prior to the load, BL1 invokes 299 ``bl1_plat_handle_pre_image_load()`` which allows the platform to update or 300 use the image information. If the BL2 image file is not present or if 301 there is not enough free trusted SRAM the following error message is 302 printed: 303 304 :: 305 306 "Failed to load BL2 firmware." 307 308#. BL1 invokes ``bl1_plat_handle_post_image_load()`` which again is intended 309 for platforms to take further action after image load. This function must 310 populate the necessary arguments for BL2, which may also include the memory 311 layout. Further description of the memory layout can be found later 312 in this document. 313 314#. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at 315 Secure SVC mode (for AArch32), starting from its load address. 316 317BL2 318~~~ 319 320BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure 321SVC mode (for AArch32) . BL2 is linked against and loaded at a platform-specific 322base address (more information can be found later in this document). 323The functionality implemented by BL2 is as follows. 324 325Architectural initialization 326^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 327 328For AArch64, BL2 performs the minimal architectural initialization required 329for subsequent stages of TF-A and normal world software. EL1 and EL0 are given 330access to Floating Point and Advanced SIMD registers by setting the 331``CPACR.FPEN`` bits. 332 333For AArch32, the minimal architectural initialization required for subsequent 334stages of TF-A and normal world software is taken care of in BL1 as both BL1 335and BL2 execute at PL1. 336 337Platform initialization 338^^^^^^^^^^^^^^^^^^^^^^^ 339 340On Arm platforms, BL2 performs the following platform initializations: 341 342- Initialize the console. 343- Configure any required platform storage to allow loading further bootloader 344 images. 345- Enable the MMU and map the memory it needs to access. 346- Perform platform security setup to allow access to controlled components. 347- Reserve some memory for passing information to the next bootloader image 348 EL3 Runtime Software and populate it. 349- Define the extents of memory available for loading each subsequent 350 bootloader image. 351- If BL1 has passed TB_FW_CONFIG dynamic configuration file in ``arg0``, 352 then parse it. 353 354Image loading in BL2 355^^^^^^^^^^^^^^^^^^^^ 356 357BL2 generic code loads the images based on the list of loadable images 358provided by the platform. BL2 passes the list of executable images 359provided by the platform to the next handover BL image. 360 361The list of loadable images provided by the platform may also contain 362dynamic configuration files. The files are loaded and can be parsed as 363needed in the ``bl2_plat_handle_post_image_load()`` function. These 364configuration files can be passed to next Boot Loader stages as arguments 365by updating the corresponding entrypoint information in this function. 366 367SCP_BL2 (System Control Processor Firmware) image load 368^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 369 370Some systems have a separate System Control Processor (SCP) for power, clock, 371reset and system control. BL2 loads the optional SCP_BL2 image from platform 372storage into a platform-specific region of secure memory. The subsequent 373handling of SCP_BL2 is platform specific. For example, on the Juno Arm 374development platform port the image is transferred into SCP's internal memory 375using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM 376memory. The SCP executes SCP_BL2 and signals to the Application Processor (AP) 377for BL2 execution to continue. 378 379EL3 Runtime Software image load 380^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 381 382BL2 loads the EL3 Runtime Software image from platform storage into a platform- 383specific address in trusted SRAM. If there is not enough memory to load the 384image or image is missing it leads to an assertion failure. 385 386AArch64 BL32 (Secure-EL1 Payload) image load 387^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 388 389BL2 loads the optional BL32 image from platform storage into a platform- 390specific region of secure memory. The image executes in the secure world. BL2 391relies on BL31 to pass control to the BL32 image, if present. Hence, BL2 392populates a platform-specific area of memory with the entrypoint/load-address 393of the BL32 image. The value of the Saved Processor Status Register (``SPSR``) 394for entry into BL32 is not determined by BL2, it is initialized by the 395Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for 396managing interaction with BL32. This information is passed to BL31. 397 398BL33 (Non-trusted Firmware) image load 399^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 400 401BL2 loads the BL33 image (e.g. UEFI or other test or boot software) from 402platform storage into non-secure memory as defined by the platform. 403 404BL2 relies on EL3 Runtime Software to pass control to BL33 once secure state 405initialization is complete. Hence, BL2 populates a platform-specific area of 406memory with the entrypoint and Saved Program Status Register (``SPSR``) of the 407normal world software image. The entrypoint is the load address of the BL33 408image. The ``SPSR`` is determined as specified in Section 5.13 of the 409`PSCI`_. This information is passed to the EL3 Runtime Software. 410 411AArch64 BL31 (EL3 Runtime Software) execution 412^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 413 414BL2 execution continues as follows: 415 416#. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the 417 BL31 entrypoint. The exception is handled by the SMC exception handler 418 installed by BL1. 419 420#. BL1 turns off the MMU and flushes the caches. It clears the 421 ``SCTLR_EL3.M/I/C`` bits, flushes the data cache to the point of coherency 422 and invalidates the TLBs. 423 424#. BL1 passes control to BL31 at the specified entrypoint at EL3. 425 426Running BL2 at EL3 execution level 427~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 428 429Some platforms have a non-TF-A Boot ROM that expects the next boot stage 430to execute at EL3. On these platforms, TF-A BL1 is a waste of memory 431as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid 432this waste, a special mode enables BL2 to execute at EL3, which allows 433a non-TF-A Boot ROM to load and jump directly to BL2. This mode is selected 434when the build flag RESET_TO_BL2 is enabled. 435The main differences in this mode are: 436 437#. BL2 includes the reset code and the mailbox mechanism to differentiate 438 cold boot and warm boot. It runs at EL3 doing the arch 439 initialization required for EL3. 440 441#. BL2 does not receive the meminfo information from BL1 anymore. This 442 information can be passed by the Boot ROM or be internal to the 443 BL2 image. 444 445#. Since BL2 executes at EL3, BL2 jumps directly to the next image, 446 instead of invoking the RUN_IMAGE SMC call. 447 448 449We assume 3 different types of BootROM support on the platform: 450 451#. The Boot ROM always jumps to the same address, for both cold 452 and warm boot. In this case, we will need to keep a resident part 453 of BL2 whose memory cannot be reclaimed by any other image. The 454 linker script defines the symbols __TEXT_RESIDENT_START__ and 455 __TEXT_RESIDENT_END__ that allows the platform to configure 456 correctly the memory map. 457#. The platform has some mechanism to indicate the jump address to the 458 Boot ROM. Platform code can then program the jump address with 459 psci_warmboot_entrypoint during cold boot. 460#. The platform has some mechanism to program the reset address using 461 the PROGRAMMABLE_RESET_ADDRESS feature. Platform code can then 462 program the reset address with psci_warmboot_entrypoint during 463 cold boot, bypassing the boot ROM for warm boot. 464 465In the last 2 cases, no part of BL2 needs to remain resident at 466runtime. In the first 2 cases, we expect the Boot ROM to be able to 467differentiate between warm and cold boot, to avoid loading BL2 again 468during warm boot. 469 470This functionality can be tested with FVP loading the image directly 471in memory and changing the address where the system jumps at reset. 472For example: 473 474 -C cluster0.cpu0.RVBAR=0x4022000 475 --data cluster0.cpu0=bl2.bin@0x4022000 476 477With this configuration, FVP is like a platform of the first case, 478where the Boot ROM jumps always to the same address. For simplification, 479BL32 is loaded in DRAM in this case, to avoid other images reclaiming 480BL2 memory. 481 482 483AArch64 BL31 484~~~~~~~~~~~~ 485 486The image for this stage is loaded by BL2 and BL1 passes control to BL31 at 487EL3. BL31 executes solely in trusted SRAM. BL31 is linked against and 488loaded at a platform-specific base address (more information can be found later 489in this document). The functionality implemented by BL31 is as follows. 490 491Architectural initialization 492^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 493 494Currently, BL31 performs a similar architectural initialization to BL1 as 495far as system register settings are concerned. Since BL1 code resides in ROM, 496architectural initialization in BL31 allows override of any previous 497initialization done by BL1. 498 499BL31 initializes the per-CPU data framework, which provides a cache of 500frequently accessed per-CPU data optimised for fast, concurrent manipulation 501on different CPUs. This buffer includes pointers to per-CPU contexts, crash 502buffer, CPU reset and power down operations, PSCI data, platform data and so on. 503 504It then replaces the exception vectors populated by BL1 with its own. BL31 505exception vectors implement more elaborate support for handling SMCs since this 506is the only mechanism to access the runtime services implemented by BL31 (PSCI 507for example). BL31 checks each SMC for validity as specified by the 508`SMC Calling Convention`_ before passing control to the required SMC 509handler routine. 510 511BL31 programs the ``CNTFRQ_EL0`` register with the clock frequency of the system 512counter, which is provided by the platform. 513 514Platform initialization 515^^^^^^^^^^^^^^^^^^^^^^^ 516 517BL31 performs detailed platform initialization, which enables normal world 518software to function correctly. 519 520On Arm platforms, this consists of the following: 521 522- Initialize the console. 523- Configure the Interconnect to enable hardware coherency. 524- Enable the MMU and map the memory it needs to access. 525- Initialize the generic interrupt controller. 526- Initialize the power controller device. 527- Detect the system topology. 528 529Runtime services initialization 530^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 531 532BL31 is responsible for initializing the runtime services. One of them is PSCI. 533 534As part of the PSCI initializations, BL31 detects the system topology. It also 535initializes the data structures that implement the state machine used to track 536the state of power domain nodes. The state can be one of ``OFF``, ``RUN`` or 537``RETENTION``. All secondary CPUs are initially in the ``OFF`` state. The cluster 538that the primary CPU belongs to is ``ON``; any other cluster is ``OFF``. It also 539initializes the locks that protect them. BL31 accesses the state of a CPU or 540cluster immediately after reset and before the data cache is enabled in the 541warm boot path. It is not currently possible to use 'exclusive' based spinlocks, 542therefore BL31 uses locks based on Lamport's Bakery algorithm instead. 543 544The runtime service framework and its initialization is described in more 545detail in the "EL3 runtime services framework" section below. 546 547Details about the status of the PSCI implementation are provided in the 548"Power State Coordination Interface" section below. 549 550AArch64 BL32 (Secure-EL1 Payload) image initialization 551^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 552 553If a BL32 image is present then there must be a matching Secure-EL1 Payload 554Dispatcher (SPD) service (see later for details). During initialization 555that service must register a function to carry out initialization of BL32 556once the runtime services are fully initialized. BL31 invokes such a 557registered function to initialize BL32 before running BL33. This initialization 558is not necessary for AArch32 SPs. 559 560Details on BL32 initialization and the SPD's role are described in the 561:ref:`firmware_design_sel1_spd` section below. 562 563BL33 (Non-trusted Firmware) execution 564^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 565 566EL3 Runtime Software initializes the EL2 or EL1 processor context for normal- 567world cold boot, ensuring that no secure state information finds its way into 568the non-secure execution state. EL3 Runtime Software uses the entrypoint 569information provided by BL2 to jump to the Non-trusted firmware image (BL33) 570at the highest available Exception Level (EL2 if available, otherwise EL1). 571 572Using alternative Trusted Boot Firmware in place of BL1 & BL2 (AArch64 only) 573~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 574 575Some platforms have existing implementations of Trusted Boot Firmware that 576would like to use TF-A BL31 for the EL3 Runtime Software. To enable this 577firmware architecture it is important to provide a fully documented and stable 578interface between the Trusted Boot Firmware and BL31. 579 580Future changes to the BL31 interface will be done in a backwards compatible 581way, and this enables these firmware components to be independently enhanced/ 582updated to develop and exploit new functionality. 583 584Required CPU state when calling ``bl31_entrypoint()`` during cold boot 585^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 586 587This function must only be called by the primary CPU. 588 589On entry to this function the calling primary CPU must be executing in AArch64 590EL3, little-endian data access, and all interrupt sources masked: 591 592:: 593 594 PSTATE.EL = 3 595 PSTATE.RW = 1 596 PSTATE.DAIF = 0xf 597 SCTLR_EL3.EE = 0 598 599X0 and X1 can be used to pass information from the Trusted Boot Firmware to the 600platform code in BL31: 601 602:: 603 604 X0 : Reserved for common TF-A information 605 X1 : Platform specific information 606 607BL31 zero-init sections (e.g. ``.bss``) should not contain valid data on entry, 608these will be zero filled prior to invoking platform setup code. 609 610Use of the X0 and X1 parameters 611''''''''''''''''''''''''''''''' 612 613The parameters are platform specific and passed from ``bl31_entrypoint()`` to 614``bl31_early_platform_setup()``. The value of these parameters is never directly 615used by the common BL31 code. 616 617The convention is that ``X0`` conveys information regarding the BL31, BL32 and 618BL33 images from the Trusted Boot firmware and ``X1`` can be used for other 619platform specific purpose. This convention allows platforms which use TF-A's 620BL1 and BL2 images to transfer additional platform specific information from 621Secure Boot without conflicting with future evolution of TF-A using ``X0`` to 622pass a ``bl31_params`` structure. 623 624BL31 common and SPD initialization code depends on image and entrypoint 625information about BL33 and BL32, which is provided via BL31 platform APIs. 626This information is required until the start of execution of BL33. This 627information can be provided in a platform defined manner, e.g. compiled into 628the platform code in BL31, or provided in a platform defined memory location 629by the Trusted Boot firmware, or passed from the Trusted Boot Firmware via the 630Cold boot Initialization parameters. This data may need to be cleaned out of 631the CPU caches if it is provided by an earlier boot stage and then accessed by 632BL31 platform code before the caches are enabled. 633 634TF-A's BL2 implementation passes a ``bl31_params`` structure in 635``X0`` and the Arm development platforms interpret this in the BL31 platform 636code. 637 638MMU, Data caches & Coherency 639'''''''''''''''''''''''''''' 640 641BL31 does not depend on the enabled state of the MMU, data caches or 642interconnect coherency on entry to ``bl31_entrypoint()``. If these are disabled 643on entry, these should be enabled during ``bl31_plat_arch_setup()``. 644 645Data structures used in the BL31 cold boot interface 646'''''''''''''''''''''''''''''''''''''''''''''''''''' 647 648In the cold boot flow, ``entry_point_info`` is used to represent the execution 649state of an image; that is, the state of general purpose registers, PC, and 650SPSR. 651 652There are two variants of this structure, for AArch64: 653 654.. code:: c 655 656 typedef struct entry_point_info { 657 param_header_t h; 658 uintptr_t pc; 659 uint32_t spsr; 660 661 aapcs64_params_t args; 662 } 663 664and, AArch32: 665 666.. code:: c 667 668 typedef struct entry_point_info { 669 param_header_t h; 670 uintptr_t pc; 671 uint32_t spsr; 672 673 uintptr_t lr_svc; 674 aapcs32_params_t args; 675 } entry_point_info_t; 676 677These structures are designed to support compatibility and independent 678evolution of the structures and the firmware images. For example, a version of 679BL31 that can interpret the BL3x image information from different versions of 680BL2, a platform that uses an extended entry_point_info structure to convey 681additional register information to BL31, or a ELF image loader that can convey 682more details about the firmware images. 683 684To support these scenarios the structures are versioned and sized, which enables 685BL31 to detect which information is present and respond appropriately. The 686``param_header`` is defined to capture this information: 687 688.. code:: c 689 690 typedef struct param_header { 691 uint8_t type; /* type of the structure */ 692 uint8_t version; /* version of this structure */ 693 uint16_t size; /* size of this structure in bytes */ 694 uint32_t attr; /* attributes */ 695 } param_header_t; 696 697In `entry_point_info`, Bits 0 and 5 of ``attr`` field are used to encode the 698security state; in other words, whether the image is to be executed in Secure, 699Non-Secure, or Realm mode. 700 701Other structures using this format are ``image_info`` and ``bl31_params``. The 702code that allocates and populates these structures must set the header fields 703appropriately, the ``SET_PARAM_HEAD()`` macro is defined to simplify this 704action. 705 706Required CPU state for BL31 Warm boot initialization 707^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 708 709When requesting a CPU power-on, or suspending a running CPU, TF-A provides 710the platform power management code with a Warm boot initialization 711entry-point, to be invoked by the CPU immediately after the reset handler. 712On entry to the Warm boot initialization function the calling CPU must be in 713AArch64 EL3, little-endian data access and all interrupt sources masked: 714 715:: 716 717 PSTATE.EL = 3 718 PSTATE.RW = 1 719 PSTATE.DAIF = 0xf 720 SCTLR_EL3.EE = 0 721 722The PSCI implementation will initialize the processor state and ensure that the 723platform power management code is then invoked as required to initialize all 724necessary system, cluster and CPU resources. 725 726AArch32 EL3 Runtime Software entrypoint interface 727~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 728 729To enable this firmware architecture it is important to provide a fully 730documented and stable interface between the Trusted Boot Firmware and the 731AArch32 EL3 Runtime Software. 732 733Future changes to the entrypoint interface will be done in a backwards 734compatible way, and this enables these firmware components to be independently 735enhanced/updated to develop and exploit new functionality. 736 737Required CPU state when entering during cold boot 738^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 739 740This function must only be called by the primary CPU. 741 742On entry to this function the calling primary CPU must be executing in AArch32 743EL3, little-endian data access, and all interrupt sources masked: 744 745:: 746 747 PSTATE.AIF = 0x7 748 SCTLR.EE = 0 749 750R0 and R1 are used to pass information from the Trusted Boot Firmware to the 751platform code in AArch32 EL3 Runtime Software: 752 753:: 754 755 R0 : Reserved for common TF-A information 756 R1 : Platform specific information 757 758Use of the R0 and R1 parameters 759''''''''''''''''''''''''''''''' 760 761The parameters are platform specific and the convention is that ``R0`` conveys 762information regarding the BL3x images from the Trusted Boot firmware and ``R1`` 763can be used for other platform specific purpose. This convention allows 764platforms which use TF-A's BL1 and BL2 images to transfer additional platform 765specific information from Secure Boot without conflicting with future 766evolution of TF-A using ``R0`` to pass a ``bl_params`` structure. 767 768The AArch32 EL3 Runtime Software is responsible for entry into BL33. This 769information can be obtained in a platform defined manner, e.g. compiled into 770the AArch32 EL3 Runtime Software, or provided in a platform defined memory 771location by the Trusted Boot firmware, or passed from the Trusted Boot Firmware 772via the Cold boot Initialization parameters. This data may need to be cleaned 773out of the CPU caches if it is provided by an earlier boot stage and then 774accessed by AArch32 EL3 Runtime Software before the caches are enabled. 775 776When using AArch32 EL3 Runtime Software, the Arm development platforms pass a 777``bl_params`` structure in ``R0`` from BL2 to be interpreted by AArch32 EL3 Runtime 778Software platform code. 779 780MMU, Data caches & Coherency 781'''''''''''''''''''''''''''' 782 783AArch32 EL3 Runtime Software must not depend on the enabled state of the MMU, 784data caches or interconnect coherency in its entrypoint. They must be explicitly 785enabled if required. 786 787Data structures used in cold boot interface 788''''''''''''''''''''''''''''''''''''''''''' 789 790The AArch32 EL3 Runtime Software cold boot interface uses ``bl_params`` instead 791of ``bl31_params``. The ``bl_params`` structure is based on the convention 792described in AArch64 BL31 cold boot interface section. 793 794Required CPU state for warm boot initialization 795^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 796 797When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3 798Runtime Software must ensure execution of a warm boot initialization entrypoint. 799If TF-A BL1 is used and the PROGRAMMABLE_RESET_ADDRESS build flag is false, 800then AArch32 EL3 Runtime Software must ensure that BL1 branches to the warm 801boot entrypoint by arranging for the BL1 platform function, 802plat_get_my_entrypoint(), to return a non-zero value. 803 804In this case, the warm boot entrypoint must be in AArch32 EL3, little-endian 805data access and all interrupt sources masked: 806 807:: 808 809 PSTATE.AIF = 0x7 810 SCTLR.EE = 0 811 812The warm boot entrypoint may be implemented by using TF-A 813``psci_warmboot_entrypoint()`` function. In that case, the platform must fulfil 814the pre-requisites mentioned in the 815:ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`. 816 817EL3 runtime services framework 818------------------------------ 819 820Software executing in the non-secure state and in the secure state at exception 821levels lower than EL3 will request runtime services using the Secure Monitor 822Call (SMC) instruction. These requests will follow the convention described in 823the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function 824identifiers to each SMC request and describes how arguments are passed and 825returned. 826 827The EL3 runtime services framework enables the development of services by 828different providers that can be easily integrated into final product firmware. 829The following sections describe the framework which facilitates the 830registration, initialization and use of runtime services in EL3 Runtime 831Software (BL31). 832 833The design of the runtime services depends heavily on the concepts and 834definitions described in the `SMCCC`_, in particular SMC Function IDs, Owning 835Entity Numbers (OEN), Fast and Yielding calls, and the SMC32 and SMC64 calling 836conventions. Please refer to that document for more detailed explanation of 837these terms. 838 839The following runtime services are expected to be implemented first. They have 840not all been instantiated in the current implementation. 841 842#. Standard service calls 843 844 This service is for management of the entire system. The Power State 845 Coordination Interface (`PSCI`_) is the first set of standard service calls 846 defined by Arm (see PSCI section later). 847 848#. Secure-EL1 Payload Dispatcher service 849 850 If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then 851 it also requires a *Secure Monitor* at EL3 to switch the EL1 processor 852 context between the normal world (EL1/EL2) and trusted world (Secure-EL1). 853 The Secure Monitor will make these world switches in response to SMCs. The 854 `SMCCC`_ provides for such SMCs with the Trusted OS Call and Trusted 855 Application Call OEN ranges. 856 857 The interface between the EL3 Runtime Software and the Secure-EL1 Payload is 858 not defined by the `SMCCC`_ or any other standard. As a result, each 859 Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime 860 service - within TF-A this service is referred to as the Secure-EL1 Payload 861 Dispatcher (SPD). 862 863 TF-A provides a Test Secure-EL1 Payload (TSP) and its associated Dispatcher 864 (TSPD). Details of SPD design and TSP/TSPD operation are described in the 865 :ref:`firmware_design_sel1_spd` section below. 866 867#. CPU implementation service 868 869 This service will provide an interface to CPU implementation specific 870 services for a given platform e.g. access to processor errata workarounds. 871 This service is currently unimplemented. 872 873Additional services for Arm Architecture, SiP and OEM calls can be implemented. 874Each implemented service handles a range of SMC function identifiers as 875described in the `SMCCC`_. 876 877Registration 878~~~~~~~~~~~~ 879 880A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying 881the name of the service, the range of OENs covered, the type of service and 882initialization and call handler functions. This macro instantiates a ``const struct rt_svc_desc`` for the service with these details (see ``runtime_svc.h``). 883This structure is allocated in a special ELF section ``.rt_svc_descs``, enabling 884the framework to find all service descriptors included into BL31. 885 886The specific service for a SMC Function is selected based on the OEN and call 887type of the Function ID, and the framework uses that information in the service 888descriptor to identify the handler for the SMC Call. 889 890The service descriptors do not include information to identify the precise set 891of SMC function identifiers supported by this service implementation, the 892security state from which such calls are valid nor the capability to support 89364-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately 894to these aspects of a SMC call is the responsibility of the service 895implementation, the framework is focused on integration of services from 896different providers and minimizing the time taken by the framework before the 897service handler is invoked. 898 899Details of the parameters, requirements and behavior of the initialization and 900call handling functions are provided in the following sections. 901 902Initialization 903~~~~~~~~~~~~~~ 904 905``runtime_svc_init()`` in ``runtime_svc.c`` initializes the runtime services 906framework running on the primary CPU during cold boot as part of the BL31 907initialization. This happens prior to initializing a Trusted OS and running 908Normal world boot firmware that might in turn use these services. 909Initialization involves validating each of the declared runtime service 910descriptors, calling the service initialization function and populating the 911index used for runtime lookup of the service. 912 913The BL31 linker script collects all of the declared service descriptors into a 914single array and defines symbols that allow the framework to locate and traverse 915the array, and determine its size. 916 917The framework does basic validation of each descriptor to halt firmware 918initialization if service declaration errors are detected. The framework does 919not check descriptors for the following error conditions, and may behave in an 920unpredictable manner under such scenarios: 921 922#. Overlapping OEN ranges 923#. Multiple descriptors for the same range of OENs and ``call_type`` 924#. Incorrect range of owning entity numbers for a given ``call_type`` 925 926Once validated, the service ``init()`` callback is invoked. This function carries 927out any essential EL3 initialization before servicing requests. The ``init()`` 928function is only invoked on the primary CPU during cold boot. If the service 929uses per-CPU data this must either be initialized for all CPUs during this call, 930or be done lazily when a CPU first issues an SMC call to that service. If 931``init()`` returns anything other than ``0``, this is treated as an initialization 932error and the service is ignored: this does not cause the firmware to halt. 933 934The OEN and call type fields present in the SMC Function ID cover a total of 935128 distinct services, but in practice a single descriptor can cover a range of 936OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a 937service handler, the framework uses an array of 128 indices that map every 938distinct OEN/call-type combination either to one of the declared services or to 939indicate the service is not handled. This ``rt_svc_descs_indices[]`` array is 940populated for all of the OENs covered by a service after the service ``init()`` 941function has reported success. So a service that fails to initialize will never 942have it's ``handle()`` function invoked. 943 944The following figure shows how the ``rt_svc_descs_indices[]`` index maps the SMC 945Function ID call type and OEN onto a specific service handler in the 946``rt_svc_descs[]`` array. 947 948|Image 1| 949 950.. _handling-an-smc: 951 952Handling an SMC 953~~~~~~~~~~~~~~~ 954 955When the EL3 runtime services framework receives a Secure Monitor Call, the SMC 956Function ID is passed in W0 from the lower exception level (as per the 957`SMCCC`_). If the calling register width is AArch32, it is invalid to invoke an 958SMC Function which indicates the SMC64 calling convention: such calls are 959ignored and return the Unknown SMC Function Identifier result code ``0xFFFFFFFF`` 960in R0/X0. 961 962Bit[31] (fast/yielding call) and bits[29:24] (owning entity number) of the SMC 963Function ID are combined to index into the ``rt_svc_descs_indices[]`` array. The 964resulting value might indicate a service that has no handler, in this case the 965framework will also report an Unknown SMC Function ID. Otherwise, the value is 966used as a further index into the ``rt_svc_descs[]`` array to locate the required 967service and handler. 968 969The service's ``handle()`` callback is provided with five of the SMC parameters 970directly, the others are saved into memory for retrieval (if needed) by the 971handler. The handler is also provided with an opaque ``handle`` for use with the 972supporting library for parameter retrieval, setting return values and context 973manipulation. The ``flags`` parameter indicates the security state of the caller 974and the state of the SVE hint bit per the SMCCCv1.3. The framework finally sets 975up the execution stack for the handler, and invokes the services ``handle()`` 976function. 977 978On return from the handler the result registers are populated in X0-X7 as needed 979before restoring the stack and CPU state and returning from the original SMC. 980 981Exception Handling Framework 982---------------------------- 983 984Please refer to the :ref:`Exception Handling Framework` document. 985 986Power State Coordination Interface 987---------------------------------- 988 989TODO: Provide design walkthrough of PSCI implementation. 990 991The PSCI v1.1 specification categorizes APIs as optional and mandatory. All the 992mandatory APIs in PSCI v1.1, PSCI v1.0 and in PSCI v0.2 draft specification 993`PSCI`_ are implemented. The table lists the PSCI v1.1 APIs and their support 994in generic code. 995 996An API implementation might have a dependency on platform code e.g. CPU_SUSPEND 997requires the platform to export a part of the implementation. Hence the level 998of support of the mandatory APIs depends upon the support exported by the 999platform port as well. The Juno and FVP (all variants) platforms export all the 1000required support. 1001 1002+-----------------------------+-------------+-------------------------------+ 1003| PSCI v1.1 API | Supported | Comments | 1004+=============================+=============+===============================+ 1005| ``PSCI_VERSION`` | Yes | The version returned is 1.1 | 1006+-----------------------------+-------------+-------------------------------+ 1007| ``CPU_SUSPEND`` | Yes\* | | 1008+-----------------------------+-------------+-------------------------------+ 1009| ``CPU_OFF`` | Yes\* | | 1010+-----------------------------+-------------+-------------------------------+ 1011| ``CPU_ON`` | Yes\* | | 1012+-----------------------------+-------------+-------------------------------+ 1013| ``AFFINITY_INFO`` | Yes | | 1014+-----------------------------+-------------+-------------------------------+ 1015| ``MIGRATE`` | Yes\*\* | | 1016+-----------------------------+-------------+-------------------------------+ 1017| ``MIGRATE_INFO_TYPE`` | Yes\*\* | | 1018+-----------------------------+-------------+-------------------------------+ 1019| ``MIGRATE_INFO_CPU`` | Yes\*\* | | 1020+-----------------------------+-------------+-------------------------------+ 1021| ``SYSTEM_OFF`` | Yes\* | | 1022+-----------------------------+-------------+-------------------------------+ 1023| ``SYSTEM_RESET`` | Yes\* | | 1024+-----------------------------+-------------+-------------------------------+ 1025| ``PSCI_FEATURES`` | Yes | | 1026+-----------------------------+-------------+-------------------------------+ 1027| ``CPU_FREEZE`` | No | | 1028+-----------------------------+-------------+-------------------------------+ 1029| ``CPU_DEFAULT_SUSPEND`` | No | | 1030+-----------------------------+-------------+-------------------------------+ 1031| ``NODE_HW_STATE`` | Yes\* | | 1032+-----------------------------+-------------+-------------------------------+ 1033| ``SYSTEM_SUSPEND`` | Yes\* | | 1034+-----------------------------+-------------+-------------------------------+ 1035| ``PSCI_SET_SUSPEND_MODE`` | No | | 1036+-----------------------------+-------------+-------------------------------+ 1037| ``PSCI_STAT_RESIDENCY`` | Yes\* | | 1038+-----------------------------+-------------+-------------------------------+ 1039| ``PSCI_STAT_COUNT`` | Yes\* | | 1040+-----------------------------+-------------+-------------------------------+ 1041| ``SYSTEM_RESET2`` | Yes\* | | 1042+-----------------------------+-------------+-------------------------------+ 1043| ``MEM_PROTECT`` | Yes\* | | 1044+-----------------------------+-------------+-------------------------------+ 1045| ``MEM_PROTECT_CHECK_RANGE`` | Yes\* | | 1046+-----------------------------+-------------+-------------------------------+ 1047 1048\*Note : These PSCI APIs require platform power management hooks to be 1049registered with the generic PSCI code to be supported. 1050 1051\*\*Note : These PSCI APIs require appropriate Secure Payload Dispatcher 1052hooks to be registered with the generic PSCI code to be supported. 1053 1054The PSCI implementation in TF-A is a library which can be integrated with 1055AArch64 or AArch32 EL3 Runtime Software for Armv8-A systems. A guide to 1056integrating PSCI library with AArch32 EL3 Runtime Software can be found 1057at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`. 1058 1059DSU driver 1060---------- 1061 1062Platforms that include a DSU (DynamIQ Shared Unit) can define 1063the ``USE_DSU_DRIVER`` build flag to enable the DSU driver. 1064This driver is responsible for configuring DSU-related powerdown 1065and power feature settings, enabling access to PMU registers at EL1 1066using ``dsu_driver_init()`` and for preserving the context of DSU 1067PMU system registers. 1068 1069To support the DSU driver, platforms must define the ``plat_dsu_data`` 1070structure. 1071 1072.. _firmware_design_sel1_spd: 1073 1074Secure-EL1 Payloads and Dispatchers 1075----------------------------------- 1076 1077On a production system that includes a Trusted OS running in Secure-EL1/EL0, 1078the Trusted OS is coupled with a companion runtime service in the BL31 1079firmware. This service is responsible for the initialisation of the Trusted 1080OS and all communications with it. The Trusted OS is the BL32 stage of the 1081boot flow in TF-A. The firmware will attempt to locate, load and execute a 1082BL32 image. 1083 1084TF-A uses a more general term for the BL32 software that runs at Secure-EL1 - 1085the *Secure-EL1 Payload* - as it is not always a Trusted OS. 1086 1087TF-A provides a Test Secure-EL1 Payload (TSP) and a Test Secure-EL1 Payload 1088Dispatcher (TSPD) service as an example of how a Trusted OS is supported on a 1089production system using the Runtime Services Framework. On such a system, the 1090Test BL32 image and service are replaced by the Trusted OS and its dispatcher 1091service. The TF-A build system expects that the dispatcher will define the 1092build flag ``NEED_BL32`` to enable it to include the BL32 in the build either 1093as a binary or to compile from source depending on whether the ``BL32`` build 1094option is specified or not. 1095 1096The TSP runs in Secure-EL1. It is designed to demonstrate synchronous 1097communication with the normal-world software running in EL1/EL2. Communication 1098is initiated by the normal-world software 1099 1100- either directly through a Fast SMC (as defined in the `SMCCC`_) 1101 1102- or indirectly through a `PSCI`_ SMC. The `PSCI`_ implementation in turn 1103 informs the TSPD about the requested power management operation. This allows 1104 the TSP to prepare for or respond to the power state change 1105 1106The TSPD service is responsible for. 1107 1108- Initializing the TSP 1109 1110- Routing requests and responses between the secure and the non-secure 1111 states during the two types of communications just described 1112 1113Initializing a BL32 Image 1114~~~~~~~~~~~~~~~~~~~~~~~~~ 1115 1116The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing 1117the BL32 image. It needs access to the information passed by BL2 to BL31 to do 1118so. This is provided by: 1119 1120.. code:: c 1121 1122 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t); 1123 1124which returns a reference to the ``entry_point_info`` structure corresponding to 1125the image which will be run in the specified security state. The SPD uses this 1126API to get entry point information for the SECURE image, BL32. 1127 1128In the absence of a BL32 image, BL31 passes control to the normal world 1129bootloader image (BL33). When the BL32 image is present, it is typical 1130that the SPD wants control to be passed to BL32 first and then later to BL33. 1131 1132To do this the SPD has to register a BL32 initialization function during 1133initialization of the SPD service. The BL32 initialization function has this 1134prototype: 1135 1136.. code:: c 1137 1138 int32_t init(void); 1139 1140and is registered using the ``bl31_register_bl32_init()`` function. 1141 1142TF-A supports two approaches for the SPD to pass control to BL32 before 1143returning through EL3 and running the non-trusted firmware (BL33): 1144 1145#. In the BL32 setup function, use ``bl31_set_next_image_type()`` to 1146 request that the exit from ``bl31_main()`` is to the BL32 entrypoint in 1147 Secure-EL1. BL31 will exit to BL32 using the asynchronous method by 1148 calling ``bl31_prepare_next_image_entry()`` and ``el3_exit()``. 1149 1150 When the BL32 has completed initialization at Secure-EL1, it returns to 1151 BL31 by issuing an SMC, using a Function ID allocated to the SPD. On 1152 receipt of this SMC, the SPD service handler should switch the CPU context 1153 from trusted to normal world and use the ``bl31_set_next_image_type()`` and 1154 ``bl31_prepare_next_image_entry()`` functions to set up the initial return to 1155 the normal world firmware BL33. On return from the handler the framework 1156 will exit to EL2 and run BL33. 1157 1158#. The BL32 setup function registers an initialization function using 1159 ``bl31_register_bl32_init()`` which provides a SPD-defined mechanism to 1160 invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32 1161 entrypoint. 1162 1163 .. note:: 1164 The Test SPD service included with TF-A provides one implementation 1165 of such a mechanism. 1166 1167 On completion BL32 returns control to BL31 via a SMC, and on receipt the 1168 SPD service handler invokes the synchronous call return mechanism to return 1169 to the BL32 initialization function. On return from this function, 1170 ``bl31_main()`` will set up the return to the normal world firmware BL33 and 1171 continue the boot process in the normal world. 1172 1173Exception handling in BL31 1174-------------------------- 1175 1176When exception occurs, PE must execute handler corresponding to exception. The 1177location in memory where the handler is stored is called the exception vector. 1178For ARM architecture, exception vectors are stored in a table, called the exception 1179vector table. 1180 1181Each EL (except EL0) has its own vector table, VBAR_ELn register stores the base 1182of vector table. Refer to `AArch64 exception vector table`_ 1183 1184Current EL with SP_EL0 1185~~~~~~~~~~~~~~~~~~~~~~ 1186 1187- Sync exception : Not expected except for BRK instruction, its debugging tool which 1188 a programmer may place at specific points in a program, to check the state of 1189 processor flags at these points in the code. 1190 1191- IRQ/FIQ : Unexpected exception, panic 1192 1193- SError : "plat_handle_el3_ea", defaults to panic 1194 1195Current EL with SP_ELx 1196~~~~~~~~~~~~~~~~~~~~~~ 1197 1198- Sync exception : Unexpected exception, panic 1199 1200- IRQ/FIQ : Unexpected exception, panic 1201 1202- SError : "plat_handle_el3_ea" Except for special handling of lower EL's SError exception 1203 which gets triggered in EL3 when PSTATE.A is unmasked. Its only applicable when lower 1204 EL's EA is routed to EL3 (FFH_SUPPORT=1). 1205 1206Lower EL Exceptions 1207~~~~~~~~~~~~~~~~~~~ 1208 1209Applies to all the exceptions in both AArch64/AArch32 mode of lower EL. 1210 1211Before handling any lower EL exception, we synchronize the errors at EL3 entry to ensure 1212that any errors pertaining to lower EL is isolated/identified. If we continue without 1213identifying these errors early on then these errors will trigger in EL3 (as SError from 1214current EL) any time after PSTATE.A is unmasked. This is wrong because the error originated 1215in lower EL but exception happened in EL3. 1216 1217To solve this problem, synchronize the errors at EL3 entry and check for any pending 1218errors (async EA). If there is no pending error then continue with original exception. 1219If there is a pending error then, handle them based on routing model of EA's. Refer to 1220:ref:`Reliability, Availability, and Serviceability (RAS) Extensions` for details about 1221routing models. 1222 1223- KFH : Reflect it back to lower EL using **reflect_pending_async_ea_to_lower_el()** 1224 1225- FFH : Handle the synchronized error first using **handle_pending_async_ea()** after 1226 that continue with original exception. It is the only scenario where EL3 is capable 1227 of doing nested exception handling. 1228 1229After synchronizing and handling lower EL SErrors, unmask EA (PSTATE.A) to ensure 1230that any further EA's caused by EL3 are caught. 1231 1232Crash Reporting in BL31 1233----------------------- 1234 1235BL31 implements a scheme for reporting the processor state when an unhandled 1236exception is encountered. The reporting mechanism attempts to preserve all the 1237register contents and report it via a dedicated UART (PL011 console). BL31 1238reports the general purpose, EL3, Secure EL1 and some EL2 state registers. 1239 1240A dedicated per-CPU crash stack is maintained by BL31 and this is retrieved via 1241the per-CPU pointer cache. The implementation attempts to minimise the memory 1242required for this feature. The file ``crash_reporting.S`` contains the 1243implementation for crash reporting. 1244 1245The sample crash output is shown below. 1246 1247:: 1248 1249 x0 = 0x000000002a4a0000 1250 x1 = 0x0000000000000001 1251 x2 = 0x0000000000000002 1252 x3 = 0x0000000000000003 1253 x4 = 0x0000000000000004 1254 x5 = 0x0000000000000005 1255 x6 = 0x0000000000000006 1256 x7 = 0x0000000000000007 1257 x8 = 0x0000000000000008 1258 x9 = 0x0000000000000009 1259 x10 = 0x0000000000000010 1260 x11 = 0x0000000000000011 1261 x12 = 0x0000000000000012 1262 x13 = 0x0000000000000013 1263 x14 = 0x0000000000000014 1264 x15 = 0x0000000000000015 1265 x16 = 0x0000000000000016 1266 x17 = 0x0000000000000017 1267 x18 = 0x0000000000000018 1268 x19 = 0x0000000000000019 1269 x20 = 0x0000000000000020 1270 x21 = 0x0000000000000021 1271 x22 = 0x0000000000000022 1272 x23 = 0x0000000000000023 1273 x24 = 0x0000000000000024 1274 x25 = 0x0000000000000025 1275 x26 = 0x0000000000000026 1276 x27 = 0x0000000000000027 1277 x28 = 0x0000000000000028 1278 x29 = 0x0000000000000029 1279 x30 = 0x0000000088000b78 1280 scr_el3 = 0x000000000003073d 1281 sctlr_el3 = 0x00000000b0cd183f 1282 cptr_el3 = 0x0000000000000000 1283 tcr_el3 = 0x000000008080351c 1284 daif = 0x00000000000002c0 1285 mair_el3 = 0x00000000004404ff 1286 spsr_el3 = 0x0000000060000349 1287 elr_el3 = 0x0000000088000114 1288 ttbr0_el3 = 0x0000000004018201 1289 esr_el3 = 0x00000000be000000 1290 far_el3 = 0x0000000000000000 1291 spsr_el1 = 0x0000000000000000 1292 elr_el1 = 0x0000000000000000 1293 spsr_abt = 0x0000000000000000 1294 spsr_und = 0x0000000000000000 1295 spsr_irq = 0x0000000000000000 1296 spsr_fiq = 0x0000000000000000 1297 sctlr_el1 = 0x0000000030d00800 1298 actlr_el1 = 0x0000000000000000 1299 cpacr_el1 = 0x0000000000000000 1300 csselr_el1 = 0x0000000000000000 1301 sp_el1 = 0x0000000000000000 1302 esr_el1 = 0x0000000000000000 1303 ttbr0_el1 = 0x0000000000000000 1304 ttbr1_el1 = 0x0000000000000000 1305 mair_el1 = 0x0000000000000000 1306 amair_el1 = 0x0000000000000000 1307 tcr_el1 = 0x0000000000000000 1308 tpidr_el1 = 0x0000000000000000 1309 tpidr_el0 = 0x0000000000000000 1310 tpidrro_el0 = 0x0000000000000000 1311 par_el1 = 0x0000000000000000 1312 mpidr_el1 = 0x0000000080000000 1313 afsr0_el1 = 0x0000000000000000 1314 afsr1_el1 = 0x0000000000000000 1315 contextidr_el1 = 0x0000000000000000 1316 vbar_el1 = 0x0000000000000000 1317 cntp_ctl_el0 = 0x0000000000000000 1318 cntp_cval_el0 = 0x0000000000000000 1319 cntv_ctl_el0 = 0x0000000000000000 1320 cntv_cval_el0 = 0x0000000000000000 1321 cntkctl_el1 = 0x0000000000000000 1322 sp_el0 = 0x0000000004014940 1323 isr_el1 = 0x0000000000000000 1324 dacr32_el2 = 0x0000000000000000 1325 ifsr32_el2 = 0x0000000000000000 1326 icc_hppir0_el1 = 0x00000000000003ff 1327 icc_hppir1_el1 = 0x00000000000003ff 1328 icc_ctlr_el3 = 0x0000000000080400 1329 gicd_ispendr regs (Offsets 0x200-0x278) 1330 Offset Value 1331 0x200: 0x0000000000000000 1332 0x208: 0x0000000000000000 1333 0x210: 0x0000000000000000 1334 0x218: 0x0000000000000000 1335 0x220: 0x0000000000000000 1336 0x228: 0x0000000000000000 1337 0x230: 0x0000000000000000 1338 0x238: 0x0000000000000000 1339 0x240: 0x0000000000000000 1340 0x248: 0x0000000000000000 1341 0x250: 0x0000000000000000 1342 0x258: 0x0000000000000000 1343 0x260: 0x0000000000000000 1344 0x268: 0x0000000000000000 1345 0x270: 0x0000000000000000 1346 0x278: 0x0000000000000000 1347 1348Guidelines for Reset Handlers 1349----------------------------- 1350 1351TF-A implements a framework that allows CPU and platform ports to perform 1352actions very early after a CPU is released from reset in both the cold and warm 1353boot paths. This is done by calling the ``reset_handler`` macro/function in both 1354the BL1 and BL31 images. It in turn calls the platform and CPU specific reset 1355handling functions. 1356 1357Details for implementing a CPU specific reset handler can be found in 1358:ref:`firmware_design_cpu_specific_reset_handling`. Details for implementing a 1359platform specific reset handler can be found in the :ref:`Porting Guide` (see 1360the``plat_reset_handler()`` function). 1361 1362When adding functionality to a reset handler, keep in mind that if a different 1363reset handling behavior is required between the first and the subsequent 1364invocations of the reset handling code, this should be detected at runtime. 1365In other words, the reset handler should be able to detect whether an action has 1366already been performed and act as appropriate. Possible courses of actions are, 1367e.g. skip the action the second time, or undo/redo it. 1368 1369.. _configuring-secure-interrupts: 1370 1371Configuring secure interrupts 1372----------------------------- 1373 1374The GIC driver is responsible for performing initial configuration of secure 1375interrupts on the platform. To this end, the platform is expected to provide the 1376GIC driver (either GICv2 or GICv3, as selected by the platform) with the 1377interrupt configuration during the driver initialisation. 1378 1379Secure interrupt configuration are specified in an array of secure interrupt 1380properties. In this scheme, in both GICv2 and GICv3 driver data structures, the 1381``interrupt_props`` member points to an array of interrupt properties. Each 1382element of the array specifies the interrupt number and its attributes 1383(priority, group, configuration). Each element of the array shall be populated 1384by the macro ``INTR_PROP_DESC()``. The macro takes the following arguments: 1385 1386- 13-bit interrupt number, 1387 1388- 8-bit interrupt priority, 1389 1390- Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``, 1391 ``INTR_TYPE_NS``), 1392 1393- Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or 1394 ``GIC_INTR_CFG_EDGE``). 1395 1396.. _firmware_design_cpu_ops_fwk: 1397 1398CPU specific operations framework 1399--------------------------------- 1400 1401Certain aspects of the Armv8-A architecture are implementation defined, 1402that is, certain behaviours are not architecturally defined, but must be 1403defined and documented by individual processor implementations. TF-A 1404implements a framework which categorises the common implementation defined 1405behaviours and allows a processor to export its implementation of that 1406behaviour. The categories are: 1407 1408#. Processor specific reset sequence. 1409 1410#. Processor specific power down sequences. 1411 1412#. Processor specific register dumping as a part of crash reporting. 1413 1414#. Errata status reporting. 1415 1416Each of the above categories fulfils a different requirement. 1417 1418#. allows any processor specific initialization before the caches and MMU 1419 are turned on, like implementation of errata workarounds, entry into 1420 the intra-cluster coherency domain etc. 1421 1422#. allows each processor to implement the power down sequence mandated in 1423 its Technical Reference Manual (TRM). 1424 1425#. allows a processor to provide additional information to the developer 1426 in the event of a crash, for example Cortex-A53 has registers which 1427 can expose the data cache contents. 1428 1429#. allows a processor to define a function that inspects and reports the status 1430 of all errata workarounds on that processor. 1431 1432Please note that only 2. is mandated by the TRM. 1433 1434The CPU specific operations framework scales to accommodate a large number of 1435different CPUs during power down and reset handling. The platform can specify 1436any CPU optimization it wants to enable for each CPU. It can also specify 1437the CPU errata workarounds to be applied for each CPU type during reset 1438handling by defining CPU errata compile time macros. Details on these macros 1439can be found in the :ref:`Arm CPU Specific Build Macros` document. 1440 1441The CPU specific operations framework depends on the ``cpu_ops`` structure which 1442needs to be exported for each type of CPU in the platform. It is defined in 1443``include/lib/cpus/aarch64/cpu_macros.S`` and has the following fields : ``midr``, 1444``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and 1445``cpu_reg_dump()``. 1446 1447The CPU specific files in ``lib/cpus`` export a ``cpu_ops`` data structure with 1448suitable handlers for that CPU. For example, ``lib/cpus/aarch64/cortex_a53.S`` 1449exports the ``cpu_ops`` for Cortex-A53 CPU. According to the platform 1450configuration, these CPU specific files must be included in the build by 1451the platform makefile. The generic CPU specific operations framework code exists 1452in ``lib/cpus/aarch64/cpu_helpers.S``. 1453 1454CPU PCS 1455~~~~~~~ 1456 1457All assembly functions in CPU files are asked to follow a modified version of 1458the Procedure Call Standard (PCS) in their internals. This is done to ensure 1459calling these functions from outside the file doesn't unexpectedly corrupt 1460registers in the very early environment and to help the internals to be easier 1461to understand. Please see the :ref:`firmware_design_cpu_errata_implementation` 1462for any function specific restrictions. 1463 1464+--------------+---------------------------------+ 1465| register | use | 1466+==============+=================================+ 1467| x0 - x15 | scratch | 1468+--------------+---------------------------------+ 1469| x16, x17 | do not use (used by the linker) | 1470+--------------+---------------------------------+ 1471| x18 | do not use (platform register) | 1472+--------------+---------------------------------+ 1473| x19 - x28 | callee saved | 1474+--------------+---------------------------------+ 1475| x29, x30 | FP, LR | 1476+--------------+---------------------------------+ 1477 1478.. _firmware_design_cpu_specific_reset_handling: 1479 1480CPU specific Reset Handling 1481~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1482 1483After a reset, the state of the CPU when it calls generic reset handler is: 1484MMU turned off, both instruction and data caches turned off, not part 1485of any coherency domain and no stack. 1486 1487The BL entrypoint code first invokes the ``plat_reset_handler()`` to allow 1488the platform to perform any system initialization required and any system 1489errata workarounds that needs to be applied. The ``get_cpu_ops_ptr()`` reads 1490the current CPU midr, finds the matching ``cpu_ops`` entry in the ``cpu_ops`` 1491array and returns it. Note that only the part number and implementer fields 1492in midr are used to find the matching ``cpu_ops`` entry. The ``reset_func()`` in 1493the returned ``cpu_ops`` is then invoked which executes the required reset 1494handling for that CPU and also any errata workarounds enabled by the platform. 1495 1496It should be defined using the ``cpu_reset_func_{start,end}`` macros and its 1497body may only clobber x0 to x14 with x14 being the cpu_rev parameter. The cpu 1498file should also include a call to ``cpu_reset_prologue`` at the start of the 1499file for errata to work correctly. 1500 1501CPU specific power down sequence 1502~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1503 1504During the BL31 initialization sequence, the pointer to the matching ``cpu_ops`` 1505entry is stored in per-CPU data by ``cpu_data_init_cpu_ops()`` so that it can be quickly 1506retrieved during power down sequences. 1507 1508Various CPU drivers register handlers to perform power down at certain power 1509levels for that specific CPU. The PSCI service, upon receiving a power down 1510request, determines the highest power level at which to execute power down 1511sequence for a particular CPU. It uses the ``prepare_cpu_pwr_dwn()`` function to 1512pick the right power down handler for the requested level. The function 1513retrieves ``cpu_ops`` pointer member of per-CPU data, and from that, further 1514retrieves ``cpu_pwr_down_ops`` array, and indexes into the required level. If the 1515requested power level is higher than what a CPU driver supports, the handler 1516registered for highest level is invoked. 1517 1518At runtime the platform hooks for power down are invoked by the PSCI service to 1519perform platform specific operations during a power down sequence, for example 1520turning off CCI coherency during a cluster power down. 1521 1522Newer CPUs include a feature called "powerdown abandon". The feature is based on 1523the observation that events like GIC wakeups have a high likelihood of happening 1524while the core is in the middle of its powerdown sequence (at ``wfi``). Older 1525cores will powerdown and immediately power back up when this happens. To save on 1526the work and latency involved, the newer cores will "give up" mid way through if 1527no context has been lost yet. This is possible as the powerdown operation is 1528lengthy and a large part of it does not lose context. 1529 1530To cater for this possibility, the powerdown hook will be called a second time 1531after a wakeup. The expectation is that the first call will operate as before, 1532while the second call will undo anything the first call did. This should be done 1533statelessly, for example by toggling the relevant bits. 1534 1535CPU specific register reporting during crash 1536~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1537 1538If the crash reporting is enabled in BL31, when a crash occurs, the crash 1539reporting framework calls ``do_cpu_reg_dump`` which retrieves the matching 1540``cpu_ops`` using ``get_cpu_ops_ptr()`` function. The ``cpu_reg_dump()`` in 1541``cpu_ops`` is invoked, which then returns the CPU specific register values to 1542be reported and a pointer to the ASCII list of register names in a format 1543expected by the crash reporting framework. 1544 1545.. _firmware_design_cpu_errata_implementation: 1546 1547CPU errata implementation 1548~~~~~~~~~~~~~~~~~~~~~~~~~ 1549 1550Errata workarounds for CPUs supported in TF-A are applied during both cold and 1551warm boots, shortly after reset. Individual Errata workarounds are enabled as 1552build options. Some errata workarounds have potential run-time implications; 1553therefore some are enabled by default, others not. Platform ports shall 1554override build options to enable or disable errata as appropriate. The CPU 1555drivers take care of applying errata workarounds that are enabled and applicable 1556to a given CPU. 1557 1558Each erratum has a build flag in ``lib/cpus/cpu-ops.mk`` of the form: 1559``ERRATA_<cpu_num>_<erratum_id>``. It also has a short description in 1560:ref:`arm_cpu_macros_errata_workarounds` on when it should apply. 1561 1562Errata framework 1563^^^^^^^^^^^^^^^^ 1564 1565The errata framework is a convention and a small library to allow errata to be 1566automatically discovered. It enables compliant errata to be automatically 1567applied and reported at runtime (either by status reporting or the errata ABI). 1568 1569To write a compliant mitigation for erratum number ``erratum_id`` on a cpu that 1570declared itself (with ``declare_cpu_ops``) as ``cpu_name`` one needs 3 things: 1571 1572#. A CPU revision checker function: ``check_erratum_<cpu_name>_<erratum_id>`` 1573 1574 It should check whether this erratum applies on this revision of this CPU. 1575 It will be called with the CPU revision as its first parameter (x0) and 1576 should return one of ``ERRATA_APPLIES`` or ``ERRATA_NOT_APPLIES``. 1577 1578 It may only clobber x0 to x4. The rest should be treated as callee-saved. 1579 1580#. A workaround function: ``erratum_<cpu_name>_<erratum_id>_wa`` 1581 1582 It should obtain the cpu revision (with ``cpu_get_rev_var``), call its 1583 revision checker, and perform the mitigation, should the erratum apply. 1584 1585 It may only clobber x0 to x8. The rest should be treated as callee-saved. 1586 1587#. Register itself to the framework 1588 1589 Do this with 1590 ``add_erratum_entry <cpu_name>, ERRATUM(<erratum_id>), <errata_flag>`` 1591 where the ``errata_flag`` is the enable flag in ``cpu-ops.mk`` described 1592 above. 1593 1594See the next section on how to do this easily. 1595 1596.. note:: 1597 1598 CVEs have the format ``CVE_<year>_<number>``. To fit them in the framework, the 1599 ``erratum_id`` for the checker and the workaround functions become the 1600 ``number`` part of its name and the ``ERRATUM(<number>)`` part of the 1601 registration should instead be ``CVE(<year>, <number>)``. In the extremely 1602 unlikely scenario where a CVE and an erratum numbers clash, the CVE number 1603 should be prefixed with a zero. 1604 1605 Also, their build flag should be ``WORKAROUND_CVE_<year>_<number>``. 1606 1607.. note:: 1608 1609 AArch32 uses the legacy convention. The checker function has the format 1610 ``check_errata_<erratum_id>`` and the workaround has the format 1611 ``errata_<cpu_number>_<erratum_id>_wa`` where ``cpu_number`` is the shortform 1612 letter and number name of the CPU. 1613 1614 For CVEs the ``erratum_id`` also becomes ``cve_<year>_<number>``. 1615 1616Errata framework helpers 1617^^^^^^^^^^^^^^^^^^^^^^^^ 1618 1619Writing these errata involves lots of boilerplate and repetitive code. On 1620AArch64 there are helpers to omit most of this. They are located in 1621``include/lib/cpus/aarch64/cpu_macros.S`` and the preferred way to implement 1622errata. Please see their comments on how to use them. 1623 1624The most common type of erratum workaround, one that just sets a "chicken" bit 1625in some arbitrary register, would have an implementation for the Cortex-A77, 1626erratum #1925769 like:: 1627 1628 workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769 1629 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8 1630 workaround_reset_end cortex_a77, ERRATUM(1925769) 1631 1632 check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1) 1633 1634Status reporting 1635^^^^^^^^^^^^^^^^ 1636 1637In a debug build of TF-A, on a CPU that comes out of reset, both BL1 and the 1638runtime firmware (BL31 in AArch64, and BL32 in AArch32) will invoke a generic 1639errata status reporting function. It will read the ``errata_entries`` list of 1640that cpu and will report whether each known erratum was applied and, if not, 1641whether it should have been. 1642 1643Reporting the status of errata workaround is for informational purpose only; it 1644has no functional significance. 1645 1646Memory layout of BL images 1647-------------------------- 1648 1649Each bootloader image can be divided in 2 parts: 1650 1651- the static contents of the image. These are data actually stored in the 1652 binary on the disk. In the ELF terminology, they are called ``PROGBITS`` 1653 sections; 1654 1655- the run-time contents of the image. These are data that don't occupy any 1656 space in the binary on the disk. The ELF binary just contains some 1657 metadata indicating where these data will be stored at run-time and the 1658 corresponding sections need to be allocated and initialized at run-time. 1659 In the ELF terminology, they are called ``NOBITS`` sections. 1660 1661All PROGBITS sections are grouped together at the beginning of the image, 1662followed by all NOBITS sections. This is true for all TF-A images and it is 1663governed by the linker scripts. This ensures that the raw binary images are 1664as small as possible. If a NOBITS section was inserted in between PROGBITS 1665sections then the resulting binary file would contain zero bytes in place of 1666this NOBITS section, making the image unnecessarily bigger. Smaller images 1667allow faster loading from the FIP to the main memory. 1668 1669For BL31, a platform can specify an alternate location for NOBITS sections 1670(other than immediately following PROGBITS sections) by setting 1671``SEPARATE_NOBITS_REGION`` to 1 and defining ``BL31_NOBITS_BASE`` and 1672``BL31_NOBITS_LIMIT``. 1673 1674Linker scripts and symbols 1675~~~~~~~~~~~~~~~~~~~~~~~~~~ 1676 1677Each bootloader stage image layout is described by its own linker script. The 1678linker scripts export some symbols into the program symbol table. Their values 1679correspond to particular addresses. TF-A code can refer to these symbols to 1680figure out the image memory layout. 1681 1682Linker symbols follow the following naming convention in TF-A. 1683 1684- ``__<SECTION>_START__`` 1685 1686 Start address of a given section named ``<SECTION>``. 1687 1688- ``__<SECTION>_END__`` 1689 1690 End address of a given section named ``<SECTION>``. If there is an alignment 1691 constraint on the section's end address then ``__<SECTION>_END__`` corresponds 1692 to the end address of the section's actual contents, rounded up to the right 1693 boundary. Refer to the value of ``__<SECTION>_UNALIGNED_END__`` to know the 1694 actual end address of the section's contents. 1695 1696- ``__<SECTION>_UNALIGNED_END__`` 1697 1698 End address of a given section named ``<SECTION>`` without any padding or 1699 rounding up due to some alignment constraint. 1700 1701- ``__<SECTION>_SIZE__`` 1702 1703 Size (in bytes) of a given section named ``<SECTION>``. If there is an 1704 alignment constraint on the section's end address then ``__<SECTION>_SIZE__`` 1705 corresponds to the size of the section's actual contents, rounded up to the 1706 right boundary. In other words, ``__<SECTION>_SIZE__ = __<SECTION>_END__ - _<SECTION>_START__``. Refer to the value of ``__<SECTION>_UNALIGNED_SIZE__`` 1707 to know the actual size of the section's contents. 1708 1709- ``__<SECTION>_UNALIGNED_SIZE__`` 1710 1711 Size (in bytes) of a given section named ``<SECTION>`` without any padding or 1712 rounding up due to some alignment constraint. In other words, 1713 ``__<SECTION>_UNALIGNED_SIZE__ = __<SECTION>_UNALIGNED_END__ - __<SECTION>_START__``. 1714 1715Some of the linker symbols are mandatory as TF-A code relies on them to be 1716defined. They are listed in the following subsections. Some of them must be 1717provided for each bootloader stage and some are specific to a given bootloader 1718stage. 1719 1720The linker scripts define some extra, optional symbols. They are not actually 1721used by any code but they help in understanding the bootloader images' memory 1722layout as they are easy to spot in the link map files. 1723 1724Common linker symbols 1725^^^^^^^^^^^^^^^^^^^^^ 1726 1727All BL images share the following requirements: 1728 1729- The BSS section must be zero-initialised before executing any C code. 1730- The coherent memory section (if enabled) must be zero-initialised as well. 1731- The MMU setup code needs to know the extents of the coherent and read-only 1732 memory regions to set the right memory attributes. When 1733 ``SEPARATE_CODE_AND_RODATA=1``, it needs to know more specifically how the 1734 read-only memory region is divided between code and data. 1735 1736The following linker symbols are defined for this purpose: 1737 1738- ``__BSS_START__`` 1739- ``__BSS_SIZE__`` 1740- ``__COHERENT_RAM_START__`` Must be aligned on a page-size boundary. 1741- ``__COHERENT_RAM_END__`` Must be aligned on a page-size boundary. 1742- ``__COHERENT_RAM_UNALIGNED_SIZE__`` 1743- ``__RO_START__`` 1744- ``__RO_END__`` 1745- ``__TEXT_START__`` 1746- ``__TEXT_END_UNALIGNED__`` 1747- ``__TEXT_END__`` 1748- ``__RODATA_START__`` 1749- ``__RODATA_END_UNALIGNED__`` 1750- ``__RODATA_END__`` 1751 1752BL1's linker symbols 1753^^^^^^^^^^^^^^^^^^^^ 1754 1755BL1 being the ROM image, it has additional requirements. BL1 resides in ROM and 1756it is entirely executed in place but it needs some read-write memory for its 1757mutable data. Its ``.data`` section (i.e. its allocated read-write data) must be 1758relocated from ROM to RAM before executing any C code. 1759 1760The following additional linker symbols are defined for BL1: 1761 1762- ``__BL1_ROM_END__`` End address of BL1's ROM contents, covering its code 1763 and ``.data`` section in ROM. 1764- ``__DATA_ROM_START__`` Start address of the ``.data`` section in ROM. Must be 1765 aligned on a 16-byte boundary. 1766- ``__DATA_RAM_START__`` Address in RAM where the ``.data`` section should be 1767 copied over. Must be aligned on a 16-byte boundary. 1768- ``__DATA_SIZE__`` Size of the ``.data`` section (in ROM or RAM). 1769- ``__BL1_RAM_START__`` Start address of BL1 read-write data. 1770- ``__BL1_RAM_END__`` End address of BL1 read-write data. 1771 1772How to choose the right base addresses for each bootloader stage image 1773~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1774 1775There is currently no support for dynamic image loading in TF-A. This means 1776that all bootloader images need to be linked against their ultimate runtime 1777locations and the base addresses of each image must be chosen carefully such 1778that images don't overlap each other in an undesired way. As the code grows, 1779the base addresses might need adjustments to cope with the new memory layout. 1780 1781The memory layout is completely specific to the platform and so there is no 1782general recipe for choosing the right base addresses for each bootloader image. 1783However, there are tools to aid in understanding the memory layout. These are 1784the link map files: ``build/<platform>/<build-type>/bl<x>/bl<x>.map``, with ``<x>`` 1785being the stage bootloader. They provide a detailed view of the memory usage of 1786each image. Among other useful information, they provide the end address of 1787each image. 1788 1789- ``bl1.map`` link map file provides ``__BL1_RAM_END__`` address. 1790- ``bl2.map`` link map file provides ``__BL2_END__`` address. 1791- ``bl31.map`` link map file provides ``__BL31_END__`` address. 1792- ``bl32.map`` link map file provides ``__BL32_END__`` address. 1793 1794For each bootloader image, the platform code must provide its start address 1795as well as a limit address that it must not overstep. The latter is used in the 1796linker scripts to check that the image doesn't grow past that address. If that 1797happens, the linker will issue a message similar to the following: 1798 1799:: 1800 1801 aarch64-none-elf-ld: BLx has exceeded its limit. 1802 1803Additionally, if the platform memory layout implies some image overlaying like 1804on FVP, BL31 and TSP need to know the limit address that their PROGBITS 1805sections must not overstep. The platform code must provide those. 1806 1807TF-A does not provide any mechanism to verify at boot time that the memory 1808to load a new image is free to prevent overwriting a previously loaded image. 1809The platform must specify the memory available in the system for all the 1810relevant BL images to be loaded. 1811 1812For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will 1813return the region defined by the platform where BL1 intends to load BL2. The 1814``load_image()`` function performs bounds check for the image size based on the 1815base and maximum image size provided by the platforms. Platforms must take 1816this behaviour into account when defining the base/size for each of the images. 1817 1818Memory layout on Arm development platforms 1819^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1820 1821The following list describes the memory layout on the Arm development platforms: 1822 1823- A 4KB page of shared memory is used for communication between Trusted 1824 Firmware and the platform's power controller. This is located at the base of 1825 Trusted SRAM. The amount of Trusted SRAM available to load the bootloader 1826 images is reduced by the size of the shared memory. 1827 1828 The shared memory is used to store the CPUs' entrypoint mailbox. On Juno, 1829 this is also used for the MHU payload when passing messages to and from the 1830 SCP. 1831 1832- Another 4 KB page is reserved for passing memory layout between BL1 and BL2 1833 and also the dynamic firmware configurations. 1834 1835- On FVP, BL1 is originally sitting in the Trusted ROM at address ``0x0``. On 1836 Juno, BL1 resides in flash memory at address ``0x0BEC0000``. BL1 read-write 1837 data are relocated to the top of Trusted SRAM at runtime. 1838 1839- BL2 is loaded below BL1 RW 1840 1841- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP_MIN), 1842 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will 1843 overwrite BL1 R/W data and BL2. This implies that BL1 global variables 1844 remain valid only until execution reaches the EL3 Runtime Software entry 1845 point during a cold boot. 1846 1847- On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory 1848 region and transferred to the SCP before being overwritten by EL3 Runtime 1849 Software. 1850 1851- BL32 (for AArch64) can be loaded in one of the following locations: 1852 1853 - Trusted SRAM 1854 - Trusted DRAM (FVP only) 1855 - Secure region of DRAM (top 16MB of DRAM configured by the TrustZone 1856 controller) 1857 1858 When BL32 (for AArch64) is loaded into Trusted SRAM, it is loaded below 1859 BL31. 1860 1861The location of the BL32 image will result in different memory maps. This is 1862illustrated for both FVP and Juno in the following diagrams, using the TSP as 1863an example. 1864 1865.. note:: 1866 Loading the BL32 image in TZC secured DRAM doesn't change the memory 1867 layout of the other images in Trusted SRAM. 1868 1869CONFIG section in memory layouts shown below contains: 1870 1871:: 1872 1873 +--------------------+ 1874 |bl2_mem_params_descs| 1875 |--------------------| 1876 | fw_configs | 1877 +--------------------+ 1878 1879``bl2_mem_params_descs`` contains parameters passed from BL2 to next the 1880BL image during boot. 1881 1882``fw_configs`` includes soc_fw_config, tos_fw_config, tb_fw_config and fw_config. 1883 1884**FVP with TSP in Trusted SRAM with firmware configs :** 1885(These diagrams only cover the AArch64 case) 1886 1887:: 1888 1889 DRAM 1890 0xffffffff +----------+ 1891 | EL3 TZC | 1892 0xffe00000 |----------| (secure) 1893 | AP TZC | 1894 0xff000000 +----------+ 1895 : : 1896 0x82100000 |----------| 1897 |HW_CONFIG | 1898 0x82000000 |----------| (non-secure) 1899 | | 1900 0x80000000 +----------+ 1901 1902 Trusted DRAM 1903 0x08000000 +----------+ 1904 |HW_CONFIG | 1905 0x07f00000 |----------| 1906 : : 1907 | | 1908 0x06000000 +----------+ 1909 1910 Trusted SRAM 1911 0x04040000 +----------+ loaded by BL2 +----------------+ 1912 | BL1 (rw) | <<<<<<<<<<<<< | | 1913 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1914 | BL2 | <<<<<<<<<<<<< | | 1915 |----------| <<<<<<<<<<<<< |----------------| 1916 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1917 | | <<<<<<<<<<<<< |----------------| 1918 | | <<<<<<<<<<<<< | BL32 | 1919 0x04003000 +----------+ +----------------+ 1920 | CONFIG | 1921 0x04001000 +----------+ 1922 | Shared | 1923 0x04000000 +----------+ 1924 1925 Trusted ROM 1926 0x04000000 +----------+ 1927 | BL1 (ro) | 1928 0x00000000 +----------+ 1929 1930**FVP with TSP in Trusted DRAM with firmware configs (default option):** 1931 1932:: 1933 1934 DRAM 1935 0xffffffff +--------------+ 1936 | EL3 TZC | 1937 0xffe00000 |--------------| (secure) 1938 | AP TZC | 1939 0xff000000 +--------------+ 1940 : : 1941 0x82100000 |--------------| 1942 | HW_CONFIG | 1943 0x82000000 |--------------| (non-secure) 1944 | | 1945 0x80000000 +--------------+ 1946 1947 Trusted DRAM 1948 0x08000000 +--------------+ 1949 | HW_CONFIG | 1950 0x07f00000 |--------------| 1951 : : 1952 | BL32 | 1953 0x06000000 +--------------+ 1954 1955 Trusted SRAM 1956 0x04040000 +--------------+ loaded by BL2 +----------------+ 1957 | BL1 (rw) | <<<<<<<<<<<<< | | 1958 |--------------| <<<<<<<<<<<<< | BL31 NOBITS | 1959 | BL2 | <<<<<<<<<<<<< | | 1960 |--------------| <<<<<<<<<<<<< |----------------| 1961 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1962 | | +----------------+ 1963 0x04003000 +--------------+ 1964 | CONFIG | 1965 0x04001000 +--------------+ 1966 | Shared | 1967 0x04000000 +--------------+ 1968 1969 Trusted ROM 1970 0x04000000 +--------------+ 1971 | BL1 (ro) | 1972 0x00000000 +--------------+ 1973 1974**FVP with TSP in TZC-Secured DRAM with firmware configs :** 1975 1976:: 1977 1978 DRAM 1979 0xffffffff +----------+ 1980 | EL3 TZC | 1981 0xffe00000 |----------| (secure) 1982 | AP TZC | 1983 | (BL32) | 1984 0xff000000 +----------+ 1985 | | 1986 0x82100000 |----------| 1987 |HW_CONFIG | 1988 0x82000000 |----------| (non-secure) 1989 | | 1990 0x80000000 +----------+ 1991 1992 Trusted DRAM 1993 0x08000000 +----------+ 1994 |HW_CONFIG | 1995 0x7f000000 |----------| 1996 : : 1997 | | 1998 0x06000000 +----------+ 1999 2000 Trusted SRAM 2001 0x04040000 +----------+ loaded by BL2 +----------------+ 2002 | BL1 (rw) | <<<<<<<<<<<<< | | 2003 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 2004 | BL2 | <<<<<<<<<<<<< | | 2005 |----------| <<<<<<<<<<<<< |----------------| 2006 | | <<<<<<<<<<<<< | BL31 PROGBITS | 2007 | | +----------------+ 2008 0x04003000 +----------+ 2009 | CONFIG | 2010 0x04001000 +----------+ 2011 | Shared | 2012 0x04000000 +----------+ 2013 2014 Trusted ROM 2015 0x04000000 +----------+ 2016 | BL1 (ro) | 2017 0x00000000 +----------+ 2018 2019**Juno with BL32 in Trusted SRAM :** 2020 2021:: 2022 2023 DRAM 2024 0xFFFFFFFF +----------+ 2025 | SCP TZC | 2026 0xFFE00000 |----------| 2027 | EL3 TZC | 2028 0xFFC00000 |----------| (secure) 2029 | AP TZC | 2030 0xFF000000 +----------+ 2031 | | 2032 : : (non-secure) 2033 | | 2034 0x80000000 +----------+ 2035 2036 2037 Flash0 2038 0x0C000000 +----------+ 2039 : : 2040 0x0BED0000 |----------| 2041 | BL1 (ro) | 2042 0x0BEC0000 |----------| 2043 : : 2044 0x08000000 +----------+ BL31 is loaded 2045 after SCP_BL2 has 2046 Trusted SRAM been sent to SCP 2047 0x04040000 +----------+ loaded by BL2 +----------------+ 2048 | BL1 (rw) | <<<<<<<<<<<<< | | 2049 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 2050 | BL2 | <<<<<<<<<<<<< | | 2051 |----------| <<<<<<<<<<<<< |----------------| 2052 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 2053 | | <<<<<<<<<<<<< |----------------| 2054 | | <<<<<<<<<<<<< | BL32 | 2055 | | +----------------+ 2056 | | 2057 0x04001000 +----------+ 2058 | MHU | 2059 0x04000000 +----------+ 2060 2061**Juno with BL32 in TZC-secured DRAM :** 2062 2063:: 2064 2065 DRAM 2066 0xFFFFFFFF +----------+ 2067 | SCP TZC | 2068 0xFFE00000 |----------| 2069 | EL3 TZC | 2070 0xFFC00000 |----------| (secure) 2071 | AP TZC | 2072 | (BL32) | 2073 0xFF000000 +----------+ 2074 | | 2075 : : (non-secure) 2076 | | 2077 0x80000000 +----------+ 2078 2079 Flash0 2080 0x0C000000 +----------+ 2081 : : 2082 0x0BED0000 |----------| 2083 | BL1 (ro) | 2084 0x0BEC0000 |----------| 2085 : : 2086 0x08000000 +----------+ BL31 is loaded 2087 after SCP_BL2 has 2088 Trusted SRAM been sent to SCP 2089 0x04040000 +----------+ loaded by BL2 +----------------+ 2090 | BL1 (rw) | <<<<<<<<<<<<< | | 2091 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 2092 | BL2 | <<<<<<<<<<<<< | | 2093 |----------| <<<<<<<<<<<<< |----------------| 2094 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 2095 | | +----------------+ 2096 0x04001000 +----------+ 2097 | MHU | 2098 0x04000000 +----------+ 2099 2100.. _firmware_design_fip: 2101 2102Firmware Image Package (FIP) 2103---------------------------- 2104 2105Using a Firmware Image Package (FIP) allows for packing bootloader images (and 2106potentially other payloads) into a single archive that can be loaded by TF-A 2107from non-volatile platform storage. A driver to load images from a FIP has 2108been added to the storage layer and allows a package to be read from supported 2109platform storage. A tool to create Firmware Image Packages is also provided 2110and described below. 2111 2112Firmware Image Package layout 2113~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2114 2115The FIP layout consists of a table of contents (ToC) followed by payload data. 2116The ToC itself has a header followed by one or more table entries. The ToC is 2117terminated by an end marker entry, and since the size of the ToC is 0 bytes, 2118the offset equals the total size of the FIP file. All ToC entries describe some 2119payload data that has been appended to the end of the binary package. With the 2120information provided in the ToC entry the corresponding payload data can be 2121retrieved. 2122 2123:: 2124 2125 ------------------ 2126 | ToC Header | 2127 |----------------| 2128 | ToC Entry 0 | 2129 |----------------| 2130 | ToC Entry 1 | 2131 |----------------| 2132 | ToC End Marker | 2133 |----------------| 2134 | | 2135 | Data 0 | 2136 | | 2137 |----------------| 2138 | | 2139 | Data 1 | 2140 | | 2141 ------------------ 2142 2143The ToC header and entry formats are described in the header file 2144``include/tools_share/firmware_image_package.h``. This file is used by both the 2145tool and TF-A. 2146 2147The ToC header has the following fields: 2148 2149:: 2150 2151 `name`: The name of the ToC. This is currently used to validate the header. 2152 `serial_number`: A non-zero number provided by the creation tool 2153 `flags`: Flags associated with this data. 2154 Bits 0-31: Reserved 2155 Bits 32-47: Platform defined 2156 Bits 48-63: Reserved 2157 2158A ToC entry has the following fields: 2159 2160:: 2161 2162 `uuid`: All files are referred to by a pre-defined Universally Unique 2163 IDentifier [UUID] . The UUIDs are defined in 2164 `include/tools_share/firmware_image_package.h`. The platform translates 2165 the requested image name into the corresponding UUID when accessing the 2166 package. 2167 `offset_address`: The offset address at which the corresponding payload data 2168 can be found. The offset is calculated from the ToC base address. 2169 `size`: The size of the corresponding payload data in bytes. 2170 `flags`: Flags associated with this entry. None are yet defined. 2171 2172Firmware Image Package creation tool 2173~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2174 2175The FIP creation tool can be used to pack specified images into a binary 2176package that can be loaded by TF-A from platform storage. The tool currently 2177only supports packing bootloader images. Additional image definitions can be 2178added to the tool as required. 2179 2180The tool can be found in ``tools/fiptool``. 2181 2182Loading from a Firmware Image Package (FIP) 2183~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2184 2185The Firmware Image Package (FIP) driver can load images from a binary package on 2186non-volatile platform storage. For the Arm development platforms, this is 2187currently NOR FLASH. 2188 2189Bootloader images are loaded according to the platform policy as specified by 2190the function ``plat_get_image_source()``. For the Arm development platforms, this 2191means the platform will attempt to load images from a Firmware Image Package 2192located at the start of NOR FLASH0. 2193 2194The Arm development platforms' policy is to only allow loading of a known set of 2195images. The platform policy can be modified to allow additional images. 2196 2197Use of coherent memory in TF-A 2198------------------------------ 2199 2200There might be loss of coherency when physical memory with mismatched 2201shareability, cacheability and memory attributes is accessed by multiple CPUs 2202(refer to section B2.9 of `Arm ARM`_ for more details). This possibility occurs 2203in TF-A during power up/down sequences when coherency, MMU and caches are 2204turned on/off incrementally. 2205 2206TF-A defines coherent memory as a region of memory with Device nGnRE attributes 2207in the translation tables. The translation granule size in TF-A is 4KB. This 2208is the smallest possible size of the coherent memory region. 2209 2210By default, all data structures which are susceptible to accesses with 2211mismatched attributes from various CPUs are allocated in a coherent memory 2212region (refer to section 2.1 of :ref:`Porting Guide`). The coherent memory 2213region accesses are Outer Shareable, non-cacheable and they can be accessed with 2214the Device nGnRE attributes when the MMU is turned on. Hence, at the expense of 2215at least an extra page of memory, TF-A is able to work around coherency issues 2216due to mismatched memory attributes. 2217 2218The alternative to the above approach is to allocate the susceptible data 2219structures in Normal WriteBack WriteAllocate Inner shareable memory. This 2220approach requires the data structures to be designed so that it is possible to 2221work around the issue of mismatched memory attributes by performing software 2222cache maintenance on them. 2223 2224Disabling the use of coherent memory in TF-A 2225~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2226 2227It might be desirable to avoid the cost of allocating coherent memory on 2228platforms which are memory constrained. TF-A enables inclusion of coherent 2229memory in firmware images through the build flag ``USE_COHERENT_MEM``. 2230This flag is enabled by default. It can be disabled to choose the second 2231approach described above. 2232 2233The below sections analyze the data structures allocated in the coherent memory 2234region and the changes required to allocate them in normal memory. 2235 2236Coherent memory usage in PSCI implementation 2237~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2238 2239The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain 2240tree information for state management of power domains. By default, this data 2241structure is allocated in the coherent memory region in TF-A because it can be 2242accessed by multiple CPUs, either with caches enabled or disabled. 2243 2244.. code:: c 2245 2246 typedef struct non_cpu_pwr_domain_node { 2247 /* 2248 * Index of the first CPU power domain node level 0 which has this node 2249 * as its parent. 2250 */ 2251 unsigned int cpu_start_idx; 2252 2253 /* 2254 * Number of CPU power domains which are siblings of the domain indexed 2255 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx 2256 * -> cpu_start_idx + ncpus' have this node as their parent. 2257 */ 2258 unsigned int ncpus; 2259 2260 /* 2261 * Index of the parent power domain node. 2262 */ 2263 unsigned int parent_node; 2264 2265 plat_local_state_t local_state; 2266 2267 unsigned char level; 2268 2269 /* For indexing the psci_lock array*/ 2270 unsigned char lock_index; 2271 } non_cpu_pd_node_t; 2272 2273In order to move this data structure to normal memory, the use of each of its 2274fields must be analyzed. Fields like ``cpu_start_idx``, ``ncpus``, ``parent_node`` 2275``level`` and ``lock_index`` are only written once during cold boot. Hence removing 2276them from coherent memory involves only doing a clean and invalidate of the 2277cache lines after these fields are written. 2278 2279The field ``local_state`` can be concurrently accessed by multiple CPUs in 2280different cache states. A Lamport's Bakery lock ``psci_locks`` is used to ensure 2281mutual exclusion to this field and a clean and invalidate is needed after it 2282is written. 2283 2284Bakery lock data 2285~~~~~~~~~~~~~~~~ 2286 2287The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory 2288and is accessed by multiple CPUs with mismatched attributes. ``bakery_lock_t`` is 2289defined as follows: 2290 2291.. code:: c 2292 2293 typedef struct bakery_lock { 2294 /* 2295 * The lock_data is a bit-field of 2 members: 2296 * Bit[0] : choosing. This field is set when the CPU is 2297 * choosing its bakery number. 2298 * Bits[1 - 15] : number. This is the bakery number allocated. 2299 */ 2300 volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS]; 2301 } bakery_lock_t; 2302 2303It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU 2304fields can be read by all CPUs but only written to by the owning CPU. 2305 2306Depending upon the data cache line size, the per-CPU fields of the 2307``bakery_lock_t`` structure for multiple CPUs may exist on a single cache line. 2308These per-CPU fields can be read and written during lock contention by multiple 2309CPUs with mismatched memory attributes. Since these fields are a part of the 2310lock implementation, they do not have access to any other locking primitive to 2311safeguard against the resulting coherency issues. As a result, simple software 2312cache maintenance is not enough to allocate them in coherent memory. Consider 2313the following example. 2314 2315CPU0 updates its per-CPU field with data cache enabled. This write updates a 2316local cache line which contains a copy of the fields for other CPUs as well. Now 2317CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache 2318disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of 2319its field in any other cache line in the system. This operation will invalidate 2320the update made by CPU0 as well. 2321 2322To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure 2323has been redesigned. The changes utilise the characteristic of Lamport's Bakery 2324algorithm mentioned earlier. The bakery_lock structure only allocates the memory 2325for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks 2326needed for a CPU into a section ``.bakery_lock``. The linker allocates the memory 2327for other cores by using the total size allocated for the bakery_lock section 2328and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to 2329perform software cache maintenance on the lock data structure without running 2330into coherency issues associated with mismatched attributes. 2331 2332The bakery lock data structure ``bakery_info_t`` is defined for use when 2333``USE_COHERENT_MEM`` is disabled as follows: 2334 2335.. code:: c 2336 2337 typedef struct bakery_info { 2338 /* 2339 * The lock_data is a bit-field of 2 members: 2340 * Bit[0] : choosing. This field is set when the CPU is 2341 * choosing its bakery number. 2342 * Bits[1 - 15] : number. This is the bakery number allocated. 2343 */ 2344 volatile uint16_t lock_data; 2345 } bakery_info_t; 2346 2347The ``bakery_info_t`` represents a single per-CPU field of one lock and 2348the combination of corresponding ``bakery_info_t`` structures for all CPUs in the 2349system represents the complete bakery lock. The view in memory for a system 2350with n bakery locks are: 2351 2352:: 2353 2354 .bakery_lock section start 2355 |----------------| 2356 | `bakery_info_t`| <-- Lock_0 per-CPU field 2357 | Lock_0 | for CPU0 2358 |----------------| 2359 | `bakery_info_t`| <-- Lock_1 per-CPU field 2360 | Lock_1 | for CPU0 2361 |----------------| 2362 | .... | 2363 |----------------| 2364 | `bakery_info_t`| <-- Lock_N per-CPU field 2365 | Lock_N | for CPU0 2366 ------------------ 2367 | XXXXX | 2368 | Padding to | 2369 | next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate 2370 | Granule | continuous memory for remaining CPUs. 2371 ------------------ 2372 | `bakery_info_t`| <-- Lock_0 per-CPU field 2373 | Lock_0 | for CPU1 2374 |----------------| 2375 | `bakery_info_t`| <-- Lock_1 per-CPU field 2376 | Lock_1 | for CPU1 2377 |----------------| 2378 | .... | 2379 |----------------| 2380 | `bakery_info_t`| <-- Lock_N per-CPU field 2381 | Lock_N | for CPU1 2382 ------------------ 2383 | XXXXX | 2384 | Padding to | 2385 | next Cache WB | 2386 | Granule | 2387 ------------------ 2388 2389Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an 2390operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1 2391``.bakery_lock`` section need to be fetched and appropriate cache operations need 2392to be performed for each access. 2393 2394On Arm Platforms, bakery locks are used in psci (``psci_locks``) and power controller 2395driver (``arm_lock``). 2396 2397Non Functional Impact of removing coherent memory 2398~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2399 2400Removal of the coherent memory region leads to the additional software overhead 2401of performing cache maintenance for the affected data structures. However, since 2402the memory where the data structures are allocated is cacheable, the overhead is 2403mostly mitigated by an increase in performance. 2404 2405There is however a performance impact for bakery locks, due to: 2406 2407- Additional cache maintenance operations, and 2408- Multiple cache line reads for each lock operation, since the bakery locks 2409 for each CPU are distributed across different cache lines. 2410 2411The implementation has been optimized to minimize this additional overhead. 2412Measurements indicate that when bakery locks are allocated in Normal memory, the 2413minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas 2414in Device memory the same is 2 micro seconds. The measurements were done on the 2415Juno Arm development platform. 2416 2417As mentioned earlier, almost a page of memory can be saved by disabling 2418``USE_COHERENT_MEM``. Each platform needs to consider these trade-offs to decide 2419whether coherent memory should be used. If a platform disables 2420``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can 2421optionally define macro ``PLAT_PERCPU_BAKERY_LOCK_SIZE`` (see the 2422:ref:`Porting Guide`). Refer to the reference platform code for examples. 2423 2424Isolating code and read-only data on separate memory pages 2425---------------------------------------------------------- 2426 2427In the Armv8-A VMSA, translation table entries include fields that define the 2428properties of the target memory region, such as its access permissions. The 2429smallest unit of memory that can be addressed by a translation table entry is 2430a memory page. Therefore, if software needs to set different permissions on two 2431memory regions then it needs to map them using different memory pages. 2432 2433The default memory layout for each BL image is as follows: 2434 2435:: 2436 2437 | ... | 2438 +-------------------+ 2439 | Read-write data | 2440 +-------------------+ Page boundary 2441 | <Padding> | 2442 +-------------------+ 2443 | Exception vectors | 2444 +-------------------+ 2 KB boundary 2445 | <Padding> | 2446 +-------------------+ 2447 | Read-only data | 2448 +-------------------+ 2449 | Code | 2450 +-------------------+ BLx_BASE 2451 2452.. note:: 2453 The 2KB alignment for the exception vectors is an architectural 2454 requirement. 2455 2456The read-write data start on a new memory page so that they can be mapped with 2457read-write permissions, whereas the code and read-only data below are configured 2458as read-only. 2459 2460However, the read-only data are not aligned on a page boundary. They are 2461contiguous to the code. Therefore, the end of the code section and the beginning 2462of the read-only data one might share a memory page. This forces both to be 2463mapped with the same memory attributes. As the code needs to be executable, this 2464means that the read-only data stored on the same memory page as the code are 2465executable as well. This could potentially be exploited as part of a security 2466attack. 2467 2468TF provides the build flag ``SEPARATE_CODE_AND_RODATA`` to isolate the code and 2469read-only data on separate memory pages. This in turn allows independent control 2470of the access permissions for the code and read-only data. In this case, 2471platform code gets a finer-grained view of the image layout and can 2472appropriately map the code region as executable and the read-only data as 2473execute-never. 2474 2475This has an impact on memory footprint, as padding bytes need to be introduced 2476between the code and read-only data to ensure the segregation of the two. To 2477limit the memory cost, this flag also changes the memory layout such that the 2478code and exception vectors are now contiguous, like so: 2479 2480:: 2481 2482 | ... | 2483 +-------------------+ 2484 | Read-write data | 2485 +-------------------+ Page boundary 2486 | <Padding> | 2487 +-------------------+ 2488 | Read-only data | 2489 +-------------------+ Page boundary 2490 | <Padding> | 2491 +-------------------+ 2492 | Exception vectors | 2493 +-------------------+ 2 KB boundary 2494 | <Padding> | 2495 +-------------------+ 2496 | Code | 2497 +-------------------+ BLx_BASE 2498 2499With this more condensed memory layout, the separation of read-only data will 2500add zero or one page to the memory footprint of each BL image. Each platform 2501should consider the trade-off between memory footprint and security. 2502 2503This build flag is disabled by default, minimising memory footprint. On Arm 2504platforms, it is enabled. 2505 2506Publish and Subscribe Framework 2507------------------------------- 2508 2509The Publish and Subscribe Framework allows EL3 components to define and publish 2510events, to which other EL3 components can subscribe. 2511 2512The following macros are provided by the framework: 2513 2514- ``REGISTER_PUBSUB_EVENT(event)``: Defines an event, and takes one argument, 2515 the event name, which must be a valid C identifier. All calls to 2516 ``REGISTER_PUBSUB_EVENT`` macro must be placed in the file 2517 ``pubsub_events.h``. 2518 2519- ``PUBLISH_EVENT_ARG(event, arg)``: Publishes a defined event, by iterating 2520 subscribed handlers and calling them in turn. The handlers will be passed the 2521 parameter ``arg``. The expected use-case is to broadcast an event. 2522 2523- ``PUBLISH_EVENT(event)``: Like ``PUBLISH_EVENT_ARG``, except that the value 2524 ``NULL`` is passed to subscribed handlers. 2525 2526- ``SUBSCRIBE_TO_EVENT(event, handler)``: Registers the ``handler`` to 2527 subscribe to ``event``. The handler will be executed whenever the ``event`` 2528 is published. 2529 2530- ``for_each_subscriber(event, subscriber)``: Iterates through all handlers 2531 subscribed for ``event``. ``subscriber`` must be a local variable of type 2532 ``pubsub_cb_t *``, and will point to each subscribed handler in turn during 2533 iteration. This macro can be used for those patterns that none of the 2534 ``PUBLISH_EVENT_*()`` macros cover. 2535 2536Publishing an event that wasn't defined using ``REGISTER_PUBSUB_EVENT`` will 2537result in build error. Subscribing to an undefined event however won't. 2538 2539Subscribed handlers must be of type ``pubsub_cb_t``, with following function 2540signature: 2541 2542.. code:: c 2543 2544 typedef void* (*pubsub_cb_t)(const void *arg); 2545 2546There may be arbitrary number of handlers registered to the same event. The 2547order in which subscribed handlers are notified when that event is published is 2548not defined. Subscribed handlers may be executed in any order; handlers should 2549not assume any relative ordering amongst them. 2550 2551Publishing an event on a PE will result in subscribed handlers executing on that 2552PE only; it won't cause handlers to execute on a different PE. 2553 2554Note that publishing an event on a PE blocks until all the subscribed handlers 2555finish executing on the PE. 2556 2557TF-A generic code publishes and subscribes to some events within. Platform 2558ports are discouraged from subscribing to them. These events may be withdrawn, 2559renamed, or have their semantics altered in the future. Platforms may however 2560register, publish, and subscribe to platform-specific events. 2561 2562Publish and Subscribe Example 2563~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2564 2565A publisher that wants to publish event ``foo`` would: 2566 2567- Define the event ``foo`` in the ``pubsub_events.h``. 2568 2569 .. code:: c 2570 2571 REGISTER_PUBSUB_EVENT(foo); 2572 2573- Depending on the nature of event, use one of ``PUBLISH_EVENT_*()`` macros to 2574 publish the event at the appropriate path and time of execution. 2575 2576A subscriber that wants to subscribe to event ``foo`` published above would 2577implement: 2578 2579.. code:: c 2580 2581 void *foo_handler(const void *arg) 2582 { 2583 void *result; 2584 2585 /* Do handling ... */ 2586 2587 return result; 2588 } 2589 2590 SUBSCRIBE_TO_EVENT(foo, foo_handler); 2591 2592 2593Reclaiming the BL31 initialization code 2594~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2595 2596A significant amount of the code used for the initialization of BL31 is never 2597needed again after boot time. In order to reduce the runtime memory 2598footprint, the memory used for this code can be reclaimed after initialization 2599has finished and be used for runtime data. 2600 2601The build option ``RECLAIM_INIT_CODE`` can be set to mark this boot time code 2602with a ``.text.init.*`` attribute which can be filtered and placed suitably 2603within the BL image for later reclamation by the platform. The platform can 2604specify the filter and the memory region for this init section in BL31 via the 2605plat.ld.S linker script. For example, on the FVP, this section is placed 2606overlapping the secondary CPU stacks so that after the cold boot is done, this 2607memory can be reclaimed for the stacks. The init memory section is initially 2608mapped with ``RO``, ``EXECUTE`` attributes. After BL31 initialization has 2609completed, the FVP changes the attributes of this section to ``RW``, 2610``EXECUTE_NEVER`` allowing it to be used for runtime data. The memory attributes 2611are changed within the ``bl31_plat_runtime_setup`` platform hook. The init 2612section section can be reclaimed for any data which is accessed after cold 2613boot initialization and it is upto the platform to make the decision. 2614 2615Please note that this will disable inlining for any functions with the __init 2616attribute. 2617 2618.. _firmware_design_pmf: 2619 2620Performance Measurement Framework 2621--------------------------------- 2622 2623The Performance Measurement Framework (PMF) facilitates collection of 2624timestamps by registered services and provides interfaces to retrieve them 2625from within TF-A. A platform can choose to expose appropriate SMCs to 2626retrieve these collected timestamps. 2627 2628By default, the global physical counter is used for the timestamp 2629value and is read via ``CNTPCT_EL0``. The framework allows to retrieve 2630timestamps captured by other CPUs. 2631 2632Timestamp identifier format 2633~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2634 2635A PMF timestamp is uniquely identified across the system via the 2636timestamp ID or ``tid``. The ``tid`` is composed as follows: 2637 2638:: 2639 2640 Bits 0-7: The local timestamp identifier. 2641 Bits 8-9: Reserved. 2642 Bits 10-15: The service identifier. 2643 Bits 16-31: Reserved. 2644 2645#. The service identifier. Each PMF service is identified by a 2646 service name and a service identifier. Both the service name and 2647 identifier are unique within the system as a whole. 2648 2649#. The local timestamp identifier. This identifier is unique within a given 2650 service. 2651 2652Registering a PMF service 2653~~~~~~~~~~~~~~~~~~~~~~~~~ 2654 2655To register a PMF service, the ``PMF_REGISTER_SERVICE()`` macro from ``pmf.h`` 2656is used. The arguments required are the service name, the service ID, 2657the total number of local timestamps to be captured and a set of flags. 2658 2659The ``flags`` field can be specified as a bitwise-OR of the following values: 2660 2661:: 2662 2663 PMF_STORE_ENABLE: The timestamp is stored in memory for later retrieval. 2664 PMF_DUMP_ENABLE: The timestamp is dumped on the serial console. 2665 2666The ``PMF_REGISTER_SERVICE()`` reserves memory to store captured 2667timestamps in a PMF specific linker section at build time. 2668Additionally, it defines necessary functions to capture and 2669retrieve a particular timestamp for the given service at runtime. 2670 2671The macro ``PMF_REGISTER_SERVICE()`` only enables capturing PMF timestamps 2672from within TF-A. In order to retrieve timestamps from outside of TF-A, the 2673``PMF_REGISTER_SERVICE_SMC()`` macro must be used instead. This macro 2674accepts the same set of arguments as the ``PMF_REGISTER_SERVICE()`` 2675macro but additionally supports retrieving timestamps using SMCs. 2676 2677Capturing a timestamp 2678~~~~~~~~~~~~~~~~~~~~~ 2679 2680PMF timestamps are stored in a per-service timestamp region. On a 2681system with multiple CPUs, each timestamp is captured and stored 2682in a per-CPU cache line aligned memory region. 2683 2684Having registered the service, the ``PMF_CAPTURE_TIMESTAMP()`` macro can be 2685used to capture a timestamp at the location where it is used. The macro 2686takes the service name, a local timestamp identifier and a flag as arguments. 2687 2688The ``flags`` field argument can be zero, or ``PMF_CACHE_MAINT`` which 2689instructs PMF to do cache maintenance following the capture. Cache 2690maintenance is required if any of the service's timestamps are captured 2691with data cache disabled. 2692 2693To capture a timestamp in assembly code, the caller should use 2694``pmf_calc_timestamp_addr`` macro (defined in ``pmf_asm_macros.S``) to 2695calculate the address of where the timestamp would be stored. The 2696caller should then read ``CNTPCT_EL0`` register to obtain the timestamp 2697and store it at the determined address for later retrieval. 2698 2699Retrieving a timestamp 2700~~~~~~~~~~~~~~~~~~~~~~ 2701 2702From within TF-A, timestamps for individual CPUs can be retrieved using either 2703``PMF_GET_TIMESTAMP_BY_MPIDR()`` or ``PMF_GET_TIMESTAMP_BY_INDEX()`` macros. 2704These macros accept the CPU's MPIDR value, or its ordinal position 2705respectively. 2706 2707From outside TF-A, timestamps for individual CPUs can be retrieved by calling 2708into ``pmf_smc_handler()``. 2709 2710:: 2711 2712 Interface : pmf_smc_handler() 2713 Argument : unsigned int smc_fid, u_register_t x1, 2714 u_register_t x2, u_register_t x3, 2715 u_register_t x4, void *cookie, 2716 void *handle, u_register_t flags 2717 Return : uintptr_t 2718 2719 smc_fid: Holds the SMC identifier which is either `PMF_SMC_GET_TIMESTAMP_32` 2720 when the caller of the SMC is running in AArch32 mode 2721 or `PMF_SMC_GET_TIMESTAMP_64` when the caller is running in AArch64 mode. 2722 x1: Timestamp identifier. 2723 x2: The `mpidr` of the CPU for which the timestamp has to be retrieved. 2724 This can be the `mpidr` of a different core to the one initiating 2725 the SMC. In that case, service specific cache maintenance may be 2726 required to ensure the updated copy of the timestamp is returned. 2727 x3: A flags value that is either 0 or `PMF_CACHE_MAINT`. If 2728 `PMF_CACHE_MAINT` is passed, then the PMF code will perform a 2729 cache invalidate before reading the timestamp. This ensures 2730 an updated copy is returned. 2731 2732The remaining arguments, ``x4``, ``cookie``, ``handle`` and ``flags`` are unused 2733in this implementation. 2734 2735PMF code structure 2736~~~~~~~~~~~~~~~~~~ 2737 2738#. ``pmf_main.c`` consists of core functions that implement service registration, 2739 initialization, storing, dumping and retrieving timestamps. 2740 2741#. ``pmf_smc.c`` contains the SMC handling for registered PMF services. 2742 2743#. ``pmf.h`` contains the public interface to Performance Measurement Framework. 2744 2745#. ``pmf_asm_macros.S`` consists of macros to facilitate capturing timestamps in 2746 assembly code. 2747 2748#. ``pmf_helpers.h`` is an internal header used by ``pmf.h``. 2749 2750Armv8-A Architecture Extensions 2751------------------------------- 2752 2753TF-A makes use of Armv8-A Architecture Extensions where applicable. This 2754section lists the usage of Architecture Extensions, and build flags 2755controlling them. 2756 2757Build options 2758~~~~~~~~~~~~~ 2759 2760``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` 2761 2762These build options serve dual purpose 2763 2764- Determine the architecture extension support in TF-A build: All the mandatory 2765 architectural features up to ``ARM_ARCH_MAJOR.ARM_ARCH_MINOR`` are included 2766 and unconditionally enabled by TF-A build system. 2767 2768- ``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` are passed to a march.mk build utility 2769 this will try to come up with an appropriate -march value to be passed to compiler 2770 by probing the compiler and checking what's supported by the compiler and what's best 2771 that can be used. But if platform provides a ``MARCH_DIRECTIVE`` then it will used 2772 directly and compiler probing will be skipped. 2773 2774The build system requires that the platform provides a valid numeric value based on 2775CPU architecture extension, otherwise it defaults to base Armv8.0-A architecture. 2776Subsequent Arm Architecture versions also support extensions which were introduced 2777in previous versions. 2778 2779.. seealso:: :ref:`Build Options` 2780 2781For details on the Architecture Extension and available features, please refer 2782to the respective Architecture Extension Supplement. 2783 2784Armv8.1-A 2785~~~~~~~~~ 2786 2787This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when 2788``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` >= 1. 2789 2790- By default, a load-/store-exclusive instruction pair is used to implement 2791 spinlocks. The ``USE_SPINLOCK_CAS`` build option when set to 1 selects the 2792 spinlock implementation using the ARMv8.1-LSE Compare and Swap instruction. 2793 Notice this instruction is only available in AArch64 execution state, so 2794 the option is only available to AArch64 builds. 2795 2796Armv8.2-A 2797~~~~~~~~~ 2798 2799- The presence of ARMv8.2-TTCNP is detected at runtime. When it is present, the 2800 Common not Private (TTBRn_ELx.CnP) bit is enabled to indicate that multiple 2801 Processing Elements in the same Inner Shareable domain use the same 2802 translation table entries for a given stage of translation for a particular 2803 translation regime. 2804 2805Armv8.3-A 2806~~~~~~~~~ 2807 2808- Pointer authentication features of Armv8.3-A are unconditionally enabled in 2809 the Non-secure world so that lower ELs are allowed to use them without 2810 causing a trap to EL3. 2811 2812 In order to enable the Secure world to use it, ``CTX_INCLUDE_PAUTH_REGS`` 2813 must be set to 1. This will add all pointer authentication system registers 2814 to the context that is saved when doing a world switch. 2815 2816 The TF-A itself has support for pointer authentication at runtime 2817 that can be enabled by setting ``BRANCH_PROTECTION`` option to non-zero and 2818 ``CTX_INCLUDE_PAUTH_REGS`` to 1. This enables pointer authentication in BL1, 2819 BL2, BL31, and the TSP if it is used. 2820 2821 Note that Pointer Authentication is enabled for Non-secure world irrespective 2822 of the value of these build flags if the CPU supports it. 2823 2824 If ``ARM_ARCH_MAJOR == 8`` and ``ARM_ARCH_MINOR >= 3`` the code footprint of 2825 enabling PAuth is lower because the compiler will use the optimized 2826 PAuth instructions rather than the backwards-compatible ones. 2827 2828Armv8.5-A 2829~~~~~~~~~ 2830 2831- Branch Target Identification feature is selected by ``BRANCH_PROTECTION`` 2832 option set to 1. This option defaults to 0. 2833 2834- Memory Tagging Extension feature has few variants but not all of them require 2835 enablement from EL3 to be used at lower EL. e.g. Memory tagging only at 2836 EL0(MTE) does not require EL3 configuration however memory tagging at 2837 EL2/EL1 (MTE2) does require EL3 enablement and we need to set this option 2838 ``ENABLE_FEAT_MTE2`` to 1. This option defaults to 0. 2839 2840Armv7-A 2841~~~~~~~ 2842 2843This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 7. 2844 2845There are several Armv7-A extensions available. Obviously the TrustZone 2846extension is mandatory to support the TF-A bootloader and runtime services. 2847 2848Platform implementing an Armv7-A system can to define from its target 2849Cortex-A architecture through ``ARM_CORTEX_A<X> = yes`` in their 2850``platform.mk`` script. For example ``ARM_CORTEX_A15=yes`` for a 2851Cortex-A15 target. 2852 2853Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support. 2854Note that using neon at runtime has constraints on non secure world context. 2855TF-A does not yet provide VFP context management. 2856 2857Directive ``ARM_CORTEX_A<x>`` and ``ARM_WITH_NEON`` are used to set 2858the toolchain target architecture directive. 2859 2860Platform may choose to not define straight the toolchain target architecture 2861directive by defining ``MARCH_DIRECTIVE``. 2862I.e: 2863 2864.. code:: make 2865 2866 MARCH_DIRECTIVE := -march=armv7-a 2867 2868Code Structure 2869-------------- 2870 2871TF-A code is logically divided between the three boot loader stages mentioned 2872in the previous sections. The code is also divided into the following 2873categories (present as directories in the source code): 2874 2875- **Platform specific.** Choice of architecture specific code depends upon 2876 the platform. 2877- **Common code.** This is platform and architecture agnostic code. 2878- **Library code.** This code comprises of functionality commonly used by all 2879 other code. The PSCI implementation and other EL3 runtime frameworks reside 2880 as Library components. 2881- **Stage specific.** Code specific to a boot stage. 2882- **Drivers.** 2883- **Services.** EL3 runtime services (eg: SPD). Specific SPD services 2884 reside in the ``services/spd`` directory (e.g. ``services/spd/tspd``). 2885 2886Each boot loader stage uses code from one or more of the above mentioned 2887categories. Based upon the above, the code layout looks like this: 2888 2889:: 2890 2891 Directory Used by BL1? Used by BL2? Used by BL31? 2892 bl1 Yes No No 2893 bl2 No Yes No 2894 bl31 No No Yes 2895 plat Yes Yes Yes 2896 drivers Yes No Yes 2897 common Yes Yes Yes 2898 lib Yes Yes Yes 2899 services No No Yes 2900 2901The build system provides a non configurable build option IMAGE_BLx for each 2902boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE_BL1 will be 2903defined by the build system. This enables TF-A to compile certain code only 2904for specific boot loader stages 2905 2906All assembler files have the ``.S`` extension. The linker source files for each 2907boot stage have the extension ``.ld.S``. These are processed by GCC to create the 2908linker scripts which have the extension ``.ld``. 2909 2910FDTs provide a description of the hardware platform and are used by the Linux 2911kernel at boot time. These can be found in the ``fdts`` directory. 2912 2913.. rubric:: References 2914 2915- `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D)`_ 2916 2917- `PSCI`_ 2918 2919- `SMC Calling Convention`_ 2920 2921- :ref:`Interrupt Management Framework` 2922 2923-------------- 2924 2925*Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.* 2926 2927.. _SMCCC: https://developer.arm.com/docs/den0028/latest 2928.. _PSCI: https://developer.arm.com/documentation/den0022/latest/ 2929.. _Arm ARM: https://developer.arm.com/docs/ddi0487/latest 2930.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest 2931.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D): https://developer.arm.com/docs/den0006/latest 2932.. _Arm Confidential Compute Architecture (Arm CCA): https://www.arm.com/why-arm/architecture/security-features/arm-confidential-compute-architecture 2933.. _AArch64 exception vector table: https://developer.arm.com/documentation/100933/0100/AArch64-exception-vector-table 2934 2935.. |Image 1| image:: ../resources/diagrams/rt-svc-descs-layout.png 2936
