1Firmware Design 2=============== 3 4.. contents:: 5 6Trusted Firmware-A (TF-A) implements a subset of the Trusted Board Boot 7Requirements (TBBR) Platform Design Document (PDD) [1]_ for Arm reference 8platforms. The TBB sequence starts when the platform is powered on and runs up 9to the stage where it hands-off control to firmware running in the normal 10world in DRAM. This is the cold boot path. 11 12TF-A also implements the Power State Coordination Interface PDD [2]_ as a 13runtime service. PSCI is the interface from normal world software to firmware 14implementing power management use-cases (for example, secondary CPU boot, 15hotplug and idle). Normal world software can access TF-A runtime services via 16the Arm SMC (Secure Monitor Call) instruction. The SMC instruction must be 17used as mandated by the SMC Calling Convention [3]_. 18 19TF-A implements a framework for configuring and managing interrupts generated 20in either security state. The details of the interrupt management framework 21and its design can be found in TF-A Interrupt Management Design guide [4]_. 22 23TF-A also implements a library for setting up and managing the translation 24tables. The details of this library can be found in `Xlat_tables design`_. 25 26TF-A can be built to support either AArch64 or AArch32 execution state. 27 28Cold boot 29--------- 30 31The cold boot path starts when the platform is physically turned on. If 32``COLD_BOOT_SINGLE_CPU=0``, one of the CPUs released from reset is chosen as the 33primary CPU, and the remaining CPUs are considered secondary CPUs. The primary 34CPU is chosen through platform-specific means. The cold boot path is mainly 35executed by the primary CPU, other than essential CPU initialization executed by 36all CPUs. The secondary CPUs are kept in a safe platform-specific state until 37the primary CPU has performed enough initialization to boot them. 38 39Refer to the `Reset Design`_ for more information on the effect of the 40``COLD_BOOT_SINGLE_CPU`` platform build option. 41 42The cold boot path in this implementation of TF-A depends on the execution 43state. For AArch64, it is divided into five steps (in order of execution): 44 45- Boot Loader stage 1 (BL1) *AP Trusted ROM* 46- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 47- Boot Loader stage 3-1 (BL31) *EL3 Runtime Software* 48- Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional) 49- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 50 51For AArch32, it is divided into four steps (in order of execution): 52 53- Boot Loader stage 1 (BL1) *AP Trusted ROM* 54- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 55- Boot Loader stage 3-2 (BL32) *EL3 Runtime Software* 56- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 57 58Arm development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a 59combination of the following types of memory regions. Each bootloader stage uses 60one or more of these memory regions. 61 62- Regions accessible from both non-secure and secure states. For example, 63 non-trusted SRAM, ROM and DRAM. 64- Regions accessible from only the secure state. For example, trusted SRAM and 65 ROM. The FVPs also implement the trusted DRAM which is statically 66 configured. Additionally, the Base FVPs and Juno development platform 67 configure the TrustZone Controller (TZC) to create a region in the DRAM 68 which is accessible only from the secure state. 69 70The sections below provide the following details: 71 72- dynamic configuration of Boot Loader stages 73- initialization and execution of the first three stages during cold boot 74- specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for 75 AArch32) entrypoint requirements for use by alternative Trusted Boot 76 Firmware in place of the provided BL1 and BL2 77 78Dynamic Configuration during cold boot 79~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 80 81Each of the Boot Loader stages may be dynamically configured if required by the 82platform. The Boot Loader stage may optionally specify a firmware 83configuration file and/or hardware configuration file as listed below: 84 85- HW_CONFIG - The hardware configuration file. Can be shared by all Boot Loader 86 stages and also by the Normal World Rich OS. 87- TB_FW_CONFIG - Trusted Boot Firmware configuration file. Shared between BL1 88 and BL2. 89- SOC_FW_CONFIG - SoC Firmware configuration file. Used by BL31. 90- TOS_FW_CONFIG - Trusted OS Firmware configuration file. Used by Trusted OS 91 (BL32). 92- NT_FW_CONFIG - Non Trusted Firmware configuration file. Used by Non-trusted 93 firmware (BL33). 94 95The Arm development platforms use the Flattened Device Tree format for the 96dynamic configuration files. 97 98Each Boot Loader stage can pass up to 4 arguments via registers to the next 99stage. BL2 passes the list of the next images to execute to the *EL3 Runtime 100Software* (BL31 for AArch64 and BL32 for AArch32) via `arg0`. All the other 101arguments are platform defined. The Arm development platforms use the following 102convention: 103 104- BL1 passes the address of a meminfo_t structure to BL2 via ``arg1``. This 105 structure contains the memory layout available to BL2. 106- When dynamic configuration files are present, the firmware configuration for 107 the next Boot Loader stage is populated in the first available argument and 108 the generic hardware configuration is passed the next available argument. 109 For example, 110 111 - If TB_FW_CONFIG is loaded by BL1, then its address is passed in ``arg0`` 112 to BL2. 113 - If HW_CONFIG is loaded by BL1, then its address is passed in ``arg2`` to 114 BL2. Note, ``arg1`` is already used for meminfo_t. 115 - If SOC_FW_CONFIG is loaded by BL2, then its address is passed in ``arg1`` 116 to BL31. Note, ``arg0`` is used to pass the list of executable images. 117 - Similarly, if HW_CONFIG is loaded by BL1 or BL2, then its address is 118 passed in ``arg2`` to BL31. 119 - For other BL3x images, if the firmware configuration file is loaded by 120 BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded 121 then its address is passed in ``arg1``. 122 123BL1 124~~~ 125 126This stage begins execution from the platform's reset vector at EL3. The reset 127address is platform dependent but it is usually located in a Trusted ROM area. 128The BL1 data section is copied to trusted SRAM at runtime. 129 130On the Arm development platforms, BL1 code starts execution from the reset 131vector defined by the constant ``BL1_RO_BASE``. The BL1 data section is copied 132to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``. 133 134The functionality implemented by this stage is as follows. 135 136Determination of boot path 137^^^^^^^^^^^^^^^^^^^^^^^^^^ 138 139Whenever a CPU is released from reset, BL1 needs to distinguish between a warm 140boot and a cold boot. This is done using platform-specific mechanisms (see the 141``plat_get_my_entrypoint()`` function in the `Porting Guide`_). In the case of a 142warm boot, a CPU is expected to continue execution from a separate 143entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe 144platform-specific state (see the ``plat_secondary_cold_boot_setup()`` function in 145the `Porting Guide`_) while the primary CPU executes the remaining cold boot path 146as described in the following sections. 147 148This step only applies when ``PROGRAMMABLE_RESET_ADDRESS=0``. Refer to the 149`Reset Design`_ for more information on the effect of the 150``PROGRAMMABLE_RESET_ADDRESS`` platform build option. 151 152Architectural initialization 153^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 154 155BL1 performs minimal architectural initialization as follows. 156 157- Exception vectors 158 159 BL1 sets up simple exception vectors for both synchronous and asynchronous 160 exceptions. The default behavior upon receiving an exception is to populate 161 a status code in the general purpose register ``X0/R0`` and call the 162 ``plat_report_exception()`` function (see the `Porting Guide`_). The status 163 code is one of: 164 165 For AArch64: 166 167 :: 168 169 0x0 : Synchronous exception from Current EL with SP_EL0 170 0x1 : IRQ exception from Current EL with SP_EL0 171 0x2 : FIQ exception from Current EL with SP_EL0 172 0x3 : System Error exception from Current EL with SP_EL0 173 0x4 : Synchronous exception from Current EL with SP_ELx 174 0x5 : IRQ exception from Current EL with SP_ELx 175 0x6 : FIQ exception from Current EL with SP_ELx 176 0x7 : System Error exception from Current EL with SP_ELx 177 0x8 : Synchronous exception from Lower EL using aarch64 178 0x9 : IRQ exception from Lower EL using aarch64 179 0xa : FIQ exception from Lower EL using aarch64 180 0xb : System Error exception from Lower EL using aarch64 181 0xc : Synchronous exception from Lower EL using aarch32 182 0xd : IRQ exception from Lower EL using aarch32 183 0xe : FIQ exception from Lower EL using aarch32 184 0xf : System Error exception from Lower EL using aarch32 185 186 For AArch32: 187 188 :: 189 190 0x10 : User mode 191 0x11 : FIQ mode 192 0x12 : IRQ mode 193 0x13 : SVC mode 194 0x16 : Monitor mode 195 0x17 : Abort mode 196 0x1a : Hypervisor mode 197 0x1b : Undefined mode 198 0x1f : System mode 199 200 The ``plat_report_exception()`` implementation on the Arm FVP port programs 201 the Versatile Express System LED register in the following format to 202 indicate the occurrence of an unexpected exception: 203 204 :: 205 206 SYS_LED[0] - Security state (Secure=0/Non-Secure=1) 207 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0) 208 For AArch32 it is always 0x0 209 SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value 210 of the status code 211 212 A write to the LED register reflects in the System LEDs (S6LED0..7) in the 213 CLCD window of the FVP. 214 215 BL1 does not expect to receive any exceptions other than the SMC exception. 216 For the latter, BL1 installs a simple stub. The stub expects to receive a 217 limited set of SMC types (determined by their function IDs in the general 218 purpose register ``X0/R0``): 219 220 - ``BL1_SMC_RUN_IMAGE``: This SMC is raised by BL2 to make BL1 pass control 221 to EL3 Runtime Software. 222 - All SMCs listed in section "BL1 SMC Interface" in the `Firmware Update`_ 223 Design Guide are supported for AArch64 only. These SMCs are currently 224 not supported when BL1 is built for AArch32. 225 226 Any other SMC leads to an assertion failure. 227 228- CPU initialization 229 230 BL1 calls the ``reset_handler()`` function which in turn calls the CPU 231 specific reset handler function (see the section: "CPU specific operations 232 framework"). 233 234- Control register setup (for AArch64) 235 236 - ``SCTLR_EL3``. Instruction cache is enabled by setting the ``SCTLR_EL3.I`` 237 bit. Alignment and stack alignment checking is enabled by setting the 238 ``SCTLR_EL3.A`` and ``SCTLR_EL3.SA`` bits. Exception endianness is set to 239 little-endian by clearing the ``SCTLR_EL3.EE`` bit. 240 241 - ``SCR_EL3``. The register width of the next lower exception level is set 242 to AArch64 by setting the ``SCR.RW`` bit. The ``SCR.EA`` bit is set to trap 243 both External Aborts and SError Interrupts in EL3. The ``SCR.SIF`` bit is 244 also set to disable instruction fetches from Non-secure memory when in 245 secure state. 246 247 - ``CPTR_EL3``. Accesses to the ``CPACR_EL1`` register from EL1 or EL2, or the 248 ``CPTR_EL2`` register from EL2 are configured to not trap to EL3 by 249 clearing the ``CPTR_EL3.TCPAC`` bit. Access to the trace functionality is 250 configured not to trap to EL3 by clearing the ``CPTR_EL3.TTA`` bit. 251 Instructions that access the registers associated with Floating Point 252 and Advanced SIMD execution are configured to not trap to EL3 by 253 clearing the ``CPTR_EL3.TFP`` bit. 254 255 - ``DAIF``. The SError interrupt is enabled by clearing the SError interrupt 256 mask bit. 257 258 - ``MDCR_EL3``. The trap controls, ``MDCR_EL3.TDOSA``, ``MDCR_EL3.TDA`` and 259 ``MDCR_EL3.TPM``, are set so that accesses to the registers they control 260 do not trap to EL3. AArch64 Secure self-hosted debug is disabled by 261 setting the ``MDCR_EL3.SDD`` bit. Also ``MDCR_EL3.SPD32`` is set to 262 disable AArch32 Secure self-hosted privileged debug from S-EL1. 263 264- Control register setup (for AArch32) 265 266 - ``SCTLR``. Instruction cache is enabled by setting the ``SCTLR.I`` bit. 267 Alignment checking is enabled by setting the ``SCTLR.A`` bit. 268 Exception endianness is set to little-endian by clearing the 269 ``SCTLR.EE`` bit. 270 271 - ``SCR``. The ``SCR.SIF`` bit is set to disable instruction fetches from 272 Non-secure memory when in secure state. 273 274 - ``CPACR``. Allow execution of Advanced SIMD instructions at PL0 and PL1, 275 by clearing the ``CPACR.ASEDIS`` bit. Access to the trace functionality 276 is configured not to trap to undefined mode by clearing the 277 ``CPACR.TRCDIS`` bit. 278 279 - ``NSACR``. Enable non-secure access to Advanced SIMD functionality and 280 system register access to implemented trace registers. 281 282 - ``FPEXC``. Enable access to the Advanced SIMD and floating-point 283 functionality from all Exception levels. 284 285 - ``CPSR.A``. The Asynchronous data abort interrupt is enabled by clearing 286 the Asynchronous data abort interrupt mask bit. 287 288 - ``SDCR``. The ``SDCR.SPD`` field is set to disable AArch32 Secure 289 self-hosted privileged debug. 290 291Platform initialization 292^^^^^^^^^^^^^^^^^^^^^^^ 293 294On Arm platforms, BL1 performs the following platform initializations: 295 296- Enable the Trusted Watchdog. 297- Initialize the console. 298- Configure the Interconnect to enable hardware coherency. 299- Enable the MMU and map the memory it needs to access. 300- Configure any required platform storage to load the next bootloader image 301 (BL2). 302- If the BL1 dynamic configuration file, ``TB_FW_CONFIG``, is available, then 303 load it to the platform defined address and make it available to BL2 via 304 ``arg0``. 305- Configure the system timer and program the `CNTFRQ_EL0` for use by NS-BL1U 306 and NS-BL2U firmware update images. 307 308Firmware Update detection and execution 309^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 310 311After performing platform setup, BL1 common code calls 312``bl1_plat_get_next_image_id()`` to determine if `Firmware Update`_ is required or 313to proceed with the normal boot process. If the platform code returns 314``BL2_IMAGE_ID`` then the normal boot sequence is executed as described in the 315next section, else BL1 assumes that `Firmware Update`_ is required and execution 316passes to the first image in the `Firmware Update`_ process. In either case, BL1 317retrieves a descriptor of the next image by calling ``bl1_plat_get_image_desc()``. 318The image descriptor contains an ``entry_point_info_t`` structure, which BL1 319uses to initialize the execution state of the next image. 320 321BL2 image load and execution 322^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 323 324In the normal boot flow, BL1 execution continues as follows: 325 326#. BL1 prints the following string from the primary CPU to indicate successful 327 execution of the BL1 stage: 328 329 :: 330 331 "Booting Trusted Firmware" 332 333#. BL1 loads a BL2 raw binary image from platform storage, at a 334 platform-specific base address. Prior to the load, BL1 invokes 335 ``bl1_plat_handle_pre_image_load()`` which allows the platform to update or 336 use the image information. If the BL2 image file is not present or if 337 there is not enough free trusted SRAM the following error message is 338 printed: 339 340 :: 341 342 "Failed to load BL2 firmware." 343 344#. BL1 invokes ``bl1_plat_handle_post_image_load()`` which again is intended 345 for platforms to take further action after image load. This function must 346 populate the necessary arguments for BL2, which may also include the memory 347 layout. Further description of the memory layout can be found later 348 in this document. 349 350#. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at 351 Secure SVC mode (for AArch32), starting from its load address. 352 353BL2 354~~~ 355 356BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure 357SVC mode (for AArch32) . BL2 is linked against and loaded at a platform-specific 358base address (more information can be found later in this document). 359The functionality implemented by BL2 is as follows. 360 361Architectural initialization 362^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 363 364For AArch64, BL2 performs the minimal architectural initialization required 365for subsequent stages of TF-A and normal world software. EL1 and EL0 are given 366access to Floating Point and Advanced SIMD registers by clearing the 367``CPACR.FPEN`` bits. 368 369For AArch32, the minimal architectural initialization required for subsequent 370stages of TF-A and normal world software is taken care of in BL1 as both BL1 371and BL2 execute at PL1. 372 373Platform initialization 374^^^^^^^^^^^^^^^^^^^^^^^ 375 376On Arm platforms, BL2 performs the following platform initializations: 377 378- Initialize the console. 379- Configure any required platform storage to allow loading further bootloader 380 images. 381- Enable the MMU and map the memory it needs to access. 382- Perform platform security setup to allow access to controlled components. 383- Reserve some memory for passing information to the next bootloader image 384 EL3 Runtime Software and populate it. 385- Define the extents of memory available for loading each subsequent 386 bootloader image. 387- If BL1 has passed TB_FW_CONFIG dynamic configuration file in ``arg0``, 388 then parse it. 389 390Image loading in BL2 391^^^^^^^^^^^^^^^^^^^^ 392 393BL2 generic code loads the images based on the list of loadable images 394provided by the platform. BL2 passes the list of executable images 395provided by the platform to the next handover BL image. 396 397The list of loadable images provided by the platform may also contain 398dynamic configuration files. The files are loaded and can be parsed as 399needed in the ``bl2_plat_handle_post_image_load()`` function. These 400configuration files can be passed to next Boot Loader stages as arguments 401by updating the corresponding entrypoint information in this function. 402 403SCP_BL2 (System Control Processor Firmware) image load 404^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 405 406Some systems have a separate System Control Processor (SCP) for power, clock, 407reset and system control. BL2 loads the optional SCP_BL2 image from platform 408storage into a platform-specific region of secure memory. The subsequent 409handling of SCP_BL2 is platform specific. For example, on the Juno Arm 410development platform port the image is transferred into SCP's internal memory 411using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM 412memory. The SCP executes SCP_BL2 and signals to the Application Processor (AP) 413for BL2 execution to continue. 414 415EL3 Runtime Software image load 416^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 417 418BL2 loads the EL3 Runtime Software image from platform storage into a platform- 419specific address in trusted SRAM. If there is not enough memory to load the 420image or image is missing it leads to an assertion failure. 421 422AArch64 BL32 (Secure-EL1 Payload) image load 423^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 424 425BL2 loads the optional BL32 image from platform storage into a platform- 426specific region of secure memory. The image executes in the secure world. BL2 427relies on BL31 to pass control to the BL32 image, if present. Hence, BL2 428populates a platform-specific area of memory with the entrypoint/load-address 429of the BL32 image. The value of the Saved Processor Status Register (``SPSR``) 430for entry into BL32 is not determined by BL2, it is initialized by the 431Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for 432managing interaction with BL32. This information is passed to BL31. 433 434BL33 (Non-trusted Firmware) image load 435^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 436 437BL2 loads the BL33 image (e.g. UEFI or other test or boot software) from 438platform storage into non-secure memory as defined by the platform. 439 440BL2 relies on EL3 Runtime Software to pass control to BL33 once secure state 441initialization is complete. Hence, BL2 populates a platform-specific area of 442memory with the entrypoint and Saved Program Status Register (``SPSR``) of the 443normal world software image. The entrypoint is the load address of the BL33 444image. The ``SPSR`` is determined as specified in Section 5.13 of the 445`PSCI PDD`_. This information is passed to the EL3 Runtime Software. 446 447AArch64 BL31 (EL3 Runtime Software) execution 448^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 449 450BL2 execution continues as follows: 451 452#. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the 453 BL31 entrypoint. The exception is handled by the SMC exception handler 454 installed by BL1. 455 456#. BL1 turns off the MMU and flushes the caches. It clears the 457 ``SCTLR_EL3.M/I/C`` bits, flushes the data cache to the point of coherency 458 and invalidates the TLBs. 459 460#. BL1 passes control to BL31 at the specified entrypoint at EL3. 461 462Running BL2 at EL3 execution level 463~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 464 465Some platforms have a non-TF-A Boot ROM that expects the next boot stage 466to execute at EL3. On these platforms, TF-A BL1 is a waste of memory 467as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid 468this waste, a special mode enables BL2 to execute at EL3, which allows 469a non-TF-A Boot ROM to load and jump directly to BL2. This mode is selected 470when the build flag BL2_AT_EL3 is enabled. The main differences in this 471mode are: 472 473#. BL2 includes the reset code and the mailbox mechanism to differentiate 474 cold boot and warm boot. It runs at EL3 doing the arch 475 initialization required for EL3. 476 477#. BL2 does not receive the meminfo information from BL1 anymore. This 478 information can be passed by the Boot ROM or be internal to the 479 BL2 image. 480 481#. Since BL2 executes at EL3, BL2 jumps directly to the next image, 482 instead of invoking the RUN_IMAGE SMC call. 483 484 485We assume 3 different types of BootROM support on the platform: 486 487#. The Boot ROM always jumps to the same address, for both cold 488 and warm boot. In this case, we will need to keep a resident part 489 of BL2 whose memory cannot be reclaimed by any other image. The 490 linker script defines the symbols __TEXT_RESIDENT_START__ and 491 __TEXT_RESIDENT_END__ that allows the platform to configure 492 correctly the memory map. 493#. The platform has some mechanism to indicate the jump address to the 494 Boot ROM. Platform code can then program the jump address with 495 psci_warmboot_entrypoint during cold boot. 496#. The platform has some mechanism to program the reset address using 497 the PROGRAMMABLE_RESET_ADDRESS feature. Platform code can then 498 program the reset address with psci_warmboot_entrypoint during 499 cold boot, bypassing the boot ROM for warm boot. 500 501In the last 2 cases, no part of BL2 needs to remain resident at 502runtime. In the first 2 cases, we expect the Boot ROM to be able to 503differentiate between warm and cold boot, to avoid loading BL2 again 504during warm boot. 505 506This functionality can be tested with FVP loading the image directly 507in memory and changing the address where the system jumps at reset. 508For example: 509 510 -C cluster0.cpu0.RVBAR=0x4022000 511 --data cluster0.cpu0=bl2.bin@0x4022000 512 513With this configuration, FVP is like a platform of the first case, 514where the Boot ROM jumps always to the same address. For simplification, 515BL32 is loaded in DRAM in this case, to avoid other images reclaiming 516BL2 memory. 517 518 519AArch64 BL31 520~~~~~~~~~~~~ 521 522The image for this stage is loaded by BL2 and BL1 passes control to BL31 at 523EL3. BL31 executes solely in trusted SRAM. BL31 is linked against and 524loaded at a platform-specific base address (more information can be found later 525in this document). The functionality implemented by BL31 is as follows. 526 527Architectural initialization 528^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 529 530Currently, BL31 performs a similar architectural initialization to BL1 as 531far as system register settings are concerned. Since BL1 code resides in ROM, 532architectural initialization in BL31 allows override of any previous 533initialization done by BL1. 534 535BL31 initializes the per-CPU data framework, which provides a cache of 536frequently accessed per-CPU data optimised for fast, concurrent manipulation 537on different CPUs. This buffer includes pointers to per-CPU contexts, crash 538buffer, CPU reset and power down operations, PSCI data, platform data and so on. 539 540It then replaces the exception vectors populated by BL1 with its own. BL31 541exception vectors implement more elaborate support for handling SMCs since this 542is the only mechanism to access the runtime services implemented by BL31 (PSCI 543for example). BL31 checks each SMC for validity as specified by the 544`SMC calling convention PDD`_ before passing control to the required SMC 545handler routine. 546 547BL31 programs the ``CNTFRQ_EL0`` register with the clock frequency of the system 548counter, which is provided by the platform. 549 550Platform initialization 551^^^^^^^^^^^^^^^^^^^^^^^ 552 553BL31 performs detailed platform initialization, which enables normal world 554software to function correctly. 555 556On Arm platforms, this consists of the following: 557 558- Initialize the console. 559- Configure the Interconnect to enable hardware coherency. 560- Enable the MMU and map the memory it needs to access. 561- Initialize the generic interrupt controller. 562- Initialize the power controller device. 563- Detect the system topology. 564 565Runtime services initialization 566^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 567 568BL31 is responsible for initializing the runtime services. One of them is PSCI. 569 570As part of the PSCI initializations, BL31 detects the system topology. It also 571initializes the data structures that implement the state machine used to track 572the state of power domain nodes. The state can be one of ``OFF``, ``RUN`` or 573``RETENTION``. All secondary CPUs are initially in the ``OFF`` state. The cluster 574that the primary CPU belongs to is ``ON``; any other cluster is ``OFF``. It also 575initializes the locks that protect them. BL31 accesses the state of a CPU or 576cluster immediately after reset and before the data cache is enabled in the 577warm boot path. It is not currently possible to use 'exclusive' based spinlocks, 578therefore BL31 uses locks based on Lamport's Bakery algorithm instead. 579 580The runtime service framework and its initialization is described in more 581detail in the "EL3 runtime services framework" section below. 582 583Details about the status of the PSCI implementation are provided in the 584"Power State Coordination Interface" section below. 585 586AArch64 BL32 (Secure-EL1 Payload) image initialization 587^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 588 589If a BL32 image is present then there must be a matching Secure-EL1 Payload 590Dispatcher (SPD) service (see later for details). During initialization 591that service must register a function to carry out initialization of BL32 592once the runtime services are fully initialized. BL31 invokes such a 593registered function to initialize BL32 before running BL33. This initialization 594is not necessary for AArch32 SPs. 595 596Details on BL32 initialization and the SPD's role are described in the 597"Secure-EL1 Payloads and Dispatchers" section below. 598 599BL33 (Non-trusted Firmware) execution 600^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 601 602EL3 Runtime Software initializes the EL2 or EL1 processor context for normal- 603world cold boot, ensuring that no secure state information finds its way into 604the non-secure execution state. EL3 Runtime Software uses the entrypoint 605information provided by BL2 to jump to the Non-trusted firmware image (BL33) 606at the highest available Exception Level (EL2 if available, otherwise EL1). 607 608Using alternative Trusted Boot Firmware in place of BL1 & BL2 (AArch64 only) 609~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 610 611Some platforms have existing implementations of Trusted Boot Firmware that 612would like to use TF-A BL31 for the EL3 Runtime Software. To enable this 613firmware architecture it is important to provide a fully documented and stable 614interface between the Trusted Boot Firmware and BL31. 615 616Future changes to the BL31 interface will be done in a backwards compatible 617way, and this enables these firmware components to be independently enhanced/ 618updated to develop and exploit new functionality. 619 620Required CPU state when calling ``bl31_entrypoint()`` during cold boot 621^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 622 623This function must only be called by the primary CPU. 624 625On entry to this function the calling primary CPU must be executing in AArch64 626EL3, little-endian data access, and all interrupt sources masked: 627 628:: 629 630 PSTATE.EL = 3 631 PSTATE.RW = 1 632 PSTATE.DAIF = 0xf 633 SCTLR_EL3.EE = 0 634 635X0 and X1 can be used to pass information from the Trusted Boot Firmware to the 636platform code in BL31: 637 638:: 639 640 X0 : Reserved for common TF-A information 641 X1 : Platform specific information 642 643BL31 zero-init sections (e.g. ``.bss``) should not contain valid data on entry, 644these will be zero filled prior to invoking platform setup code. 645 646Use of the X0 and X1 parameters 647''''''''''''''''''''''''''''''' 648 649The parameters are platform specific and passed from ``bl31_entrypoint()`` to 650``bl31_early_platform_setup()``. The value of these parameters is never directly 651used by the common BL31 code. 652 653The convention is that ``X0`` conveys information regarding the BL31, BL32 and 654BL33 images from the Trusted Boot firmware and ``X1`` can be used for other 655platform specific purpose. This convention allows platforms which use TF-A's 656BL1 and BL2 images to transfer additional platform specific information from 657Secure Boot without conflicting with future evolution of TF-A using ``X0`` to 658pass a ``bl31_params`` structure. 659 660BL31 common and SPD initialization code depends on image and entrypoint 661information about BL33 and BL32, which is provided via BL31 platform APIs. 662This information is required until the start of execution of BL33. This 663information can be provided in a platform defined manner, e.g. compiled into 664the platform code in BL31, or provided in a platform defined memory location 665by the Trusted Boot firmware, or passed from the Trusted Boot Firmware via the 666Cold boot Initialization parameters. This data may need to be cleaned out of 667the CPU caches if it is provided by an earlier boot stage and then accessed by 668BL31 platform code before the caches are enabled. 669 670TF-A's BL2 implementation passes a ``bl31_params`` structure in 671``X0`` and the Arm development platforms interpret this in the BL31 platform 672code. 673 674MMU, Data caches & Coherency 675'''''''''''''''''''''''''''' 676 677BL31 does not depend on the enabled state of the MMU, data caches or 678interconnect coherency on entry to ``bl31_entrypoint()``. If these are disabled 679on entry, these should be enabled during ``bl31_plat_arch_setup()``. 680 681Data structures used in the BL31 cold boot interface 682'''''''''''''''''''''''''''''''''''''''''''''''''''' 683 684These structures are designed to support compatibility and independent 685evolution of the structures and the firmware images. For example, a version of 686BL31 that can interpret the BL3x image information from different versions of 687BL2, a platform that uses an extended entry_point_info structure to convey 688additional register information to BL31, or a ELF image loader that can convey 689more details about the firmware images. 690 691To support these scenarios the structures are versioned and sized, which enables 692BL31 to detect which information is present and respond appropriately. The 693``param_header`` is defined to capture this information: 694 695.. code:: c 696 697 typedef struct param_header { 698 uint8_t type; /* type of the structure */ 699 uint8_t version; /* version of this structure */ 700 uint16_t size; /* size of this structure in bytes */ 701 uint32_t attr; /* attributes: unused bits SBZ */ 702 } param_header_t; 703 704The structures using this format are ``entry_point_info``, ``image_info`` and 705``bl31_params``. The code that allocates and populates these structures must set 706the header fields appropriately, and the ``SET_PARAM_HEAD()`` a macro is defined 707to simplify this action. 708 709Required CPU state for BL31 Warm boot initialization 710^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 711 712When requesting a CPU power-on, or suspending a running CPU, TF-A provides 713the platform power management code with a Warm boot initialization 714entry-point, to be invoked by the CPU immediately after the reset handler. 715On entry to the Warm boot initialization function the calling CPU must be in 716AArch64 EL3, little-endian data access and all interrupt sources masked: 717 718:: 719 720 PSTATE.EL = 3 721 PSTATE.RW = 1 722 PSTATE.DAIF = 0xf 723 SCTLR_EL3.EE = 0 724 725The PSCI implementation will initialize the processor state and ensure that the 726platform power management code is then invoked as required to initialize all 727necessary system, cluster and CPU resources. 728 729AArch32 EL3 Runtime Software entrypoint interface 730~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 731 732To enable this firmware architecture it is important to provide a fully 733documented and stable interface between the Trusted Boot Firmware and the 734AArch32 EL3 Runtime Software. 735 736Future changes to the entrypoint interface will be done in a backwards 737compatible way, and this enables these firmware components to be independently 738enhanced/updated to develop and exploit new functionality. 739 740Required CPU state when entering during cold boot 741^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 742 743This function must only be called by the primary CPU. 744 745On entry to this function the calling primary CPU must be executing in AArch32 746EL3, little-endian data access, and all interrupt sources masked: 747 748:: 749 750 PSTATE.AIF = 0x7 751 SCTLR.EE = 0 752 753R0 and R1 are used to pass information from the Trusted Boot Firmware to the 754platform code in AArch32 EL3 Runtime Software: 755 756:: 757 758 R0 : Reserved for common TF-A information 759 R1 : Platform specific information 760 761Use of the R0 and R1 parameters 762''''''''''''''''''''''''''''''' 763 764The parameters are platform specific and the convention is that ``R0`` conveys 765information regarding the BL3x images from the Trusted Boot firmware and ``R1`` 766can be used for other platform specific purpose. This convention allows 767platforms which use TF-A's BL1 and BL2 images to transfer additional platform 768specific information from Secure Boot without conflicting with future 769evolution of TF-A using ``R0`` to pass a ``bl_params`` structure. 770 771The AArch32 EL3 Runtime Software is responsible for entry into BL33. This 772information can be obtained in a platform defined manner, e.g. compiled into 773the AArch32 EL3 Runtime Software, or provided in a platform defined memory 774location by the Trusted Boot firmware, or passed from the Trusted Boot Firmware 775via the Cold boot Initialization parameters. This data may need to be cleaned 776out of the CPU caches if it is provided by an earlier boot stage and then 777accessed by AArch32 EL3 Runtime Software before the caches are enabled. 778 779When using AArch32 EL3 Runtime Software, the Arm development platforms pass a 780``bl_params`` structure in ``R0`` from BL2 to be interpreted by AArch32 EL3 Runtime 781Software platform code. 782 783MMU, Data caches & Coherency 784'''''''''''''''''''''''''''' 785 786AArch32 EL3 Runtime Software must not depend on the enabled state of the MMU, 787data caches or interconnect coherency in its entrypoint. They must be explicitly 788enabled if required. 789 790Data structures used in cold boot interface 791''''''''''''''''''''''''''''''''''''''''''' 792 793The AArch32 EL3 Runtime Software cold boot interface uses ``bl_params`` instead 794of ``bl31_params``. The ``bl_params`` structure is based on the convention 795described in AArch64 BL31 cold boot interface section. 796 797Required CPU state for warm boot initialization 798^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 799 800When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3 801Runtime Software must ensure execution of a warm boot initialization entrypoint. 802If TF-A BL1 is used and the PROGRAMMABLE_RESET_ADDRESS build flag is false, 803then AArch32 EL3 Runtime Software must ensure that BL1 branches to the warm 804boot entrypoint by arranging for the BL1 platform function, 805plat_get_my_entrypoint(), to return a non-zero value. 806 807In this case, the warm boot entrypoint must be in AArch32 EL3, little-endian 808data access and all interrupt sources masked: 809 810:: 811 812 PSTATE.AIF = 0x7 813 SCTLR.EE = 0 814 815The warm boot entrypoint may be implemented by using TF-A 816``psci_warmboot_entrypoint()`` function. In that case, the platform must fulfil 817the pre-requisites mentioned in the `PSCI Library integration guide`_. 818 819EL3 runtime services framework 820------------------------------ 821 822Software executing in the non-secure state and in the secure state at exception 823levels lower than EL3 will request runtime services using the Secure Monitor 824Call (SMC) instruction. These requests will follow the convention described in 825the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function 826identifiers to each SMC request and describes how arguments are passed and 827returned. 828 829The EL3 runtime services framework enables the development of services by 830different providers that can be easily integrated into final product firmware. 831The following sections describe the framework which facilitates the 832registration, initialization and use of runtime services in EL3 Runtime 833Software (BL31). 834 835The design of the runtime services depends heavily on the concepts and 836definitions described in the `SMCCC`_, in particular SMC Function IDs, Owning 837Entity Numbers (OEN), Fast and Yielding calls, and the SMC32 and SMC64 calling 838conventions. Please refer to that document for more detailed explanation of 839these terms. 840 841The following runtime services are expected to be implemented first. They have 842not all been instantiated in the current implementation. 843 844#. Standard service calls 845 846 This service is for management of the entire system. The Power State 847 Coordination Interface (`PSCI`_) is the first set of standard service calls 848 defined by Arm (see PSCI section later). 849 850#. Secure-EL1 Payload Dispatcher service 851 852 If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then 853 it also requires a *Secure Monitor* at EL3 to switch the EL1 processor 854 context between the normal world (EL1/EL2) and trusted world (Secure-EL1). 855 The Secure Monitor will make these world switches in response to SMCs. The 856 `SMCCC`_ provides for such SMCs with the Trusted OS Call and Trusted 857 Application Call OEN ranges. 858 859 The interface between the EL3 Runtime Software and the Secure-EL1 Payload is 860 not defined by the `SMCCC`_ or any other standard. As a result, each 861 Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime 862 service - within TF-A this service is referred to as the Secure-EL1 Payload 863 Dispatcher (SPD). 864 865 TF-A provides a Test Secure-EL1 Payload (TSP) and its associated Dispatcher 866 (TSPD). Details of SPD design and TSP/TSPD operation are described in the 867 "Secure-EL1 Payloads and Dispatchers" section below. 868 869#. CPU implementation service 870 871 This service will provide an interface to CPU implementation specific 872 services for a given platform e.g. access to processor errata workarounds. 873 This service is currently unimplemented. 874 875Additional services for Arm Architecture, SiP and OEM calls can be implemented. 876Each implemented service handles a range of SMC function identifiers as 877described in the `SMCCC`_. 878 879Registration 880~~~~~~~~~~~~ 881 882A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying 883the name of the service, the range of OENs covered, the type of service and 884initialization and call handler functions. This macro instantiates a ``const struct rt_svc_desc`` for the service with these details (see ``runtime_svc.h``). 885This structure is allocated in a special ELF section ``rt_svc_descs``, enabling 886the framework to find all service descriptors included into BL31. 887 888The specific service for a SMC Function is selected based on the OEN and call 889type of the Function ID, and the framework uses that information in the service 890descriptor to identify the handler for the SMC Call. 891 892The service descriptors do not include information to identify the precise set 893of SMC function identifiers supported by this service implementation, the 894security state from which such calls are valid nor the capability to support 89564-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately 896to these aspects of a SMC call is the responsibility of the service 897implementation, the framework is focused on integration of services from 898different providers and minimizing the time taken by the framework before the 899service handler is invoked. 900 901Details of the parameters, requirements and behavior of the initialization and 902call handling functions are provided in the following sections. 903 904Initialization 905~~~~~~~~~~~~~~ 906 907``runtime_svc_init()`` in ``runtime_svc.c`` initializes the runtime services 908framework running on the primary CPU during cold boot as part of the BL31 909initialization. This happens prior to initializing a Trusted OS and running 910Normal world boot firmware that might in turn use these services. 911Initialization involves validating each of the declared runtime service 912descriptors, calling the service initialization function and populating the 913index used for runtime lookup of the service. 914 915The BL31 linker script collects all of the declared service descriptors into a 916single array and defines symbols that allow the framework to locate and traverse 917the array, and determine its size. 918 919The framework does basic validation of each descriptor to halt firmware 920initialization if service declaration errors are detected. The framework does 921not check descriptors for the following error conditions, and may behave in an 922unpredictable manner under such scenarios: 923 924#. Overlapping OEN ranges 925#. Multiple descriptors for the same range of OENs and ``call_type`` 926#. Incorrect range of owning entity numbers for a given ``call_type`` 927 928Once validated, the service ``init()`` callback is invoked. This function carries 929out any essential EL3 initialization before servicing requests. The ``init()`` 930function is only invoked on the primary CPU during cold boot. If the service 931uses per-CPU data this must either be initialized for all CPUs during this call, 932or be done lazily when a CPU first issues an SMC call to that service. If 933``init()`` returns anything other than ``0``, this is treated as an initialization 934error and the service is ignored: this does not cause the firmware to halt. 935 936The OEN and call type fields present in the SMC Function ID cover a total of 937128 distinct services, but in practice a single descriptor can cover a range of 938OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a 939service handler, the framework uses an array of 128 indices that map every 940distinct OEN/call-type combination either to one of the declared services or to 941indicate the service is not handled. This ``rt_svc_descs_indices[]`` array is 942populated for all of the OENs covered by a service after the service ``init()`` 943function has reported success. So a service that fails to initialize will never 944have it's ``handle()`` function invoked. 945 946The following figure shows how the ``rt_svc_descs_indices[]`` index maps the SMC 947Function ID call type and OEN onto a specific service handler in the 948``rt_svc_descs[]`` array. 949 950|Image 1| 951 952Handling an SMC 953~~~~~~~~~~~~~~~ 954 955When the EL3 runtime services framework receives a Secure Monitor Call, the SMC 956Function ID is passed in W0 from the lower exception level (as per the 957`SMCCC`_). If the calling register width is AArch32, it is invalid to invoke an 958SMC Function which indicates the SMC64 calling convention: such calls are 959ignored and return the Unknown SMC Function Identifier result code ``0xFFFFFFFF`` 960in R0/X0. 961 962Bit[31] (fast/yielding call) and bits[29:24] (owning entity number) of the SMC 963Function ID are combined to index into the ``rt_svc_descs_indices[]`` array. The 964resulting value might indicate a service that has no handler, in this case the 965framework will also report an Unknown SMC Function ID. Otherwise, the value is 966used as a further index into the ``rt_svc_descs[]`` array to locate the required 967service and handler. 968 969The service's ``handle()`` callback is provided with five of the SMC parameters 970directly, the others are saved into memory for retrieval (if needed) by the 971handler. The handler is also provided with an opaque ``handle`` for use with the 972supporting library for parameter retrieval, setting return values and context 973manipulation; and with ``flags`` indicating the security state of the caller. The 974framework finally sets up the execution stack for the handler, and invokes the 975services ``handle()`` function. 976 977On return from the handler the result registers are populated in X0-X3 before 978restoring the stack and CPU state and returning from the original SMC. 979 980Exception Handling Framework 981---------------------------- 982 983Please refer to the `Exception Handling Framework`_ document. 984 985Power State Coordination Interface 986---------------------------------- 987 988TODO: Provide design walkthrough of PSCI implementation. 989 990The PSCI v1.1 specification categorizes APIs as optional and mandatory. All the 991mandatory APIs in PSCI v1.1, PSCI v1.0 and in PSCI v0.2 draft specification 992`Power State Coordination Interface PDD`_ are implemented. The table lists 993the PSCI v1.1 APIs and their support in generic code. 994 995An API implementation might have a dependency on platform code e.g. CPU_SUSPEND 996requires the platform to export a part of the implementation. Hence the level 997of support of the mandatory APIs depends upon the support exported by the 998platform port as well. The Juno and FVP (all variants) platforms export all the 999required support. 1000 1001+-----------------------------+-------------+-------------------------------+ 1002| PSCI v1.1 API | Supported | Comments | 1003+=============================+=============+===============================+ 1004| ``PSCI_VERSION`` | Yes | The version returned is 1.1 | 1005+-----------------------------+-------------+-------------------------------+ 1006| ``CPU_SUSPEND`` | Yes\* | | 1007+-----------------------------+-------------+-------------------------------+ 1008| ``CPU_OFF`` | Yes\* | | 1009+-----------------------------+-------------+-------------------------------+ 1010| ``CPU_ON`` | Yes\* | | 1011+-----------------------------+-------------+-------------------------------+ 1012| ``AFFINITY_INFO`` | Yes | | 1013+-----------------------------+-------------+-------------------------------+ 1014| ``MIGRATE`` | Yes\*\* | | 1015+-----------------------------+-------------+-------------------------------+ 1016| ``MIGRATE_INFO_TYPE`` | Yes\*\* | | 1017+-----------------------------+-------------+-------------------------------+ 1018| ``MIGRATE_INFO_CPU`` | Yes\*\* | | 1019+-----------------------------+-------------+-------------------------------+ 1020| ``SYSTEM_OFF`` | Yes\* | | 1021+-----------------------------+-------------+-------------------------------+ 1022| ``SYSTEM_RESET`` | Yes\* | | 1023+-----------------------------+-------------+-------------------------------+ 1024| ``PSCI_FEATURES`` | Yes | | 1025+-----------------------------+-------------+-------------------------------+ 1026| ``CPU_FREEZE`` | No | | 1027+-----------------------------+-------------+-------------------------------+ 1028| ``CPU_DEFAULT_SUSPEND`` | No | | 1029+-----------------------------+-------------+-------------------------------+ 1030| ``NODE_HW_STATE`` | Yes\* | | 1031+-----------------------------+-------------+-------------------------------+ 1032| ``SYSTEM_SUSPEND`` | Yes\* | | 1033+-----------------------------+-------------+-------------------------------+ 1034| ``PSCI_SET_SUSPEND_MODE`` | No | | 1035+-----------------------------+-------------+-------------------------------+ 1036| ``PSCI_STAT_RESIDENCY`` | Yes\* | | 1037+-----------------------------+-------------+-------------------------------+ 1038| ``PSCI_STAT_COUNT`` | Yes\* | | 1039+-----------------------------+-------------+-------------------------------+ 1040| ``SYSTEM_RESET2`` | Yes\* | | 1041+-----------------------------+-------------+-------------------------------+ 1042| ``MEM_PROTECT`` | Yes\* | | 1043+-----------------------------+-------------+-------------------------------+ 1044| ``MEM_PROTECT_CHECK_RANGE`` | Yes\* | | 1045+-----------------------------+-------------+-------------------------------+ 1046 1047\*Note : These PSCI APIs require platform power management hooks to be 1048registered with the generic PSCI code to be supported. 1049 1050\*\*Note : These PSCI APIs require appropriate Secure Payload Dispatcher 1051hooks to be registered with the generic PSCI code to be supported. 1052 1053The PSCI implementation in TF-A is a library which can be integrated with 1054AArch64 or AArch32 EL3 Runtime Software for Armv8-A systems. A guide to 1055integrating PSCI library with AArch32 EL3 Runtime Software can be found 1056`here`_. 1057 1058Secure-EL1 Payloads and Dispatchers 1059----------------------------------- 1060 1061On a production system that includes a Trusted OS running in Secure-EL1/EL0, 1062the Trusted OS is coupled with a companion runtime service in the BL31 1063firmware. This service is responsible for the initialisation of the Trusted 1064OS and all communications with it. The Trusted OS is the BL32 stage of the 1065boot flow in TF-A. The firmware will attempt to locate, load and execute a 1066BL32 image. 1067 1068TF-A uses a more general term for the BL32 software that runs at Secure-EL1 - 1069the *Secure-EL1 Payload* - as it is not always a Trusted OS. 1070 1071TF-A provides a Test Secure-EL1 Payload (TSP) and a Test Secure-EL1 Payload 1072Dispatcher (TSPD) service as an example of how a Trusted OS is supported on a 1073production system using the Runtime Services Framework. On such a system, the 1074Test BL32 image and service are replaced by the Trusted OS and its dispatcher 1075service. The TF-A build system expects that the dispatcher will define the 1076build flag ``NEED_BL32`` to enable it to include the BL32 in the build either 1077as a binary or to compile from source depending on whether the ``BL32`` build 1078option is specified or not. 1079 1080The TSP runs in Secure-EL1. It is designed to demonstrate synchronous 1081communication with the normal-world software running in EL1/EL2. Communication 1082is initiated by the normal-world software 1083 1084- either directly through a Fast SMC (as defined in the `SMCCC`_) 1085 1086- or indirectly through a `PSCI`_ SMC. The `PSCI`_ implementation in turn 1087 informs the TSPD about the requested power management operation. This allows 1088 the TSP to prepare for or respond to the power state change 1089 1090The TSPD service is responsible for. 1091 1092- Initializing the TSP 1093 1094- Routing requests and responses between the secure and the non-secure 1095 states during the two types of communications just described 1096 1097Initializing a BL32 Image 1098~~~~~~~~~~~~~~~~~~~~~~~~~ 1099 1100The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing 1101the BL32 image. It needs access to the information passed by BL2 to BL31 to do 1102so. This is provided by: 1103 1104.. code:: c 1105 1106 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t); 1107 1108which returns a reference to the ``entry_point_info`` structure corresponding to 1109the image which will be run in the specified security state. The SPD uses this 1110API to get entry point information for the SECURE image, BL32. 1111 1112In the absence of a BL32 image, BL31 passes control to the normal world 1113bootloader image (BL33). When the BL32 image is present, it is typical 1114that the SPD wants control to be passed to BL32 first and then later to BL33. 1115 1116To do this the SPD has to register a BL32 initialization function during 1117initialization of the SPD service. The BL32 initialization function has this 1118prototype: 1119 1120.. code:: c 1121 1122 int32_t init(void); 1123 1124and is registered using the ``bl31_register_bl32_init()`` function. 1125 1126TF-A supports two approaches for the SPD to pass control to BL32 before 1127returning through EL3 and running the non-trusted firmware (BL33): 1128 1129#. In the BL32 setup function, use ``bl31_set_next_image_type()`` to 1130 request that the exit from ``bl31_main()`` is to the BL32 entrypoint in 1131 Secure-EL1. BL31 will exit to BL32 using the asynchronous method by 1132 calling ``bl31_prepare_next_image_entry()`` and ``el3_exit()``. 1133 1134 When the BL32 has completed initialization at Secure-EL1, it returns to 1135 BL31 by issuing an SMC, using a Function ID allocated to the SPD. On 1136 receipt of this SMC, the SPD service handler should switch the CPU context 1137 from trusted to normal world and use the ``bl31_set_next_image_type()`` and 1138 ``bl31_prepare_next_image_entry()`` functions to set up the initial return to 1139 the normal world firmware BL33. On return from the handler the framework 1140 will exit to EL2 and run BL33. 1141 1142#. The BL32 setup function registers an initialization function using 1143 ``bl31_register_bl32_init()`` which provides a SPD-defined mechanism to 1144 invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32 1145 entrypoint. 1146 NOTE: The Test SPD service included with TF-A provides one implementation 1147 of such a mechanism. 1148 1149 On completion BL32 returns control to BL31 via a SMC, and on receipt the 1150 SPD service handler invokes the synchronous call return mechanism to return 1151 to the BL32 initialization function. On return from this function, 1152 ``bl31_main()`` will set up the return to the normal world firmware BL33 and 1153 continue the boot process in the normal world. 1154 1155Crash Reporting in BL31 1156----------------------- 1157 1158BL31 implements a scheme for reporting the processor state when an unhandled 1159exception is encountered. The reporting mechanism attempts to preserve all the 1160register contents and report it via a dedicated UART (PL011 console). BL31 1161reports the general purpose, EL3, Secure EL1 and some EL2 state registers. 1162 1163A dedicated per-CPU crash stack is maintained by BL31 and this is retrieved via 1164the per-CPU pointer cache. The implementation attempts to minimise the memory 1165required for this feature. The file ``crash_reporting.S`` contains the 1166implementation for crash reporting. 1167 1168The sample crash output is shown below. 1169 1170:: 1171 1172 x0 :0x000000004F00007C 1173 x1 :0x0000000007FFFFFF 1174 x2 :0x0000000004014D50 1175 x3 :0x0000000000000000 1176 x4 :0x0000000088007998 1177 x5 :0x00000000001343AC 1178 x6 :0x0000000000000016 1179 x7 :0x00000000000B8A38 1180 x8 :0x00000000001343AC 1181 x9 :0x00000000000101A8 1182 x10 :0x0000000000000002 1183 x11 :0x000000000000011C 1184 x12 :0x00000000FEFDC644 1185 x13 :0x00000000FED93FFC 1186 x14 :0x0000000000247950 1187 x15 :0x00000000000007A2 1188 x16 :0x00000000000007A4 1189 x17 :0x0000000000247950 1190 x18 :0x0000000000000000 1191 x19 :0x00000000FFFFFFFF 1192 x20 :0x0000000004014D50 1193 x21 :0x000000000400A38C 1194 x22 :0x0000000000247950 1195 x23 :0x0000000000000010 1196 x24 :0x0000000000000024 1197 x25 :0x00000000FEFDC868 1198 x26 :0x00000000FEFDC86A 1199 x27 :0x00000000019EDEDC 1200 x28 :0x000000000A7CFDAA 1201 x29 :0x0000000004010780 1202 x30 :0x000000000400F004 1203 scr_el3 :0x0000000000000D3D 1204 sctlr_el3 :0x0000000000C8181F 1205 cptr_el3 :0x0000000000000000 1206 tcr_el3 :0x0000000080803520 1207 daif :0x00000000000003C0 1208 mair_el3 :0x00000000000004FF 1209 spsr_el3 :0x00000000800003CC 1210 elr_el3 :0x000000000400C0CC 1211 ttbr0_el3 :0x00000000040172A0 1212 esr_el3 :0x0000000096000210 1213 sp_el3 :0x0000000004014D50 1214 far_el3 :0x000000004F00007C 1215 spsr_el1 :0x0000000000000000 1216 elr_el1 :0x0000000000000000 1217 spsr_abt :0x0000000000000000 1218 spsr_und :0x0000000000000000 1219 spsr_irq :0x0000000000000000 1220 spsr_fiq :0x0000000000000000 1221 sctlr_el1 :0x0000000030C81807 1222 actlr_el1 :0x0000000000000000 1223 cpacr_el1 :0x0000000000300000 1224 csselr_el1 :0x0000000000000002 1225 sp_el1 :0x0000000004028800 1226 esr_el1 :0x0000000000000000 1227 ttbr0_el1 :0x000000000402C200 1228 ttbr1_el1 :0x0000000000000000 1229 mair_el1 :0x00000000000004FF 1230 amair_el1 :0x0000000000000000 1231 tcr_el1 :0x0000000000003520 1232 tpidr_el1 :0x0000000000000000 1233 tpidr_el0 :0x0000000000000000 1234 tpidrro_el0 :0x0000000000000000 1235 dacr32_el2 :0x0000000000000000 1236 ifsr32_el2 :0x0000000000000000 1237 par_el1 :0x0000000000000000 1238 far_el1 :0x0000000000000000 1239 afsr0_el1 :0x0000000000000000 1240 afsr1_el1 :0x0000000000000000 1241 contextidr_el1 :0x0000000000000000 1242 vbar_el1 :0x0000000004027000 1243 cntp_ctl_el0 :0x0000000000000000 1244 cntp_cval_el0 :0x0000000000000000 1245 cntv_ctl_el0 :0x0000000000000000 1246 cntv_cval_el0 :0x0000000000000000 1247 cntkctl_el1 :0x0000000000000000 1248 sp_el0 :0x0000000004010780 1249 1250Guidelines for Reset Handlers 1251----------------------------- 1252 1253TF-A implements a framework that allows CPU and platform ports to perform 1254actions very early after a CPU is released from reset in both the cold and warm 1255boot paths. This is done by calling the ``reset_handler()`` function in both 1256the BL1 and BL31 images. It in turn calls the platform and CPU specific reset 1257handling functions. 1258 1259Details for implementing a CPU specific reset handler can be found in 1260Section 8. Details for implementing a platform specific reset handler can be 1261found in the `Porting Guide`_ (see the ``plat_reset_handler()`` function). 1262 1263When adding functionality to a reset handler, keep in mind that if a different 1264reset handling behavior is required between the first and the subsequent 1265invocations of the reset handling code, this should be detected at runtime. 1266In other words, the reset handler should be able to detect whether an action has 1267already been performed and act as appropriate. Possible courses of actions are, 1268e.g. skip the action the second time, or undo/redo it. 1269 1270Configuring secure interrupts 1271----------------------------- 1272 1273The GIC driver is responsible for performing initial configuration of secure 1274interrupts on the platform. To this end, the platform is expected to provide the 1275GIC driver (either GICv2 or GICv3, as selected by the platform) with the 1276interrupt configuration during the driver initialisation. 1277 1278Secure interrupt configuration are specified in an array of secure interrupt 1279properties. In this scheme, in both GICv2 and GICv3 driver data structures, the 1280``interrupt_props`` member points to an array of interrupt properties. Each 1281element of the array specifies the interrupt number and its attributes 1282(priority, group, configuration). Each element of the array shall be populated 1283by the macro ``INTR_PROP_DESC()``. The macro takes the following arguments: 1284 1285- 10-bit interrupt number, 1286 1287- 8-bit interrupt priority, 1288 1289- Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``, 1290 ``INTR_TYPE_NS``), 1291 1292- Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or 1293 ``GIC_INTR_CFG_EDGE``). 1294 1295CPU specific operations framework 1296--------------------------------- 1297 1298Certain aspects of the Armv8-A architecture are implementation defined, 1299that is, certain behaviours are not architecturally defined, but must be 1300defined and documented by individual processor implementations. TF-A 1301implements a framework which categorises the common implementation defined 1302behaviours and allows a processor to export its implementation of that 1303behaviour. The categories are: 1304 1305#. Processor specific reset sequence. 1306 1307#. Processor specific power down sequences. 1308 1309#. Processor specific register dumping as a part of crash reporting. 1310 1311#. Errata status reporting. 1312 1313Each of the above categories fulfils a different requirement. 1314 1315#. allows any processor specific initialization before the caches and MMU 1316 are turned on, like implementation of errata workarounds, entry into 1317 the intra-cluster coherency domain etc. 1318 1319#. allows each processor to implement the power down sequence mandated in 1320 its Technical Reference Manual (TRM). 1321 1322#. allows a processor to provide additional information to the developer 1323 in the event of a crash, for example Cortex-A53 has registers which 1324 can expose the data cache contents. 1325 1326#. allows a processor to define a function that inspects and reports the status 1327 of all errata workarounds on that processor. 1328 1329Please note that only 2. is mandated by the TRM. 1330 1331The CPU specific operations framework scales to accommodate a large number of 1332different CPUs during power down and reset handling. The platform can specify 1333any CPU optimization it wants to enable for each CPU. It can also specify 1334the CPU errata workarounds to be applied for each CPU type during reset 1335handling by defining CPU errata compile time macros. Details on these macros 1336can be found in the `cpu-specific-build-macros.rst`_ file. 1337 1338The CPU specific operations framework depends on the ``cpu_ops`` structure which 1339needs to be exported for each type of CPU in the platform. It is defined in 1340``include/lib/cpus/aarch64/cpu_macros.S`` and has the following fields : ``midr``, 1341``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and 1342``cpu_reg_dump()``. 1343 1344The CPU specific files in ``lib/cpus`` export a ``cpu_ops`` data structure with 1345suitable handlers for that CPU. For example, ``lib/cpus/aarch64/cortex_a53.S`` 1346exports the ``cpu_ops`` for Cortex-A53 CPU. According to the platform 1347configuration, these CPU specific files must be included in the build by 1348the platform makefile. The generic CPU specific operations framework code exists 1349in ``lib/cpus/aarch64/cpu_helpers.S``. 1350 1351CPU specific Reset Handling 1352~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1353 1354After a reset, the state of the CPU when it calls generic reset handler is: 1355MMU turned off, both instruction and data caches turned off and not part 1356of any coherency domain. 1357 1358The BL entrypoint code first invokes the ``plat_reset_handler()`` to allow 1359the platform to perform any system initialization required and any system 1360errata workarounds that needs to be applied. The ``get_cpu_ops_ptr()`` reads 1361the current CPU midr, finds the matching ``cpu_ops`` entry in the ``cpu_ops`` 1362array and returns it. Note that only the part number and implementer fields 1363in midr are used to find the matching ``cpu_ops`` entry. The ``reset_func()`` in 1364the returned ``cpu_ops`` is then invoked which executes the required reset 1365handling for that CPU and also any errata workarounds enabled by the platform. 1366This function must preserve the values of general purpose registers x20 to x29. 1367 1368Refer to Section "Guidelines for Reset Handlers" for general guidelines 1369regarding placement of code in a reset handler. 1370 1371CPU specific power down sequence 1372~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1373 1374During the BL31 initialization sequence, the pointer to the matching ``cpu_ops`` 1375entry is stored in per-CPU data by ``init_cpu_ops()`` so that it can be quickly 1376retrieved during power down sequences. 1377 1378Various CPU drivers register handlers to perform power down at certain power 1379levels for that specific CPU. The PSCI service, upon receiving a power down 1380request, determines the highest power level at which to execute power down 1381sequence for a particular CPU. It uses the ``prepare_cpu_pwr_dwn()`` function to 1382pick the right power down handler for the requested level. The function 1383retrieves ``cpu_ops`` pointer member of per-CPU data, and from that, further 1384retrieves ``cpu_pwr_down_ops`` array, and indexes into the required level. If the 1385requested power level is higher than what a CPU driver supports, the handler 1386registered for highest level is invoked. 1387 1388At runtime the platform hooks for power down are invoked by the PSCI service to 1389perform platform specific operations during a power down sequence, for example 1390turning off CCI coherency during a cluster power down. 1391 1392CPU specific register reporting during crash 1393~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1394 1395If the crash reporting is enabled in BL31, when a crash occurs, the crash 1396reporting framework calls ``do_cpu_reg_dump`` which retrieves the matching 1397``cpu_ops`` using ``get_cpu_ops_ptr()`` function. The ``cpu_reg_dump()`` in 1398``cpu_ops`` is invoked, which then returns the CPU specific register values to 1399be reported and a pointer to the ASCII list of register names in a format 1400expected by the crash reporting framework. 1401 1402CPU errata status reporting 1403~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1404 1405Errata workarounds for CPUs supported in TF-A are applied during both cold and 1406warm boots, shortly after reset. Individual Errata workarounds are enabled as 1407build options. Some errata workarounds have potential run-time implications; 1408therefore some are enabled by default, others not. Platform ports shall 1409override build options to enable or disable errata as appropriate. The CPU 1410drivers take care of applying errata workarounds that are enabled and applicable 1411to a given CPU. Refer to the section titled *CPU Errata Workarounds* in `CPUBM`_ 1412for more information. 1413 1414Functions in CPU drivers that apply errata workaround must follow the 1415conventions listed below. 1416 1417The errata workaround must be authored as two separate functions: 1418 1419- One that checks for errata. This function must determine whether that errata 1420 applies to the current CPU. Typically this involves matching the current 1421 CPUs revision and variant against a value that's known to be affected by the 1422 errata. If the function determines that the errata applies to this CPU, it 1423 must return ``ERRATA_APPLIES``; otherwise, it must return 1424 ``ERRATA_NOT_APPLIES``. The utility functions ``cpu_get_rev_var`` and 1425 ``cpu_rev_var_ls`` functions may come in handy for this purpose. 1426 1427For an errata identified as ``E``, the check function must be named 1428``check_errata_E``. 1429 1430This function will be invoked at different times, both from assembly and from 1431C run time. Therefore it must follow AAPCS, and must not use stack. 1432 1433- Another one that applies the errata workaround. This function would call the 1434 check function described above, and applies errata workaround if required. 1435 1436CPU drivers that apply errata workaround can optionally implement an assembly 1437function that report the status of errata workarounds pertaining to that CPU. 1438For a driver that registers the CPU, for example, ``cpux`` via ``declare_cpu_ops`` 1439macro, the errata reporting function, if it exists, must be named 1440``cpux_errata_report``. This function will always be called with MMU enabled; it 1441must follow AAPCS and may use stack. 1442 1443In a debug build of TF-A, on a CPU that comes out of reset, both BL1 and the 1444runtime firmware (BL31 in AArch64, and BL32 in AArch32) will invoke errata 1445status reporting function, if one exists, for that type of CPU. 1446 1447To report the status of each errata workaround, the function shall use the 1448assembler macro ``report_errata``, passing it: 1449 1450- The build option that enables the errata; 1451 1452- The name of the CPU: this must be the same identifier that CPU driver 1453 registered itself with, using ``declare_cpu_ops``; 1454 1455- And the errata identifier: the identifier must match what's used in the 1456 errata's check function described above. 1457 1458The errata status reporting function will be called once per CPU type/errata 1459combination during the software's active life time. 1460 1461It's expected that whenever an errata workaround is submitted to TF-A, the 1462errata reporting function is appropriately extended to report its status as 1463well. 1464 1465Reporting the status of errata workaround is for informational purpose only; it 1466has no functional significance. 1467 1468Memory layout of BL images 1469-------------------------- 1470 1471Each bootloader image can be divided in 2 parts: 1472 1473- the static contents of the image. These are data actually stored in the 1474 binary on the disk. In the ELF terminology, they are called ``PROGBITS`` 1475 sections; 1476 1477- the run-time contents of the image. These are data that don't occupy any 1478 space in the binary on the disk. The ELF binary just contains some 1479 metadata indicating where these data will be stored at run-time and the 1480 corresponding sections need to be allocated and initialized at run-time. 1481 In the ELF terminology, they are called ``NOBITS`` sections. 1482 1483All PROGBITS sections are grouped together at the beginning of the image, 1484followed by all NOBITS sections. This is true for all TF-A images and it is 1485governed by the linker scripts. This ensures that the raw binary images are 1486as small as possible. If a NOBITS section was inserted in between PROGBITS 1487sections then the resulting binary file would contain zero bytes in place of 1488this NOBITS section, making the image unnecessarily bigger. Smaller images 1489allow faster loading from the FIP to the main memory. 1490 1491Linker scripts and symbols 1492~~~~~~~~~~~~~~~~~~~~~~~~~~ 1493 1494Each bootloader stage image layout is described by its own linker script. The 1495linker scripts export some symbols into the program symbol table. Their values 1496correspond to particular addresses. TF-A code can refer to these symbols to 1497figure out the image memory layout. 1498 1499Linker symbols follow the following naming convention in TF-A. 1500 1501- ``__<SECTION>_START__`` 1502 1503 Start address of a given section named ``<SECTION>``. 1504 1505- ``__<SECTION>_END__`` 1506 1507 End address of a given section named ``<SECTION>``. If there is an alignment 1508 constraint on the section's end address then ``__<SECTION>_END__`` corresponds 1509 to the end address of the section's actual contents, rounded up to the right 1510 boundary. Refer to the value of ``__<SECTION>_UNALIGNED_END__`` to know the 1511 actual end address of the section's contents. 1512 1513- ``__<SECTION>_UNALIGNED_END__`` 1514 1515 End address of a given section named ``<SECTION>`` without any padding or 1516 rounding up due to some alignment constraint. 1517 1518- ``__<SECTION>_SIZE__`` 1519 1520 Size (in bytes) of a given section named ``<SECTION>``. If there is an 1521 alignment constraint on the section's end address then ``__<SECTION>_SIZE__`` 1522 corresponds to the size of the section's actual contents, rounded up to the 1523 right boundary. In other words, ``__<SECTION>_SIZE__ = __<SECTION>_END__ - _<SECTION>_START__``. Refer to the value of ``__<SECTION>_UNALIGNED_SIZE__`` 1524 to know the actual size of the section's contents. 1525 1526- ``__<SECTION>_UNALIGNED_SIZE__`` 1527 1528 Size (in bytes) of a given section named ``<SECTION>`` without any padding or 1529 rounding up due to some alignment constraint. In other words, 1530 ``__<SECTION>_UNALIGNED_SIZE__ = __<SECTION>_UNALIGNED_END__ - __<SECTION>_START__``. 1531 1532Some of the linker symbols are mandatory as TF-A code relies on them to be 1533defined. They are listed in the following subsections. Some of them must be 1534provided for each bootloader stage and some are specific to a given bootloader 1535stage. 1536 1537The linker scripts define some extra, optional symbols. They are not actually 1538used by any code but they help in understanding the bootloader images' memory 1539layout as they are easy to spot in the link map files. 1540 1541Common linker symbols 1542^^^^^^^^^^^^^^^^^^^^^ 1543 1544All BL images share the following requirements: 1545 1546- The BSS section must be zero-initialised before executing any C code. 1547- The coherent memory section (if enabled) must be zero-initialised as well. 1548- The MMU setup code needs to know the extents of the coherent and read-only 1549 memory regions to set the right memory attributes. When 1550 ``SEPARATE_CODE_AND_RODATA=1``, it needs to know more specifically how the 1551 read-only memory region is divided between code and data. 1552 1553The following linker symbols are defined for this purpose: 1554 1555- ``__BSS_START__`` 1556- ``__BSS_SIZE__`` 1557- ``__COHERENT_RAM_START__`` Must be aligned on a page-size boundary. 1558- ``__COHERENT_RAM_END__`` Must be aligned on a page-size boundary. 1559- ``__COHERENT_RAM_UNALIGNED_SIZE__`` 1560- ``__RO_START__`` 1561- ``__RO_END__`` 1562- ``__TEXT_START__`` 1563- ``__TEXT_END__`` 1564- ``__RODATA_START__`` 1565- ``__RODATA_END__`` 1566 1567BL1's linker symbols 1568^^^^^^^^^^^^^^^^^^^^ 1569 1570BL1 being the ROM image, it has additional requirements. BL1 resides in ROM and 1571it is entirely executed in place but it needs some read-write memory for its 1572mutable data. Its ``.data`` section (i.e. its allocated read-write data) must be 1573relocated from ROM to RAM before executing any C code. 1574 1575The following additional linker symbols are defined for BL1: 1576 1577- ``__BL1_ROM_END__`` End address of BL1's ROM contents, covering its code 1578 and ``.data`` section in ROM. 1579- ``__DATA_ROM_START__`` Start address of the ``.data`` section in ROM. Must be 1580 aligned on a 16-byte boundary. 1581- ``__DATA_RAM_START__`` Address in RAM where the ``.data`` section should be 1582 copied over. Must be aligned on a 16-byte boundary. 1583- ``__DATA_SIZE__`` Size of the ``.data`` section (in ROM or RAM). 1584- ``__BL1_RAM_START__`` Start address of BL1 read-write data. 1585- ``__BL1_RAM_END__`` End address of BL1 read-write data. 1586 1587How to choose the right base addresses for each bootloader stage image 1588~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1589 1590There is currently no support for dynamic image loading in TF-A. This means 1591that all bootloader images need to be linked against their ultimate runtime 1592locations and the base addresses of each image must be chosen carefully such 1593that images don't overlap each other in an undesired way. As the code grows, 1594the base addresses might need adjustments to cope with the new memory layout. 1595 1596The memory layout is completely specific to the platform and so there is no 1597general recipe for choosing the right base addresses for each bootloader image. 1598However, there are tools to aid in understanding the memory layout. These are 1599the link map files: ``build/<platform>/<build-type>/bl<x>/bl<x>.map``, with ``<x>`` 1600being the stage bootloader. They provide a detailed view of the memory usage of 1601each image. Among other useful information, they provide the end address of 1602each image. 1603 1604- ``bl1.map`` link map file provides ``__BL1_RAM_END__`` address. 1605- ``bl2.map`` link map file provides ``__BL2_END__`` address. 1606- ``bl31.map`` link map file provides ``__BL31_END__`` address. 1607- ``bl32.map`` link map file provides ``__BL32_END__`` address. 1608 1609For each bootloader image, the platform code must provide its start address 1610as well as a limit address that it must not overstep. The latter is used in the 1611linker scripts to check that the image doesn't grow past that address. If that 1612happens, the linker will issue a message similar to the following: 1613 1614:: 1615 1616 aarch64-none-elf-ld: BLx has exceeded its limit. 1617 1618Additionally, if the platform memory layout implies some image overlaying like 1619on FVP, BL31 and TSP need to know the limit address that their PROGBITS 1620sections must not overstep. The platform code must provide those. 1621 1622TF-A does not provide any mechanism to verify at boot time that the memory 1623to load a new image is free to prevent overwriting a previously loaded image. 1624The platform must specify the memory available in the system for all the 1625relevant BL images to be loaded. 1626 1627For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will 1628return the region defined by the platform where BL1 intends to load BL2. The 1629``load_image()`` function performs bounds check for the image size based on the 1630base and maximum image size provided by the platforms. Platforms must take 1631this behaviour into account when defining the base/size for each of the images. 1632 1633Memory layout on Arm development platforms 1634^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1635 1636The following list describes the memory layout on the Arm development platforms: 1637 1638- A 4KB page of shared memory is used for communication between Trusted 1639 Firmware and the platform's power controller. This is located at the base of 1640 Trusted SRAM. The amount of Trusted SRAM available to load the bootloader 1641 images is reduced by the size of the shared memory. 1642 1643 The shared memory is used to store the CPUs' entrypoint mailbox. On Juno, 1644 this is also used for the MHU payload when passing messages to and from the 1645 SCP. 1646 1647- Another 4 KB page is reserved for passing memory layout between BL1 and BL2 1648 and also the dynamic firmware configurations. 1649 1650- On FVP, BL1 is originally sitting in the Trusted ROM at address ``0x0``. On 1651 Juno, BL1 resides in flash memory at address ``0x0BEC0000``. BL1 read-write 1652 data are relocated to the top of Trusted SRAM at runtime. 1653 1654- BL2 is loaded below BL1 RW 1655 1656- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP_MIN), 1657 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will 1658 overwrite BL1 R/W data and BL2. This implies that BL1 global variables 1659 remain valid only until execution reaches the EL3 Runtime Software entry 1660 point during a cold boot. 1661 1662- On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory 1663 region and transfered to the SCP before being overwritten by EL3 Runtime 1664 Software. 1665 1666- BL32 (for AArch64) can be loaded in one of the following locations: 1667 1668 - Trusted SRAM 1669 - Trusted DRAM (FVP only) 1670 - Secure region of DRAM (top 16MB of DRAM configured by the TrustZone 1671 controller) 1672 1673 When BL32 (for AArch64) is loaded into Trusted SRAM, it is loaded below 1674 BL31. 1675 1676The location of the BL32 image will result in different memory maps. This is 1677illustrated for both FVP and Juno in the following diagrams, using the TSP as 1678an example. 1679 1680Note: Loading the BL32 image in TZC secured DRAM doesn't change the memory 1681layout of the other images in Trusted SRAM. 1682 1683CONFIG section in memory layouts shown below contains: 1684 1685:: 1686 1687 +--------------------+ 1688 |bl2_mem_params_descs| 1689 |--------------------| 1690 | fw_configs | 1691 +--------------------+ 1692 1693``bl2_mem_params_descs`` contains parameters passed from BL2 to next the 1694BL image during boot. 1695 1696``fw_configs`` includes soc_fw_config, tos_fw_config and tb_fw_config. 1697 1698**FVP with TSP in Trusted SRAM with firmware configs :** 1699(These diagrams only cover the AArch64 case) 1700 1701:: 1702 1703 DRAM 1704 0xffffffff +----------+ 1705 : : 1706 |----------| 1707 |HW_CONFIG | 1708 0x83000000 |----------| (non-secure) 1709 | | 1710 0x80000000 +----------+ 1711 1712 Trusted SRAM 1713 0x04040000 +----------+ loaded by BL2 +----------------+ 1714 | BL1 (rw) | <<<<<<<<<<<<< | | 1715 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1716 | BL2 | <<<<<<<<<<<<< | | 1717 |----------| <<<<<<<<<<<<< |----------------| 1718 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1719 | | <<<<<<<<<<<<< |----------------| 1720 | | <<<<<<<<<<<<< | BL32 | 1721 0x04002000 +----------+ +----------------+ 1722 | CONFIG | 1723 0x04001000 +----------+ 1724 | Shared | 1725 0x04000000 +----------+ 1726 1727 Trusted ROM 1728 0x04000000 +----------+ 1729 | BL1 (ro) | 1730 0x00000000 +----------+ 1731 1732**FVP with TSP in Trusted DRAM with firmware configs (default option):** 1733 1734:: 1735 1736 DRAM 1737 0xffffffff +--------------+ 1738 : : 1739 |--------------| 1740 | HW_CONFIG | 1741 0x83000000 |--------------| (non-secure) 1742 | | 1743 0x80000000 +--------------+ 1744 1745 Trusted DRAM 1746 0x08000000 +--------------+ 1747 | BL32 | 1748 0x06000000 +--------------+ 1749 1750 Trusted SRAM 1751 0x04040000 +--------------+ loaded by BL2 +----------------+ 1752 | BL1 (rw) | <<<<<<<<<<<<< | | 1753 |--------------| <<<<<<<<<<<<< | BL31 NOBITS | 1754 | BL2 | <<<<<<<<<<<<< | | 1755 |--------------| <<<<<<<<<<<<< |----------------| 1756 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1757 | | +----------------+ 1758 +--------------+ 1759 | CONFIG | 1760 0x04001000 +--------------+ 1761 | Shared | 1762 0x04000000 +--------------+ 1763 1764 Trusted ROM 1765 0x04000000 +--------------+ 1766 | BL1 (ro) | 1767 0x00000000 +--------------+ 1768 1769**FVP with TSP in TZC-Secured DRAM with firmware configs :** 1770 1771:: 1772 1773 DRAM 1774 0xffffffff +----------+ 1775 | BL32 | (secure) 1776 0xff000000 +----------+ 1777 | | 1778 |----------| 1779 |HW_CONFIG | 1780 0x83000000 |----------| (non-secure) 1781 | | 1782 0x80000000 +----------+ 1783 1784 Trusted SRAM 1785 0x04040000 +----------+ loaded by BL2 +----------------+ 1786 | BL1 (rw) | <<<<<<<<<<<<< | | 1787 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1788 | BL2 | <<<<<<<<<<<<< | | 1789 |----------| <<<<<<<<<<<<< |----------------| 1790 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1791 | | +----------------+ 1792 0x04002000 +----------+ 1793 | CONFIG | 1794 0x04001000 +----------+ 1795 | Shared | 1796 0x04000000 +----------+ 1797 1798 Trusted ROM 1799 0x04000000 +----------+ 1800 | BL1 (ro) | 1801 0x00000000 +----------+ 1802 1803**Juno with BL32 in Trusted SRAM :** 1804 1805:: 1806 1807 Flash0 1808 0x0C000000 +----------+ 1809 : : 1810 0x0BED0000 |----------| 1811 | BL1 (ro) | 1812 0x0BEC0000 |----------| 1813 : : 1814 0x08000000 +----------+ BL31 is loaded 1815 after SCP_BL2 has 1816 Trusted SRAM been sent to SCP 1817 0x04040000 +----------+ loaded by BL2 +----------------+ 1818 | BL1 (rw) | <<<<<<<<<<<<< | | 1819 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1820 | BL2 | <<<<<<<<<<<<< | | 1821 |----------| <<<<<<<<<<<<< |----------------| 1822 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 1823 |----------| <<<<<<<<<<<<< |----------------| 1824 | | <<<<<<<<<<<<< | BL32 | 1825 | | +----------------+ 1826 | | 1827 0x04001000 +----------+ 1828 | MHU | 1829 0x04000000 +----------+ 1830 1831**Juno with BL32 in TZC-secured DRAM :** 1832 1833:: 1834 1835 DRAM 1836 0xFFE00000 +----------+ 1837 | BL32 | (secure) 1838 0xFF000000 |----------| 1839 | | 1840 : : (non-secure) 1841 | | 1842 0x80000000 +----------+ 1843 1844 Flash0 1845 0x0C000000 +----------+ 1846 : : 1847 0x0BED0000 |----------| 1848 | BL1 (ro) | 1849 0x0BEC0000 |----------| 1850 : : 1851 0x08000000 +----------+ BL31 is loaded 1852 after SCP_BL2 has 1853 Trusted SRAM been sent to SCP 1854 0x04040000 +----------+ loaded by BL2 +----------------+ 1855 | BL1 (rw) | <<<<<<<<<<<<< | | 1856 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1857 | BL2 | <<<<<<<<<<<<< | | 1858 |----------| <<<<<<<<<<<<< |----------------| 1859 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 1860 |----------| +----------------+ 1861 0x04001000 +----------+ 1862 | MHU | 1863 0x04000000 +----------+ 1864 1865Library at ROM 1866--------------- 1867 1868Please refer to the `ROMLIB Design`_ document. 1869 1870Firmware Image Package (FIP) 1871---------------------------- 1872 1873Using a Firmware Image Package (FIP) allows for packing bootloader images (and 1874potentially other payloads) into a single archive that can be loaded by TF-A 1875from non-volatile platform storage. A driver to load images from a FIP has 1876been added to the storage layer and allows a package to be read from supported 1877platform storage. A tool to create Firmware Image Packages is also provided 1878and described below. 1879 1880Firmware Image Package layout 1881~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1882 1883The FIP layout consists of a table of contents (ToC) followed by payload data. 1884The ToC itself has a header followed by one or more table entries. The ToC is 1885terminated by an end marker entry, and since the size of the ToC is 0 bytes, 1886the offset equals the total size of the FIP file. All ToC entries describe some 1887payload data that has been appended to the end of the binary package. With the 1888information provided in the ToC entry the corresponding payload data can be 1889retrieved. 1890 1891:: 1892 1893 ------------------ 1894 | ToC Header | 1895 |----------------| 1896 | ToC Entry 0 | 1897 |----------------| 1898 | ToC Entry 1 | 1899 |----------------| 1900 | ToC End Marker | 1901 |----------------| 1902 | | 1903 | Data 0 | 1904 | | 1905 |----------------| 1906 | | 1907 | Data 1 | 1908 | | 1909 ------------------ 1910 1911The ToC header and entry formats are described in the header file 1912``include/tools_share/firmware_image_package.h``. This file is used by both the 1913tool and TF-A. 1914 1915The ToC header has the following fields: 1916 1917:: 1918 1919 `name`: The name of the ToC. This is currently used to validate the header. 1920 `serial_number`: A non-zero number provided by the creation tool 1921 `flags`: Flags associated with this data. 1922 Bits 0-31: Reserved 1923 Bits 32-47: Platform defined 1924 Bits 48-63: Reserved 1925 1926A ToC entry has the following fields: 1927 1928:: 1929 1930 `uuid`: All files are referred to by a pre-defined Universally Unique 1931 IDentifier [UUID] . The UUIDs are defined in 1932 `include/tools_share/firmware_image_package.h`. The platform translates 1933 the requested image name into the corresponding UUID when accessing the 1934 package. 1935 `offset_address`: The offset address at which the corresponding payload data 1936 can be found. The offset is calculated from the ToC base address. 1937 `size`: The size of the corresponding payload data in bytes. 1938 `flags`: Flags associated with this entry. None are yet defined. 1939 1940Firmware Image Package creation tool 1941~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1942 1943The FIP creation tool can be used to pack specified images into a binary 1944package that can be loaded by TF-A from platform storage. The tool currently 1945only supports packing bootloader images. Additional image definitions can be 1946added to the tool as required. 1947 1948The tool can be found in ``tools/fiptool``. 1949 1950Loading from a Firmware Image Package (FIP) 1951~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1952 1953The Firmware Image Package (FIP) driver can load images from a binary package on 1954non-volatile platform storage. For the Arm development platforms, this is 1955currently NOR FLASH. 1956 1957Bootloader images are loaded according to the platform policy as specified by 1958the function ``plat_get_image_source()``. For the Arm development platforms, this 1959means the platform will attempt to load images from a Firmware Image Package 1960located at the start of NOR FLASH0. 1961 1962The Arm development platforms' policy is to only allow loading of a known set of 1963images. The platform policy can be modified to allow additional images. 1964 1965Use of coherent memory in TF-A 1966------------------------------ 1967 1968There might be loss of coherency when physical memory with mismatched 1969shareability, cacheability and memory attributes is accessed by multiple CPUs 1970(refer to section B2.9 of `Arm ARM`_ for more details). This possibility occurs 1971in TF-A during power up/down sequences when coherency, MMU and caches are 1972turned on/off incrementally. 1973 1974TF-A defines coherent memory as a region of memory with Device nGnRE attributes 1975in the translation tables. The translation granule size in TF-A is 4KB. This 1976is the smallest possible size of the coherent memory region. 1977 1978By default, all data structures which are susceptible to accesses with 1979mismatched attributes from various CPUs are allocated in a coherent memory 1980region (refer to section 2.1 of `Porting Guide`_). The coherent memory region 1981accesses are Outer Shareable, non-cacheable and they can be accessed 1982with the Device nGnRE attributes when the MMU is turned on. Hence, at the 1983expense of at least an extra page of memory, TF-A is able to work around 1984coherency issues due to mismatched memory attributes. 1985 1986The alternative to the above approach is to allocate the susceptible data 1987structures in Normal WriteBack WriteAllocate Inner shareable memory. This 1988approach requires the data structures to be designed so that it is possible to 1989work around the issue of mismatched memory attributes by performing software 1990cache maintenance on them. 1991 1992Disabling the use of coherent memory in TF-A 1993~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1994 1995It might be desirable to avoid the cost of allocating coherent memory on 1996platforms which are memory constrained. TF-A enables inclusion of coherent 1997memory in firmware images through the build flag ``USE_COHERENT_MEM``. 1998This flag is enabled by default. It can be disabled to choose the second 1999approach described above. 2000 2001The below sections analyze the data structures allocated in the coherent memory 2002region and the changes required to allocate them in normal memory. 2003 2004Coherent memory usage in PSCI implementation 2005~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2006 2007The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain 2008tree information for state management of power domains. By default, this data 2009structure is allocated in the coherent memory region in TF-A because it can be 2010accessed by multiple CPUs, either with caches enabled or disabled. 2011 2012.. code:: c 2013 2014 typedef struct non_cpu_pwr_domain_node { 2015 /* 2016 * Index of the first CPU power domain node level 0 which has this node 2017 * as its parent. 2018 */ 2019 unsigned int cpu_start_idx; 2020 2021 /* 2022 * Number of CPU power domains which are siblings of the domain indexed 2023 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx 2024 * -> cpu_start_idx + ncpus' have this node as their parent. 2025 */ 2026 unsigned int ncpus; 2027 2028 /* 2029 * Index of the parent power domain node. 2030 */ 2031 unsigned int parent_node; 2032 2033 plat_local_state_t local_state; 2034 2035 unsigned char level; 2036 2037 /* For indexing the psci_lock array*/ 2038 unsigned char lock_index; 2039 } non_cpu_pd_node_t; 2040 2041In order to move this data structure to normal memory, the use of each of its 2042fields must be analyzed. Fields like ``cpu_start_idx``, ``ncpus``, ``parent_node`` 2043``level`` and ``lock_index`` are only written once during cold boot. Hence removing 2044them from coherent memory involves only doing a clean and invalidate of the 2045cache lines after these fields are written. 2046 2047The field ``local_state`` can be concurrently accessed by multiple CPUs in 2048different cache states. A Lamport's Bakery lock ``psci_locks`` is used to ensure 2049mutual exclusion to this field and a clean and invalidate is needed after it 2050is written. 2051 2052Bakery lock data 2053~~~~~~~~~~~~~~~~ 2054 2055The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory 2056and is accessed by multiple CPUs with mismatched attributes. ``bakery_lock_t`` is 2057defined as follows: 2058 2059.. code:: c 2060 2061 typedef struct bakery_lock { 2062 /* 2063 * The lock_data is a bit-field of 2 members: 2064 * Bit[0] : choosing. This field is set when the CPU is 2065 * choosing its bakery number. 2066 * Bits[1 - 15] : number. This is the bakery number allocated. 2067 */ 2068 volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS]; 2069 } bakery_lock_t; 2070 2071It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU 2072fields can be read by all CPUs but only written to by the owning CPU. 2073 2074Depending upon the data cache line size, the per-CPU fields of the 2075``bakery_lock_t`` structure for multiple CPUs may exist on a single cache line. 2076These per-CPU fields can be read and written during lock contention by multiple 2077CPUs with mismatched memory attributes. Since these fields are a part of the 2078lock implementation, they do not have access to any other locking primitive to 2079safeguard against the resulting coherency issues. As a result, simple software 2080cache maintenance is not enough to allocate them in coherent memory. Consider 2081the following example. 2082 2083CPU0 updates its per-CPU field with data cache enabled. This write updates a 2084local cache line which contains a copy of the fields for other CPUs as well. Now 2085CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache 2086disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of 2087its field in any other cache line in the system. This operation will invalidate 2088the update made by CPU0 as well. 2089 2090To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure 2091has been redesigned. The changes utilise the characteristic of Lamport's Bakery 2092algorithm mentioned earlier. The bakery_lock structure only allocates the memory 2093for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks 2094needed for a CPU into a section ``bakery_lock``. The linker allocates the memory 2095for other cores by using the total size allocated for the bakery_lock section 2096and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to 2097perform software cache maintenance on the lock data structure without running 2098into coherency issues associated with mismatched attributes. 2099 2100The bakery lock data structure ``bakery_info_t`` is defined for use when 2101``USE_COHERENT_MEM`` is disabled as follows: 2102 2103.. code:: c 2104 2105 typedef struct bakery_info { 2106 /* 2107 * The lock_data is a bit-field of 2 members: 2108 * Bit[0] : choosing. This field is set when the CPU is 2109 * choosing its bakery number. 2110 * Bits[1 - 15] : number. This is the bakery number allocated. 2111 */ 2112 volatile uint16_t lock_data; 2113 } bakery_info_t; 2114 2115The ``bakery_info_t`` represents a single per-CPU field of one lock and 2116the combination of corresponding ``bakery_info_t`` structures for all CPUs in the 2117system represents the complete bakery lock. The view in memory for a system 2118with n bakery locks are: 2119 2120:: 2121 2122 bakery_lock section start 2123 |----------------| 2124 | `bakery_info_t`| <-- Lock_0 per-CPU field 2125 | Lock_0 | for CPU0 2126 |----------------| 2127 | `bakery_info_t`| <-- Lock_1 per-CPU field 2128 | Lock_1 | for CPU0 2129 |----------------| 2130 | .... | 2131 |----------------| 2132 | `bakery_info_t`| <-- Lock_N per-CPU field 2133 | Lock_N | for CPU0 2134 ------------------ 2135 | XXXXX | 2136 | Padding to | 2137 | next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate 2138 | Granule | continuous memory for remaining CPUs. 2139 ------------------ 2140 | `bakery_info_t`| <-- Lock_0 per-CPU field 2141 | Lock_0 | for CPU1 2142 |----------------| 2143 | `bakery_info_t`| <-- Lock_1 per-CPU field 2144 | Lock_1 | for CPU1 2145 |----------------| 2146 | .... | 2147 |----------------| 2148 | `bakery_info_t`| <-- Lock_N per-CPU field 2149 | Lock_N | for CPU1 2150 ------------------ 2151 | XXXXX | 2152 | Padding to | 2153 | next Cache WB | 2154 | Granule | 2155 ------------------ 2156 2157Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an 2158operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1 2159``bakery_lock`` section need to be fetched and appropriate cache operations need 2160to be performed for each access. 2161 2162On Arm Platforms, bakery locks are used in psci (``psci_locks``) and power controller 2163driver (``arm_lock``). 2164 2165Non Functional Impact of removing coherent memory 2166~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2167 2168Removal of the coherent memory region leads to the additional software overhead 2169of performing cache maintenance for the affected data structures. However, since 2170the memory where the data structures are allocated is cacheable, the overhead is 2171mostly mitigated by an increase in performance. 2172 2173There is however a performance impact for bakery locks, due to: 2174 2175- Additional cache maintenance operations, and 2176- Multiple cache line reads for each lock operation, since the bakery locks 2177 for each CPU are distributed across different cache lines. 2178 2179The implementation has been optimized to minimize this additional overhead. 2180Measurements indicate that when bakery locks are allocated in Normal memory, the 2181minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas 2182in Device memory the same is 2 micro seconds. The measurements were done on the 2183Juno Arm development platform. 2184 2185As mentioned earlier, almost a page of memory can be saved by disabling 2186``USE_COHERENT_MEM``. Each platform needs to consider these trade-offs to decide 2187whether coherent memory should be used. If a platform disables 2188``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can 2189optionally define macro ``PLAT_PERCPU_BAKERY_LOCK_SIZE`` (see the 2190`Porting Guide`_). Refer to the reference platform code for examples. 2191 2192Isolating code and read-only data on separate memory pages 2193---------------------------------------------------------- 2194 2195In the Armv8-A VMSA, translation table entries include fields that define the 2196properties of the target memory region, such as its access permissions. The 2197smallest unit of memory that can be addressed by a translation table entry is 2198a memory page. Therefore, if software needs to set different permissions on two 2199memory regions then it needs to map them using different memory pages. 2200 2201The default memory layout for each BL image is as follows: 2202 2203:: 2204 2205 | ... | 2206 +-------------------+ 2207 | Read-write data | 2208 +-------------------+ Page boundary 2209 | <Padding> | 2210 +-------------------+ 2211 | Exception vectors | 2212 +-------------------+ 2 KB boundary 2213 | <Padding> | 2214 +-------------------+ 2215 | Read-only data | 2216 +-------------------+ 2217 | Code | 2218 +-------------------+ BLx_BASE 2219 2220Note: The 2KB alignment for the exception vectors is an architectural 2221requirement. 2222 2223The read-write data start on a new memory page so that they can be mapped with 2224read-write permissions, whereas the code and read-only data below are configured 2225as read-only. 2226 2227However, the read-only data are not aligned on a page boundary. They are 2228contiguous to the code. Therefore, the end of the code section and the beginning 2229of the read-only data one might share a memory page. This forces both to be 2230mapped with the same memory attributes. As the code needs to be executable, this 2231means that the read-only data stored on the same memory page as the code are 2232executable as well. This could potentially be exploited as part of a security 2233attack. 2234 2235TF provides the build flag ``SEPARATE_CODE_AND_RODATA`` to isolate the code and 2236read-only data on separate memory pages. This in turn allows independent control 2237of the access permissions for the code and read-only data. In this case, 2238platform code gets a finer-grained view of the image layout and can 2239appropriately map the code region as executable and the read-only data as 2240execute-never. 2241 2242This has an impact on memory footprint, as padding bytes need to be introduced 2243between the code and read-only data to ensure the segregation of the two. To 2244limit the memory cost, this flag also changes the memory layout such that the 2245code and exception vectors are now contiguous, like so: 2246 2247:: 2248 2249 | ... | 2250 +-------------------+ 2251 | Read-write data | 2252 +-------------------+ Page boundary 2253 | <Padding> | 2254 +-------------------+ 2255 | Read-only data | 2256 +-------------------+ Page boundary 2257 | <Padding> | 2258 +-------------------+ 2259 | Exception vectors | 2260 +-------------------+ 2 KB boundary 2261 | <Padding> | 2262 +-------------------+ 2263 | Code | 2264 +-------------------+ BLx_BASE 2265 2266With this more condensed memory layout, the separation of read-only data will 2267add zero or one page to the memory footprint of each BL image. Each platform 2268should consider the trade-off between memory footprint and security. 2269 2270This build flag is disabled by default, minimising memory footprint. On Arm 2271platforms, it is enabled. 2272 2273Publish and Subscribe Framework 2274------------------------------- 2275 2276The Publish and Subscribe Framework allows EL3 components to define and publish 2277events, to which other EL3 components can subscribe. 2278 2279The following macros are provided by the framework: 2280 2281- ``REGISTER_PUBSUB_EVENT(event)``: Defines an event, and takes one argument, 2282 the event name, which must be a valid C identifier. All calls to 2283 ``REGISTER_PUBSUB_EVENT`` macro must be placed in the file 2284 ``pubsub_events.h``. 2285 2286- ``PUBLISH_EVENT_ARG(event, arg)``: Publishes a defined event, by iterating 2287 subscribed handlers and calling them in turn. The handlers will be passed the 2288 parameter ``arg``. The expected use-case is to broadcast an event. 2289 2290- ``PUBLISH_EVENT(event)``: Like ``PUBLISH_EVENT_ARG``, except that the value 2291 ``NULL`` is passed to subscribed handlers. 2292 2293- ``SUBSCRIBE_TO_EVENT(event, handler)``: Registers the ``handler`` to 2294 subscribe to ``event``. The handler will be executed whenever the ``event`` 2295 is published. 2296 2297- ``for_each_subscriber(event, subscriber)``: Iterates through all handlers 2298 subscribed for ``event``. ``subscriber`` must be a local variable of type 2299 ``pubsub_cb_t *``, and will point to each subscribed handler in turn during 2300 iteration. This macro can be used for those patterns that none of the 2301 ``PUBLISH_EVENT_*()`` macros cover. 2302 2303Publishing an event that wasn't defined using ``REGISTER_PUBSUB_EVENT`` will 2304result in build error. Subscribing to an undefined event however won't. 2305 2306Subscribed handlers must be of type ``pubsub_cb_t``, with following function 2307signature: 2308 2309:: 2310 2311 typedef void* (*pubsub_cb_t)(const void *arg); 2312 2313There may be arbitrary number of handlers registered to the same event. The 2314order in which subscribed handlers are notified when that event is published is 2315not defined. Subscribed handlers may be executed in any order; handlers should 2316not assume any relative ordering amongst them. 2317 2318Publishing an event on a PE will result in subscribed handlers executing on that 2319PE only; it won't cause handlers to execute on a different PE. 2320 2321Note that publishing an event on a PE blocks until all the subscribed handlers 2322finish executing on the PE. 2323 2324TF-A generic code publishes and subscribes to some events within. Platform 2325ports are discouraged from subscribing to them. These events may be withdrawn, 2326renamed, or have their semantics altered in the future. Platforms may however 2327register, publish, and subscribe to platform-specific events. 2328 2329Publish and Subscribe Example 2330~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2331 2332A publisher that wants to publish event ``foo`` would: 2333 2334- Define the event ``foo`` in the ``pubsub_events.h``. 2335 2336 :: 2337 2338 REGISTER_PUBSUB_EVENT(foo); 2339 2340- Depending on the nature of event, use one of ``PUBLISH_EVENT_*()`` macros to 2341 publish the event at the appropriate path and time of execution. 2342 2343A subscriber that wants to subscribe to event ``foo`` published above would 2344implement: 2345 2346.. code:: c 2347 2348 void *foo_handler(const void *arg) 2349 { 2350 void *result; 2351 2352 /* Do handling ... */ 2353 2354 return result; 2355 } 2356 2357 SUBSCRIBE_TO_EVENT(foo, foo_handler); 2358 2359 2360Reclaiming the BL31 initialization code 2361~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2362 2363A significant amount of the code used for the initialization of BL31 is never 2364needed again after boot time. In order to reduce the runtime memory 2365footprint, the memory used for this code can be reclaimed after initialization 2366has finished and be used for runtime data. 2367 2368The build option ``RECLAIM_INIT_CODE`` can be set to mark this boot time code 2369with a ``.text.init.*`` attribute which can be filtered and placed suitably 2370within the BL image for later reclamation by the platform. The platform can 2371specify the filter and the memory region for this init section in BL31 via the 2372plat.ld.S linker script. For example, on the FVP, this section is placed 2373overlapping the secondary CPU stacks so that after the cold boot is done, this 2374memory can be reclaimed for the stacks. The init memory section is initially 2375mapped with ``RO``, ``EXECUTE`` attributes. After BL31 initialization has 2376completed, the FVP changes the attributes of this section to ``RW``, 2377``EXECUTE_NEVER`` allowing it to be used for runtime data. The memory attributes 2378are changed within the ``bl31_plat_runtime_setup`` platform hook. The init 2379section section can be reclaimed for any data which is accessed after cold 2380boot initialization and it is upto the platform to make the decision. 2381 2382Performance Measurement Framework 2383--------------------------------- 2384 2385The Performance Measurement Framework (PMF) facilitates collection of 2386timestamps by registered services and provides interfaces to retrieve them 2387from within TF-A. A platform can choose to expose appropriate SMCs to 2388retrieve these collected timestamps. 2389 2390By default, the global physical counter is used for the timestamp 2391value and is read via ``CNTPCT_EL0``. The framework allows to retrieve 2392timestamps captured by other CPUs. 2393 2394Timestamp identifier format 2395~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2396 2397A PMF timestamp is uniquely identified across the system via the 2398timestamp ID or ``tid``. The ``tid`` is composed as follows: 2399 2400:: 2401 2402 Bits 0-7: The local timestamp identifier. 2403 Bits 8-9: Reserved. 2404 Bits 10-15: The service identifier. 2405 Bits 16-31: Reserved. 2406 2407#. The service identifier. Each PMF service is identified by a 2408 service name and a service identifier. Both the service name and 2409 identifier are unique within the system as a whole. 2410 2411#. The local timestamp identifier. This identifier is unique within a given 2412 service. 2413 2414Registering a PMF service 2415~~~~~~~~~~~~~~~~~~~~~~~~~ 2416 2417To register a PMF service, the ``PMF_REGISTER_SERVICE()`` macro from ``pmf.h`` 2418is used. The arguments required are the service name, the service ID, 2419the total number of local timestamps to be captured and a set of flags. 2420 2421The ``flags`` field can be specified as a bitwise-OR of the following values: 2422 2423:: 2424 2425 PMF_STORE_ENABLE: The timestamp is stored in memory for later retrieval. 2426 PMF_DUMP_ENABLE: The timestamp is dumped on the serial console. 2427 2428The ``PMF_REGISTER_SERVICE()`` reserves memory to store captured 2429timestamps in a PMF specific linker section at build time. 2430Additionally, it defines necessary functions to capture and 2431retrieve a particular timestamp for the given service at runtime. 2432 2433The macro ``PMF_REGISTER_SERVICE()`` only enables capturing PMF timestamps 2434from within TF-A. In order to retrieve timestamps from outside of TF-A, the 2435``PMF_REGISTER_SERVICE_SMC()`` macro must be used instead. This macro 2436accepts the same set of arguments as the ``PMF_REGISTER_SERVICE()`` 2437macro but additionally supports retrieving timestamps using SMCs. 2438 2439Capturing a timestamp 2440~~~~~~~~~~~~~~~~~~~~~ 2441 2442PMF timestamps are stored in a per-service timestamp region. On a 2443system with multiple CPUs, each timestamp is captured and stored 2444in a per-CPU cache line aligned memory region. 2445 2446Having registered the service, the ``PMF_CAPTURE_TIMESTAMP()`` macro can be 2447used to capture a timestamp at the location where it is used. The macro 2448takes the service name, a local timestamp identifier and a flag as arguments. 2449 2450The ``flags`` field argument can be zero, or ``PMF_CACHE_MAINT`` which 2451instructs PMF to do cache maintenance following the capture. Cache 2452maintenance is required if any of the service's timestamps are captured 2453with data cache disabled. 2454 2455To capture a timestamp in assembly code, the caller should use 2456``pmf_calc_timestamp_addr`` macro (defined in ``pmf_asm_macros.S``) to 2457calculate the address of where the timestamp would be stored. The 2458caller should then read ``CNTPCT_EL0`` register to obtain the timestamp 2459and store it at the determined address for later retrieval. 2460 2461Retrieving a timestamp 2462~~~~~~~~~~~~~~~~~~~~~~ 2463 2464From within TF-A, timestamps for individual CPUs can be retrieved using either 2465``PMF_GET_TIMESTAMP_BY_MPIDR()`` or ``PMF_GET_TIMESTAMP_BY_INDEX()`` macros. 2466These macros accept the CPU's MPIDR value, or its ordinal position 2467respectively. 2468 2469From outside TF-A, timestamps for individual CPUs can be retrieved by calling 2470into ``pmf_smc_handler()``. 2471 2472.. code:: c 2473 2474 Interface : pmf_smc_handler() 2475 Argument : unsigned int smc_fid, u_register_t x1, 2476 u_register_t x2, u_register_t x3, 2477 u_register_t x4, void *cookie, 2478 void *handle, u_register_t flags 2479 Return : uintptr_t 2480 2481 smc_fid: Holds the SMC identifier which is either `PMF_SMC_GET_TIMESTAMP_32` 2482 when the caller of the SMC is running in AArch32 mode 2483 or `PMF_SMC_GET_TIMESTAMP_64` when the caller is running in AArch64 mode. 2484 x1: Timestamp identifier. 2485 x2: The `mpidr` of the CPU for which the timestamp has to be retrieved. 2486 This can be the `mpidr` of a different core to the one initiating 2487 the SMC. In that case, service specific cache maintenance may be 2488 required to ensure the updated copy of the timestamp is returned. 2489 x3: A flags value that is either 0 or `PMF_CACHE_MAINT`. If 2490 `PMF_CACHE_MAINT` is passed, then the PMF code will perform a 2491 cache invalidate before reading the timestamp. This ensures 2492 an updated copy is returned. 2493 2494The remaining arguments, ``x4``, ``cookie``, ``handle`` and ``flags`` are unused 2495in this implementation. 2496 2497PMF code structure 2498~~~~~~~~~~~~~~~~~~ 2499 2500#. ``pmf_main.c`` consists of core functions that implement service registration, 2501 initialization, storing, dumping and retrieving timestamps. 2502 2503#. ``pmf_smc.c`` contains the SMC handling for registered PMF services. 2504 2505#. ``pmf.h`` contains the public interface to Performance Measurement Framework. 2506 2507#. ``pmf_asm_macros.S`` consists of macros to facilitate capturing timestamps in 2508 assembly code. 2509 2510#. ``pmf_helpers.h`` is an internal header used by ``pmf.h``. 2511 2512Armv8-A Architecture Extensions 2513------------------------------- 2514 2515TF-A makes use of Armv8-A Architecture Extensions where applicable. This 2516section lists the usage of Architecture Extensions, and build flags 2517controlling them. 2518 2519In general, and unless individually mentioned, the build options 2520``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` select the Architecture Extension to 2521target when building TF-A. Subsequent Arm Architecture Extensions are backward 2522compatible with previous versions. 2523 2524The build system only requires that ``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` have a 2525valid numeric value. These build options only control whether or not 2526Architecture Extension-specific code is included in the build. Otherwise, TF-A 2527targets the base Armv8.0-A architecture; i.e. as if ``ARM_ARCH_MAJOR`` == 8 2528and ``ARM_ARCH_MINOR`` == 0, which are also their respective default values. 2529 2530See also the *Summary of build options* in `User Guide`_. 2531 2532For details on the Architecture Extension and available features, please refer 2533to the respective Architecture Extension Supplement. 2534 2535Armv8.1-A 2536~~~~~~~~~ 2537 2538This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when 2539``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` >= 1. 2540 2541- The Compare and Swap instruction is used to implement spinlocks. Otherwise, 2542 the load-/store-exclusive instruction pair is used. 2543 2544Armv8.2-A 2545~~~~~~~~~ 2546 2547- The presence of ARMv8.2-TTCNP is detected at runtime. When it is present, the 2548 Common not Private (TTBRn_ELx.CnP) bit is enabled to indicate that multiple 2549 Processing Elements in the same Inner Shareable domain use the same 2550 translation table entries for a given stage of translation for a particular 2551 translation regime. 2552 2553Armv8.3-A 2554~~~~~~~~~ 2555 2556- Pointer authentication features of Armv8.3-A are unconditionally enabled in 2557 the Non-secure world so that lower ELs are allowed to use them without 2558 causing a trap to EL3. 2559 2560 In order to enable the Secure world to use it, ``CTX_INCLUDE_PAUTH_REGS`` 2561 must be set to 1. This will add all pointer authentication system registers 2562 to the context that is saved when doing a world switch. 2563 2564 The TF-A itself has support for pointer authentication at runtime 2565 that can be enabled by setting both options ``ENABLE_PAUTH`` and 2566 ``CTX_INCLUDE_PAUTH_REGS`` to 1. This enables pointer authentication in BL1, 2567 BL2, BL31, and the TSP if it is used. 2568 2569 These options are experimental features. 2570 2571 Note that Pointer Authentication is enabled for Non-secure world irrespective 2572 of the value of these build flags if the CPU supports it. 2573 2574 If ``ARM_ARCH_MAJOR == 8`` and ``ARM_ARCH_MINOR >= 3`` the code footprint of 2575 enabling PAuth is lower because the compiler will use the optimized 2576 PAuth instructions rather than the backwards-compatible ones. 2577 2578Armv7-A 2579~~~~~~~ 2580 2581This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 7. 2582 2583There are several Armv7-A extensions available. Obviously the TrustZone 2584extension is mandatory to support the TF-A bootloader and runtime services. 2585 2586Platform implementing an Armv7-A system can to define from its target 2587Cortex-A architecture through ``ARM_CORTEX_A<X> = yes`` in their 2588``platform.mk`` script. For example ``ARM_CORTEX_A15=yes`` for a 2589Cortex-A15 target. 2590 2591Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support. 2592Note that using neon at runtime has constraints on non secure wolrd context. 2593TF-A does not yet provide VFP context management. 2594 2595Directive ``ARM_CORTEX_A<x>`` and ``ARM_WITH_NEON`` are used to set 2596the toolchain target architecture directive. 2597 2598Platform may choose to not define straight the toolchain target architecture 2599directive by defining ``MARCH32_DIRECTIVE``. 2600I.e: 2601 2602:: 2603 2604 MARCH32_DIRECTIVE := -mach=armv7-a 2605 2606Code Structure 2607-------------- 2608 2609TF-A code is logically divided between the three boot loader stages mentioned 2610in the previous sections. The code is also divided into the following 2611categories (present as directories in the source code): 2612 2613- **Platform specific.** Choice of architecture specific code depends upon 2614 the platform. 2615- **Common code.** This is platform and architecture agnostic code. 2616- **Library code.** This code comprises of functionality commonly used by all 2617 other code. The PSCI implementation and other EL3 runtime frameworks reside 2618 as Library components. 2619- **Stage specific.** Code specific to a boot stage. 2620- **Drivers.** 2621- **Services.** EL3 runtime services (eg: SPD). Specific SPD services 2622 reside in the ``services/spd`` directory (e.g. ``services/spd/tspd``). 2623 2624Each boot loader stage uses code from one or more of the above mentioned 2625categories. Based upon the above, the code layout looks like this: 2626 2627:: 2628 2629 Directory Used by BL1? Used by BL2? Used by BL31? 2630 bl1 Yes No No 2631 bl2 No Yes No 2632 bl31 No No Yes 2633 plat Yes Yes Yes 2634 drivers Yes No Yes 2635 common Yes Yes Yes 2636 lib Yes Yes Yes 2637 services No No Yes 2638 2639The build system provides a non configurable build option IMAGE_BLx for each 2640boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE_BL1 will be 2641defined by the build system. This enables TF-A to compile certain code only 2642for specific boot loader stages 2643 2644All assembler files have the ``.S`` extension. The linker source files for each 2645boot stage have the extension ``.ld.S``. These are processed by GCC to create the 2646linker scripts which have the extension ``.ld``. 2647 2648FDTs provide a description of the hardware platform and are used by the Linux 2649kernel at boot time. These can be found in the ``fdts`` directory. 2650 2651References 2652---------- 2653 2654.. [#] `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D)`_ 2655.. [#] `Power State Coordination Interface PDD`_ 2656.. [#] `SMC Calling Convention PDD`_ 2657.. [#] `TF-A Interrupt Management Design guide`_. 2658 2659-------------- 2660 2661*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.* 2662 2663.. _Reset Design: ./reset-design.rst 2664.. _Porting Guide: ../getting_started/porting-guide.rst 2665.. _Firmware Update: ./firmware-update.rst 2666.. _PSCI PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2667.. _SMC calling convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf 2668.. _PSCI Library integration guide: ../getting_started/psci-lib-integration-guide.rst 2669.. _SMCCC: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf 2670.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2671.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2672.. _here: ../getting_started/psci-lib-integration-guide.rst 2673.. _cpu-specific-build-macros.rst: ./cpu-specific-build-macros.rst 2674.. _CPUBM: ./cpu-specific-build-macros.rst 2675.. _Arm ARM: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0487a.e/index.html 2676.. _User Guide: ../getting_started/user-guide.rst 2677.. _SMC Calling Convention PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf 2678.. _TF-A Interrupt Management Design guide: ./interrupt-framework-design.rst 2679.. _Xlat_tables design: xlat-tables-lib-v2-design.rst 2680.. _Exception Handling Framework: exception-handling.rst 2681.. _ROMLIB Design: romlib-design.rst 2682.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a 2683 2684.. |Image 1| image:: diagrams/rt-svc-descs-layout.png?raw=true 2685
