1Firmware Design 2=============== 3 4Trusted Firmware-A (TF-A) implements a subset of the Trusted Board Boot 5Requirements (TBBR) Platform Design Document (PDD) for Arm reference 6platforms. 7 8The TBB sequence starts when the platform is powered on and runs up 9to the stage where it hands-off control to firmware running in the normal 10world in DRAM. This is the cold boot path. 11 12TF-A also implements the `PSCI`_ as a runtime service. PSCI is the interface 13from normal world software to firmware implementing power management use-cases 14(for example, secondary CPU boot, hotplug and idle). Normal world software can 15access TF-A runtime services via the Arm SMC (Secure Monitor Call) instruction. 16The SMC instruction must be used as mandated by the SMC Calling Convention 17(`SMCCC`_). 18 19TF-A implements a framework for configuring and managing interrupts generated 20in either security state. The details of the interrupt management framework 21and its design can be found in :ref:`Interrupt Management Framework`. 22 23TF-A also implements a library for setting up and managing the translation 24tables. The details of this library can be found in 25:ref:`Translation (XLAT) Tables Library`. 26 27TF-A can be built to support either AArch64 or AArch32 execution state. 28 29.. note:: 30 The descriptions in this chapter are for the Arm TrustZone architecture. 31 For changes to the firmware design for the `Arm Confidential Compute 32 Architecture (Arm CCA)`_ please refer to the chapter :ref:`Realm Management 33 Extension (RME)`. 34 35Cold boot 36--------- 37 38The cold boot path starts when the platform is physically turned on. If 39``COLD_BOOT_SINGLE_CPU=0``, one of the CPUs released from reset is chosen as the 40primary CPU, and the remaining CPUs are considered secondary CPUs. The primary 41CPU is chosen through platform-specific means. The cold boot path is mainly 42executed by the primary CPU, other than essential CPU initialization executed by 43all CPUs. The secondary CPUs are kept in a safe platform-specific state until 44the primary CPU has performed enough initialization to boot them. 45 46Refer to the :ref:`CPU Reset` for more information on the effect of the 47``COLD_BOOT_SINGLE_CPU`` platform build option. 48 49The cold boot path in this implementation of TF-A depends on the execution 50state. For AArch64, it is divided into five steps (in order of execution): 51 52- Boot Loader stage 1 (BL1) *AP Trusted ROM* 53- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 54- Boot Loader stage 3-1 (BL31) *EL3 Runtime Software* 55- Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional) 56- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 57 58For AArch32, it is divided into four steps (in order of execution): 59 60- Boot Loader stage 1 (BL1) *AP Trusted ROM* 61- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 62- Boot Loader stage 3-2 (BL32) *EL3 Runtime Software* 63- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 64 65Arm development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a 66combination of the following types of memory regions. Each bootloader stage uses 67one or more of these memory regions. 68 69- Regions accessible from both non-secure and secure states. For example, 70 non-trusted SRAM, ROM and DRAM. 71- Regions accessible from only the secure state. For example, trusted SRAM and 72 ROM. The FVPs also implement the trusted DRAM which is statically 73 configured. Additionally, the Base FVPs and Juno development platform 74 configure the TrustZone Controller (TZC) to create a region in the DRAM 75 which is accessible only from the secure state. 76 77The sections below provide the following details: 78 79- dynamic configuration of Boot Loader stages 80- initialization and execution of the first three stages during cold boot 81- specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for 82 AArch32) entrypoint requirements for use by alternative Trusted Boot 83 Firmware in place of the provided BL1 and BL2 84 85Dynamic Configuration during cold boot 86~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 87 88Each of the Boot Loader stages may be dynamically configured if required by the 89platform. The Boot Loader stage may optionally specify a firmware 90configuration file and/or hardware configuration file as listed below: 91 92- FW_CONFIG - The firmware configuration file. Holds properties shared across 93 all BLx images. 94 An example is the "dtb-registry" node, which contains the information about 95 the other device tree configurations (load-address, size, image_id). 96- HW_CONFIG - The hardware configuration file. Can be shared by all Boot Loader 97 stages and also by the Normal World Rich OS. 98- TB_FW_CONFIG - Trusted Boot Firmware configuration file. Shared between BL1 99 and BL2. 100- SOC_FW_CONFIG - SoC Firmware configuration file. Used by BL31. 101- TOS_FW_CONFIG - Trusted OS Firmware configuration file. Used by Trusted OS 102 (BL32). 103- NT_FW_CONFIG - Non Trusted Firmware configuration file. Used by Non-trusted 104 firmware (BL33). 105 106The Arm development platforms use the Flattened Device Tree format for the 107dynamic configuration files. 108 109Each Boot Loader stage can pass up to 4 arguments via registers to the next 110stage. BL2 passes the list of the next images to execute to the *EL3 Runtime 111Software* (BL31 for AArch64 and BL32 for AArch32) via `arg0`. All the other 112arguments are platform defined. The Arm development platforms use the following 113convention: 114 115- BL1 passes the address of a meminfo_t structure to BL2 via ``arg1``. This 116 structure contains the memory layout available to BL2. 117- When dynamic configuration files are present, the firmware configuration for 118 the next Boot Loader stage is populated in the first available argument and 119 the generic hardware configuration is passed the next available argument. 120 For example, 121 122 - FW_CONFIG is loaded by BL1, then its address is passed in ``arg0`` to BL2. 123 - TB_FW_CONFIG address is retrieved by BL2 from FW_CONFIG device tree. 124 - If HW_CONFIG is loaded by BL1, then its address is passed in ``arg2`` to 125 BL2. Note, ``arg1`` is already used for meminfo_t. 126 - If SOC_FW_CONFIG is loaded by BL2, then its address is passed in ``arg1`` 127 to BL31. Note, ``arg0`` is used to pass the list of executable images. 128 - Similarly, if HW_CONFIG is loaded by BL1 or BL2, then its address is 129 passed in ``arg2`` to BL31. 130 - For other BL3x images, if the firmware configuration file is loaded by 131 BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded 132 then its address is passed in ``arg1``. 133 - In case SPMC_AT_EL3 is enabled, populate the BL32 image base, size and max 134 limit in the entry point information, since there is no platform function 135 to retrieve these in generic code. We choose ``arg2``, ``arg3`` and 136 ``arg4`` since the generic code uses ``arg1`` for stashing the SP manifest 137 size. The SPMC setup uses these arguments to update SP manifest with 138 actual SP's base address and it size. 139 - In case of the Arm FVP platform, FW_CONFIG address passed in ``arg1`` to 140 BL31/SP_MIN, and the SOC_FW_CONFIG and HW_CONFIG details are retrieved 141 from FW_CONFIG device tree. 142 143BL1 144~~~ 145 146This stage begins execution from the platform's reset vector at EL3. The reset 147address is platform dependent but it is usually located in a Trusted ROM area. 148The BL1 data section is copied to trusted SRAM at runtime. 149 150On the Arm development platforms, BL1 code starts execution from the reset 151vector defined by the constant ``BL1_RO_BASE``. The BL1 data section is copied 152to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``. 153 154The functionality implemented by this stage is as follows. 155 156Determination of boot path 157^^^^^^^^^^^^^^^^^^^^^^^^^^ 158 159Whenever a CPU is released from reset, BL1 needs to distinguish between a warm 160boot and a cold boot. This is done using platform-specific mechanisms (see the 161``plat_get_my_entrypoint()`` function in the :ref:`Porting Guide`). In the case 162of a warm boot, a CPU is expected to continue execution from a separate 163entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe 164platform-specific state (see the ``plat_secondary_cold_boot_setup()`` function in 165the :ref:`Porting Guide`) while the primary CPU executes the remaining cold boot 166path as described in the following sections. 167 168This step only applies when ``PROGRAMMABLE_RESET_ADDRESS=0``. Refer to the 169:ref:`CPU Reset` for more information on the effect of the 170``PROGRAMMABLE_RESET_ADDRESS`` platform build option. 171 172Architectural initialization 173^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 174 175BL1 performs minimal architectural initialization as follows. 176 177- Exception vectors 178 179 BL1 sets up simple exception vectors for both synchronous and asynchronous 180 exceptions. The default behavior upon receiving an exception is to populate 181 a status code in the general purpose register ``X0/R0`` and call the 182 ``plat_report_exception()`` function (see the :ref:`Porting Guide`). The 183 status code is one of: 184 185 For AArch64: 186 187 :: 188 189 0x0 : Synchronous exception from Current EL with SP_EL0 190 0x1 : IRQ exception from Current EL with SP_EL0 191 0x2 : FIQ exception from Current EL with SP_EL0 192 0x3 : System Error exception from Current EL with SP_EL0 193 0x4 : Synchronous exception from Current EL with SP_ELx 194 0x5 : IRQ exception from Current EL with SP_ELx 195 0x6 : FIQ exception from Current EL with SP_ELx 196 0x7 : System Error exception from Current EL with SP_ELx 197 0x8 : Synchronous exception from Lower EL using aarch64 198 0x9 : IRQ exception from Lower EL using aarch64 199 0xa : FIQ exception from Lower EL using aarch64 200 0xb : System Error exception from Lower EL using aarch64 201 0xc : Synchronous exception from Lower EL using aarch32 202 0xd : IRQ exception from Lower EL using aarch32 203 0xe : FIQ exception from Lower EL using aarch32 204 0xf : System Error exception from Lower EL using aarch32 205 206 For AArch32: 207 208 :: 209 210 0x10 : User mode 211 0x11 : FIQ mode 212 0x12 : IRQ mode 213 0x13 : SVC mode 214 0x16 : Monitor mode 215 0x17 : Abort mode 216 0x1a : Hypervisor mode 217 0x1b : Undefined mode 218 0x1f : System mode 219 220 The ``plat_report_exception()`` implementation on the Arm FVP port programs 221 the Versatile Express System LED register in the following format to 222 indicate the occurrence of an unexpected exception: 223 224 :: 225 226 SYS_LED[0] - Security state (Secure=0/Non-Secure=1) 227 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0) 228 For AArch32 it is always 0x0 229 SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value 230 of the status code 231 232 A write to the LED register reflects in the System LEDs (S6LED0..7) in the 233 CLCD window of the FVP. 234 235 BL1 does not expect to receive any exceptions other than the SMC exception. 236 For the latter, BL1 installs a simple stub. The stub expects to receive a 237 limited set of SMC types (determined by their function IDs in the general 238 purpose register ``X0/R0``): 239 240 - ``BL1_SMC_RUN_IMAGE``: This SMC is raised by BL2 to make BL1 pass control 241 to EL3 Runtime Software. 242 - All SMCs listed in section "BL1 SMC Interface" in the :ref:`Firmware Update (FWU)` 243 Design Guide are supported for AArch64 only. These SMCs are currently 244 not supported when BL1 is built for AArch32. 245 246 Any other SMC leads to an assertion failure. 247 248- CPU initialization 249 250 BL1 calls the ``reset_handler`` macro/function which in turn calls the CPU 251 specific reset handler function (see the section: "CPU specific operations 252 framework"). 253 254Platform initialization 255^^^^^^^^^^^^^^^^^^^^^^^ 256 257On Arm platforms, BL1 performs the following platform initializations: 258 259- Enable the Trusted Watchdog. 260- Initialize the console. 261- Configure the Interconnect to enable hardware coherency. 262- Enable the MMU and map the memory it needs to access. 263- Configure any required platform storage to load the next bootloader image 264 (BL2). 265- If the BL1 dynamic configuration file, ``TB_FW_CONFIG``, is available, then 266 load it to the platform defined address and make it available to BL2 via 267 ``arg0``. 268- Configure the system timer and program the `CNTFRQ_EL0` for use by NS-BL1U 269 and NS-BL2U firmware update images. 270 271Firmware Update detection and execution 272^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 273 274After performing platform setup, BL1 common code calls 275``bl1_plat_get_next_image_id()`` to determine if :ref:`Firmware Update (FWU)` is 276required or to proceed with the normal boot process. If the platform code 277returns ``BL2_IMAGE_ID`` then the normal boot sequence is executed as described 278in the next section, else BL1 assumes that :ref:`Firmware Update (FWU)` is 279required and execution passes to the first image in the 280:ref:`Firmware Update (FWU)` process. In either case, BL1 retrieves a descriptor 281of the next image by calling ``bl1_plat_get_image_desc()``. The image descriptor 282contains an ``entry_point_info_t`` structure, which BL1 uses to initialize the 283execution state of the next image. 284 285BL2 image load and execution 286^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 287 288In the normal boot flow, BL1 execution continues as follows: 289 290#. BL1 prints the following string from the primary CPU to indicate successful 291 execution of the BL1 stage: 292 293 :: 294 295 "Booting Trusted Firmware" 296 297#. BL1 loads a BL2 raw binary image from platform storage, at a 298 platform-specific base address. Prior to the load, BL1 invokes 299 ``bl1_plat_handle_pre_image_load()`` which allows the platform to update or 300 use the image information. If the BL2 image file is not present or if 301 there is not enough free trusted SRAM the following error message is 302 printed: 303 304 :: 305 306 "Failed to load BL2 firmware." 307 308#. BL1 invokes ``bl1_plat_handle_post_image_load()`` which again is intended 309 for platforms to take further action after image load. This function must 310 populate the necessary arguments for BL2, which may also include the memory 311 layout. Further description of the memory layout can be found later 312 in this document. 313 314#. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at 315 Secure SVC mode (for AArch32), starting from its load address. 316 317BL2 318~~~ 319 320BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure 321SVC mode (for AArch32) . BL2 is linked against and loaded at a platform-specific 322base address (more information can be found later in this document). 323The functionality implemented by BL2 is as follows. 324 325Architectural initialization 326^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 327 328For AArch64, BL2 performs the minimal architectural initialization required 329for subsequent stages of TF-A and normal world software. EL1 and EL0 are given 330access to Floating Point and Advanced SIMD registers by setting the 331``CPACR.FPEN`` bits. 332 333For AArch32, the minimal architectural initialization required for subsequent 334stages of TF-A and normal world software is taken care of in BL1 as both BL1 335and BL2 execute at PL1. 336 337Platform initialization 338^^^^^^^^^^^^^^^^^^^^^^^ 339 340On Arm platforms, BL2 performs the following platform initializations: 341 342- Initialize the console. 343- Configure any required platform storage to allow loading further bootloader 344 images. 345- Enable the MMU and map the memory it needs to access. 346- Perform platform security setup to allow access to controlled components. 347- Reserve some memory for passing information to the next bootloader image 348 EL3 Runtime Software and populate it. 349- Define the extents of memory available for loading each subsequent 350 bootloader image. 351- If BL1 has passed TB_FW_CONFIG dynamic configuration file in ``arg0``, 352 then parse it. 353 354Image loading in BL2 355^^^^^^^^^^^^^^^^^^^^ 356 357BL2 generic code loads the images based on the list of loadable images 358provided by the platform. BL2 passes the list of executable images 359provided by the platform to the next handover BL image. 360 361The list of loadable images provided by the platform may also contain 362dynamic configuration files. The files are loaded and can be parsed as 363needed in the ``bl2_plat_handle_post_image_load()`` function. These 364configuration files can be passed to next Boot Loader stages as arguments 365by updating the corresponding entrypoint information in this function. 366 367SCP_BL2 (System Control Processor Firmware) image load 368^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 369 370Some systems have a separate System Control Processor (SCP) for power, clock, 371reset and system control. BL2 loads the optional SCP_BL2 image from platform 372storage into a platform-specific region of secure memory. The subsequent 373handling of SCP_BL2 is platform specific. For example, on the Juno Arm 374development platform port the image is transferred into SCP's internal memory 375using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM 376memory. The SCP executes SCP_BL2 and signals to the Application Processor (AP) 377for BL2 execution to continue. 378 379EL3 Runtime Software image load 380^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 381 382BL2 loads the EL3 Runtime Software image from platform storage into a platform- 383specific address in trusted SRAM. If there is not enough memory to load the 384image or image is missing it leads to an assertion failure. 385 386AArch64 BL32 (Secure-EL1 Payload) image load 387^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 388 389BL2 loads the optional BL32 image from platform storage into a platform- 390specific region of secure memory. The image executes in the secure world. BL2 391relies on BL31 to pass control to the BL32 image, if present. Hence, BL2 392populates a platform-specific area of memory with the entrypoint/load-address 393of the BL32 image. The value of the Saved Processor Status Register (``SPSR``) 394for entry into BL32 is not determined by BL2, it is initialized by the 395Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for 396managing interaction with BL32. This information is passed to BL31. 397 398BL33 (Non-trusted Firmware) image load 399^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 400 401BL2 loads the BL33 image (e.g. UEFI or other test or boot software) from 402platform storage into non-secure memory as defined by the platform. 403 404BL2 relies on EL3 Runtime Software to pass control to BL33 once secure state 405initialization is complete. Hence, BL2 populates a platform-specific area of 406memory with the entrypoint and Saved Program Status Register (``SPSR``) of the 407normal world software image. The entrypoint is the load address of the BL33 408image. The ``SPSR`` is determined as specified in Section 5.13 of the 409`PSCI`_. This information is passed to the EL3 Runtime Software. 410 411AArch64 BL31 (EL3 Runtime Software) execution 412^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 413 414BL2 execution continues as follows: 415 416#. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the 417 BL31 entrypoint. The exception is handled by the SMC exception handler 418 installed by BL1. 419 420#. BL1 turns off the MMU and flushes the caches. It clears the 421 ``SCTLR_EL3.M/I/C`` bits, flushes the data cache to the point of coherency 422 and invalidates the TLBs. 423 424#. BL1 passes control to BL31 at the specified entrypoint at EL3. 425 426Running BL2 at EL3 execution level 427~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 428 429Some platforms have a non-TF-A Boot ROM that expects the next boot stage 430to execute at EL3. On these platforms, TF-A BL1 is a waste of memory 431as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid 432this waste, a special mode enables BL2 to execute at EL3, which allows 433a non-TF-A Boot ROM to load and jump directly to BL2. This mode is selected 434when the build flag RESET_TO_BL2 is enabled. 435The main differences in this mode are: 436 437#. BL2 includes the reset code and the mailbox mechanism to differentiate 438 cold boot and warm boot. It runs at EL3 doing the arch 439 initialization required for EL3. 440 441#. BL2 does not receive the meminfo information from BL1 anymore. This 442 information can be passed by the Boot ROM or be internal to the 443 BL2 image. 444 445#. Since BL2 executes at EL3, BL2 jumps directly to the next image, 446 instead of invoking the RUN_IMAGE SMC call. 447 448 449We assume 3 different types of BootROM support on the platform: 450 451#. The Boot ROM always jumps to the same address, for both cold 452 and warm boot. In this case, we will need to keep a resident part 453 of BL2 whose memory cannot be reclaimed by any other image. The 454 linker script defines the symbols __TEXT_RESIDENT_START__ and 455 __TEXT_RESIDENT_END__ that allows the platform to configure 456 correctly the memory map. 457#. The platform has some mechanism to indicate the jump address to the 458 Boot ROM. Platform code can then program the jump address with 459 psci_warmboot_entrypoint during cold boot. 460#. The platform has some mechanism to program the reset address using 461 the PROGRAMMABLE_RESET_ADDRESS feature. Platform code can then 462 program the reset address with psci_warmboot_entrypoint during 463 cold boot, bypassing the boot ROM for warm boot. 464 465In the last 2 cases, no part of BL2 needs to remain resident at 466runtime. In the first 2 cases, we expect the Boot ROM to be able to 467differentiate between warm and cold boot, to avoid loading BL2 again 468during warm boot. 469 470This functionality can be tested with FVP loading the image directly 471in memory and changing the address where the system jumps at reset. 472For example: 473 474 -C cluster0.cpu0.RVBAR=0x4022000 475 --data cluster0.cpu0=bl2.bin@0x4022000 476 477With this configuration, FVP is like a platform of the first case, 478where the Boot ROM jumps always to the same address. For simplification, 479BL32 is loaded in DRAM in this case, to avoid other images reclaiming 480BL2 memory. 481 482 483AArch64 BL31 484~~~~~~~~~~~~ 485 486The image for this stage is loaded by BL2 and BL1 passes control to BL31 at 487EL3. BL31 executes solely in trusted SRAM. BL31 is linked against and 488loaded at a platform-specific base address (more information can be found later 489in this document). The functionality implemented by BL31 is as follows. 490 491Architectural initialization 492^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 493 494Currently, BL31 performs a similar architectural initialization to BL1 as 495far as system register settings are concerned. Since BL1 code resides in ROM, 496architectural initialization in BL31 allows override of any previous 497initialization done by BL1. 498 499BL31 initializes the per-CPU data framework, which provides a cache of 500frequently accessed per-CPU data optimised for fast, concurrent manipulation 501on different CPUs. This buffer includes pointers to per-CPU contexts, crash 502buffer, CPU reset and power down operations, PSCI data, platform data and so on. 503 504It then replaces the exception vectors populated by BL1 with its own. BL31 505exception vectors implement more elaborate support for handling SMCs since this 506is the only mechanism to access the runtime services implemented by BL31 (PSCI 507for example). BL31 checks each SMC for validity as specified by the 508`SMC Calling Convention`_ before passing control to the required SMC 509handler routine. 510 511BL31 programs the ``CNTFRQ_EL0`` register with the clock frequency of the system 512counter, which is provided by the platform. 513 514Platform initialization 515^^^^^^^^^^^^^^^^^^^^^^^ 516 517BL31 performs detailed platform initialization, which enables normal world 518software to function correctly. 519 520On Arm platforms, this consists of the following: 521 522- Initialize the console. 523- Configure the Interconnect to enable hardware coherency. 524- Enable the MMU and map the memory it needs to access. 525- Initialize the generic interrupt controller. 526- Initialize the power controller device. 527- Detect the system topology. 528 529Runtime services initialization 530^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 531 532BL31 is responsible for initializing the runtime services. One of them is PSCI. 533 534As part of the PSCI initializations, BL31 detects the system topology. It also 535initializes the data structures that implement the state machine used to track 536the state of power domain nodes. The state can be one of ``OFF``, ``RUN`` or 537``RETENTION``. All secondary CPUs are initially in the ``OFF`` state. The cluster 538that the primary CPU belongs to is ``ON``; any other cluster is ``OFF``. It also 539initializes the locks that protect them. BL31 accesses the state of a CPU or 540cluster immediately after reset and before the data cache is enabled in the 541warm boot path. It is not currently possible to use 'exclusive' based spinlocks, 542therefore BL31 uses locks based on Lamport's Bakery algorithm instead. 543 544The runtime service framework and its initialization is described in more 545detail in the "EL3 runtime services framework" section below. 546 547Details about the status of the PSCI implementation are provided in the 548"Power State Coordination Interface" section below. 549 550AArch64 BL32 (Secure-EL1 Payload) image initialization 551^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 552 553If a BL32 image is present then there must be a matching Secure-EL1 Payload 554Dispatcher (SPD) service (see later for details). During initialization 555that service must register a function to carry out initialization of BL32 556once the runtime services are fully initialized. BL31 invokes such a 557registered function to initialize BL32 before running BL33. This initialization 558is not necessary for AArch32 SPs. 559 560Details on BL32 initialization and the SPD's role are described in the 561:ref:`firmware_design_sel1_spd` section below. 562 563BL33 (Non-trusted Firmware) execution 564^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 565 566EL3 Runtime Software initializes the EL2 or EL1 processor context for normal- 567world cold boot, ensuring that no secure state information finds its way into 568the non-secure execution state. EL3 Runtime Software uses the entrypoint 569information provided by BL2 to jump to the Non-trusted firmware image (BL33) 570at the highest available Exception Level (EL2 if available, otherwise EL1). 571 572Using alternative Trusted Boot Firmware in place of BL1 & BL2 (AArch64 only) 573~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 574 575Some platforms have existing implementations of Trusted Boot Firmware that 576would like to use TF-A BL31 for the EL3 Runtime Software. To enable this 577firmware architecture it is important to provide a fully documented and stable 578interface between the Trusted Boot Firmware and BL31. 579 580Future changes to the BL31 interface will be done in a backwards compatible 581way, and this enables these firmware components to be independently enhanced/ 582updated to develop and exploit new functionality. 583 584Required CPU state when calling ``bl31_entrypoint()`` during cold boot 585^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 586 587This function must only be called by the primary CPU. 588 589On entry to this function the calling primary CPU must be executing in AArch64 590EL3, little-endian data access, and all interrupt sources masked: 591 592:: 593 594 PSTATE.EL = 3 595 PSTATE.RW = 1 596 PSTATE.DAIF = 0xf 597 SCTLR_EL3.EE = 0 598 599X0 and X1 can be used to pass information from the Trusted Boot Firmware to the 600platform code in BL31: 601 602:: 603 604 X0 : Reserved for common TF-A information 605 X1 : Platform specific information 606 607BL31 zero-init sections (e.g. ``.bss``) should not contain valid data on entry, 608these will be zero filled prior to invoking platform setup code. 609 610Use of the X0 and X1 parameters 611''''''''''''''''''''''''''''''' 612 613The parameters are platform specific and passed from ``bl31_entrypoint()`` to 614``bl31_early_platform_setup()``. The value of these parameters is never directly 615used by the common BL31 code. 616 617The convention is that ``X0`` conveys information regarding the BL31, BL32 and 618BL33 images from the Trusted Boot firmware and ``X1`` can be used for other 619platform specific purpose. This convention allows platforms which use TF-A's 620BL1 and BL2 images to transfer additional platform specific information from 621Secure Boot without conflicting with future evolution of TF-A using ``X0`` to 622pass a ``bl31_params`` structure. 623 624BL31 common and SPD initialization code depends on image and entrypoint 625information about BL33 and BL32, which is provided via BL31 platform APIs. 626This information is required until the start of execution of BL33. This 627information can be provided in a platform defined manner, e.g. compiled into 628the platform code in BL31, or provided in a platform defined memory location 629by the Trusted Boot firmware, or passed from the Trusted Boot Firmware via the 630Cold boot Initialization parameters. This data may need to be cleaned out of 631the CPU caches if it is provided by an earlier boot stage and then accessed by 632BL31 platform code before the caches are enabled. 633 634TF-A's BL2 implementation passes a ``bl31_params`` structure in 635``X0`` and the Arm development platforms interpret this in the BL31 platform 636code. 637 638MMU, Data caches & Coherency 639'''''''''''''''''''''''''''' 640 641BL31 does not depend on the enabled state of the MMU, data caches or 642interconnect coherency on entry to ``bl31_entrypoint()``. If these are disabled 643on entry, these should be enabled during ``bl31_plat_arch_setup()``. 644 645Data structures used in the BL31 cold boot interface 646'''''''''''''''''''''''''''''''''''''''''''''''''''' 647 648In the cold boot flow, ``entry_point_info`` is used to represent the execution 649state of an image; that is, the state of general purpose registers, PC, and 650SPSR. 651 652There are two variants of this structure, for AArch64: 653 654.. code:: c 655 656 typedef struct entry_point_info { 657 param_header_t h; 658 uintptr_t pc; 659 uint32_t spsr; 660 661 aapcs64_params_t args; 662 } 663 664and, AArch32: 665 666.. code:: c 667 668 typedef struct entry_point_info { 669 param_header_t h; 670 uintptr_t pc; 671 uint32_t spsr; 672 673 uintptr_t lr_svc; 674 aapcs32_params_t args; 675 } entry_point_info_t; 676 677These structures are designed to support compatibility and independent 678evolution of the structures and the firmware images. For example, a version of 679BL31 that can interpret the BL3x image information from different versions of 680BL2, a platform that uses an extended entry_point_info structure to convey 681additional register information to BL31, or a ELF image loader that can convey 682more details about the firmware images. 683 684To support these scenarios the structures are versioned and sized, which enables 685BL31 to detect which information is present and respond appropriately. The 686``param_header`` is defined to capture this information: 687 688.. code:: c 689 690 typedef struct param_header { 691 uint8_t type; /* type of the structure */ 692 uint8_t version; /* version of this structure */ 693 uint16_t size; /* size of this structure in bytes */ 694 uint32_t attr; /* attributes */ 695 } param_header_t; 696 697In `entry_point_info`, Bits 0 and 5 of ``attr`` field are used to encode the 698security state; in other words, whether the image is to be executed in Secure, 699Non-Secure, or Realm mode. 700 701Other structures using this format are ``image_info`` and ``bl31_params``. The 702code that allocates and populates these structures must set the header fields 703appropriately, the ``SET_PARAM_HEAD()`` macro is defined to simplify this 704action. 705 706Required CPU state for BL31 Warm boot initialization 707^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 708 709When requesting a CPU power-on, or suspending a running CPU, TF-A provides 710the platform power management code with a Warm boot initialization 711entry-point, to be invoked by the CPU immediately after the reset handler. 712On entry to the Warm boot initialization function the calling CPU must be in 713AArch64 EL3, little-endian data access and all interrupt sources masked: 714 715:: 716 717 PSTATE.EL = 3 718 PSTATE.RW = 1 719 PSTATE.DAIF = 0xf 720 SCTLR_EL3.EE = 0 721 722The PSCI implementation will initialize the processor state and ensure that the 723platform power management code is then invoked as required to initialize all 724necessary system, cluster and CPU resources. 725 726AArch32 EL3 Runtime Software entrypoint interface 727~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 728 729To enable this firmware architecture it is important to provide a fully 730documented and stable interface between the Trusted Boot Firmware and the 731AArch32 EL3 Runtime Software. 732 733Future changes to the entrypoint interface will be done in a backwards 734compatible way, and this enables these firmware components to be independently 735enhanced/updated to develop and exploit new functionality. 736 737Required CPU state when entering during cold boot 738^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 739 740This function must only be called by the primary CPU. 741 742On entry to this function the calling primary CPU must be executing in AArch32 743EL3, little-endian data access, and all interrupt sources masked: 744 745:: 746 747 PSTATE.AIF = 0x7 748 SCTLR.EE = 0 749 750R0 and R1 are used to pass information from the Trusted Boot Firmware to the 751platform code in AArch32 EL3 Runtime Software: 752 753:: 754 755 R0 : Reserved for common TF-A information 756 R1 : Platform specific information 757 758Use of the R0 and R1 parameters 759''''''''''''''''''''''''''''''' 760 761The parameters are platform specific and the convention is that ``R0`` conveys 762information regarding the BL3x images from the Trusted Boot firmware and ``R1`` 763can be used for other platform specific purpose. This convention allows 764platforms which use TF-A's BL1 and BL2 images to transfer additional platform 765specific information from Secure Boot without conflicting with future 766evolution of TF-A using ``R0`` to pass a ``bl_params`` structure. 767 768The AArch32 EL3 Runtime Software is responsible for entry into BL33. This 769information can be obtained in a platform defined manner, e.g. compiled into 770the AArch32 EL3 Runtime Software, or provided in a platform defined memory 771location by the Trusted Boot firmware, or passed from the Trusted Boot Firmware 772via the Cold boot Initialization parameters. This data may need to be cleaned 773out of the CPU caches if it is provided by an earlier boot stage and then 774accessed by AArch32 EL3 Runtime Software before the caches are enabled. 775 776When using AArch32 EL3 Runtime Software, the Arm development platforms pass a 777``bl_params`` structure in ``R0`` from BL2 to be interpreted by AArch32 EL3 Runtime 778Software platform code. 779 780MMU, Data caches & Coherency 781'''''''''''''''''''''''''''' 782 783AArch32 EL3 Runtime Software must not depend on the enabled state of the MMU, 784data caches or interconnect coherency in its entrypoint. They must be explicitly 785enabled if required. 786 787Data structures used in cold boot interface 788''''''''''''''''''''''''''''''''''''''''''' 789 790The AArch32 EL3 Runtime Software cold boot interface uses ``bl_params`` instead 791of ``bl31_params``. The ``bl_params`` structure is based on the convention 792described in AArch64 BL31 cold boot interface section. 793 794Required CPU state for warm boot initialization 795^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 796 797When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3 798Runtime Software must ensure execution of a warm boot initialization entrypoint. 799If TF-A BL1 is used and the PROGRAMMABLE_RESET_ADDRESS build flag is false, 800then AArch32 EL3 Runtime Software must ensure that BL1 branches to the warm 801boot entrypoint by arranging for the BL1 platform function, 802plat_get_my_entrypoint(), to return a non-zero value. 803 804In this case, the warm boot entrypoint must be in AArch32 EL3, little-endian 805data access and all interrupt sources masked: 806 807:: 808 809 PSTATE.AIF = 0x7 810 SCTLR.EE = 0 811 812The warm boot entrypoint may be implemented by using TF-A 813``psci_warmboot_entrypoint()`` function. In that case, the platform must fulfil 814the pre-requisites mentioned in the :ref:`Porting Guide`. 815 816EL3 runtime services framework 817------------------------------ 818 819Software executing in the non-secure state and in the secure state at exception 820levels lower than EL3 will request runtime services using the Secure Monitor 821Call (SMC) instruction. These requests will follow the convention described in 822the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function 823identifiers to each SMC request and describes how arguments are passed and 824returned. 825 826The EL3 runtime services framework enables the development of services by 827different providers that can be easily integrated into final product firmware. 828The following sections describe the framework which facilitates the 829registration, initialization and use of runtime services in EL3 Runtime 830Software (BL31). 831 832The design of the runtime services depends heavily on the concepts and 833definitions described in the `SMCCC`_, in particular SMC Function IDs, Owning 834Entity Numbers (OEN), Fast and Yielding calls, and the SMC32 and SMC64 calling 835conventions. Please refer to that document for more detailed explanation of 836these terms. 837 838The following runtime services are expected to be implemented first. They have 839not all been instantiated in the current implementation. 840 841#. Standard service calls 842 843 This service is for management of the entire system. The Power State 844 Coordination Interface (`PSCI`_) is the first set of standard service calls 845 defined by Arm (see PSCI section later). 846 847#. Secure-EL1 Payload Dispatcher service 848 849 If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then 850 it also requires a *Secure Monitor* at EL3 to switch the EL1 processor 851 context between the normal world (EL1/EL2) and trusted world (Secure-EL1). 852 The Secure Monitor will make these world switches in response to SMCs. The 853 `SMCCC`_ provides for such SMCs with the Trusted OS Call and Trusted 854 Application Call OEN ranges. 855 856 The interface between the EL3 Runtime Software and the Secure-EL1 Payload is 857 not defined by the `SMCCC`_ or any other standard. As a result, each 858 Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime 859 service - within TF-A this service is referred to as the Secure-EL1 Payload 860 Dispatcher (SPD). 861 862 TF-A provides a Test Secure-EL1 Payload (TSP) and its associated Dispatcher 863 (TSPD). Details of SPD design and TSP/TSPD operation are described in the 864 :ref:`firmware_design_sel1_spd` section below. 865 866#. CPU implementation service 867 868 This service will provide an interface to CPU implementation specific 869 services for a given platform e.g. access to processor errata workarounds. 870 This service is currently unimplemented. 871 872Additional services for Arm Architecture, SiP and OEM calls can be implemented. 873Each implemented service handles a range of SMC function identifiers as 874described in the `SMCCC`_. 875 876Registration 877~~~~~~~~~~~~ 878 879A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying 880the name of the service, the range of OENs covered, the type of service and 881initialization and call handler functions. This macro instantiates a ``const struct rt_svc_desc`` for the service with these details (see ``runtime_svc.h``). 882This structure is allocated in a special ELF section ``.rt_svc_descs``, enabling 883the framework to find all service descriptors included into BL31. 884 885The specific service for a SMC Function is selected based on the OEN and call 886type of the Function ID, and the framework uses that information in the service 887descriptor to identify the handler for the SMC Call. 888 889The service descriptors do not include information to identify the precise set 890of SMC function identifiers supported by this service implementation, the 891security state from which such calls are valid nor the capability to support 89264-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately 893to these aspects of a SMC call is the responsibility of the service 894implementation, the framework is focused on integration of services from 895different providers and minimizing the time taken by the framework before the 896service handler is invoked. 897 898Details of the parameters, requirements and behavior of the initialization and 899call handling functions are provided in the following sections. 900 901Initialization 902~~~~~~~~~~~~~~ 903 904``runtime_svc_init()`` in ``runtime_svc.c`` initializes the runtime services 905framework running on the primary CPU during cold boot as part of the BL31 906initialization. This happens prior to initializing a Trusted OS and running 907Normal world boot firmware that might in turn use these services. 908Initialization involves validating each of the declared runtime service 909descriptors, calling the service initialization function and populating the 910index used for runtime lookup of the service. 911 912The BL31 linker script collects all of the declared service descriptors into a 913single array and defines symbols that allow the framework to locate and traverse 914the array, and determine its size. 915 916The framework does basic validation of each descriptor to halt firmware 917initialization if service declaration errors are detected. The framework does 918not check descriptors for the following error conditions, and may behave in an 919unpredictable manner under such scenarios: 920 921#. Overlapping OEN ranges 922#. Multiple descriptors for the same range of OENs and ``call_type`` 923#. Incorrect range of owning entity numbers for a given ``call_type`` 924 925Once validated, the service ``init()`` callback is invoked. This function carries 926out any essential EL3 initialization before servicing requests. The ``init()`` 927function is only invoked on the primary CPU during cold boot. If the service 928uses per-CPU data this must either be initialized for all CPUs during this call, 929or be done lazily when a CPU first issues an SMC call to that service. If 930``init()`` returns anything other than ``0``, this is treated as an initialization 931error and the service is ignored: this does not cause the firmware to halt. 932 933The OEN and call type fields present in the SMC Function ID cover a total of 934128 distinct services, but in practice a single descriptor can cover a range of 935OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a 936service handler, the framework uses an array of 128 indices that map every 937distinct OEN/call-type combination either to one of the declared services or to 938indicate the service is not handled. This ``rt_svc_descs_indices[]`` array is 939populated for all of the OENs covered by a service after the service ``init()`` 940function has reported success. So a service that fails to initialize will never 941have it's ``handle()`` function invoked. 942 943The following figure shows how the ``rt_svc_descs_indices[]`` index maps the SMC 944Function ID call type and OEN onto a specific service handler in the 945``rt_svc_descs[]`` array. 946 947|Image 1| 948 949.. _handling-an-smc: 950 951Handling an SMC 952~~~~~~~~~~~~~~~ 953 954When the EL3 runtime services framework receives a Secure Monitor Call, the SMC 955Function ID is passed in W0 from the lower exception level (as per the 956`SMCCC`_). If the calling register width is AArch32, it is invalid to invoke an 957SMC Function which indicates the SMC64 calling convention: such calls are 958ignored and return the Unknown SMC Function Identifier result code ``0xFFFFFFFF`` 959in R0/X0. 960 961Bit[31] (fast/yielding call) and bits[29:24] (owning entity number) of the SMC 962Function ID are combined to index into the ``rt_svc_descs_indices[]`` array. The 963resulting value might indicate a service that has no handler, in this case the 964framework will also report an Unknown SMC Function ID. Otherwise, the value is 965used as a further index into the ``rt_svc_descs[]`` array to locate the required 966service and handler. 967 968The service's ``handle()`` callback is provided with five of the SMC parameters 969directly, the others are saved into memory for retrieval (if needed) by the 970handler. The handler is also provided with an opaque ``handle`` for use with the 971supporting library for parameter retrieval, setting return values and context 972manipulation. The ``flags`` parameter indicates the security state of the caller 973and the state of the SVE hint bit per the SMCCCv1.3. The framework finally sets 974up the execution stack for the handler, and invokes the services ``handle()`` 975function. 976 977On return from the handler the result registers are populated in X0-X7 as needed 978before restoring the stack and CPU state and returning from the original SMC. 979 980Exception Handling Framework 981---------------------------- 982 983Please refer to the :ref:`Exception Handling Framework` document. 984 985Power State Coordination Interface 986---------------------------------- 987 988TODO: Provide design walkthrough of PSCI implementation. 989 990The PSCI v1.1 specification categorizes APIs as optional and mandatory. All the 991mandatory APIs in PSCI v1.1, PSCI v1.0 and in PSCI v0.2 draft specification 992`PSCI`_ are implemented. The table lists the PSCI v1.1 APIs and their support 993in generic code. 994 995An API implementation might have a dependency on platform code e.g. CPU_SUSPEND 996requires the platform to export a part of the implementation. Hence the level 997of support of the mandatory APIs depends upon the support exported by the 998platform port as well. The Juno and FVP (all variants) platforms export all the 999required support. 1000 1001+-----------------------------+-------------+-------------------------------+ 1002| PSCI v1.1 API | Supported | Comments | 1003+=============================+=============+===============================+ 1004| ``PSCI_VERSION`` | Yes | The version returned is 1.1 | 1005+-----------------------------+-------------+-------------------------------+ 1006| ``CPU_SUSPEND`` | Yes\* | | 1007+-----------------------------+-------------+-------------------------------+ 1008| ``CPU_OFF`` | Yes\* | | 1009+-----------------------------+-------------+-------------------------------+ 1010| ``CPU_ON`` | Yes\* | | 1011+-----------------------------+-------------+-------------------------------+ 1012| ``AFFINITY_INFO`` | Yes | | 1013+-----------------------------+-------------+-------------------------------+ 1014| ``MIGRATE`` | Yes\*\* | | 1015+-----------------------------+-------------+-------------------------------+ 1016| ``MIGRATE_INFO_TYPE`` | Yes\*\* | | 1017+-----------------------------+-------------+-------------------------------+ 1018| ``MIGRATE_INFO_CPU`` | Yes\*\* | | 1019+-----------------------------+-------------+-------------------------------+ 1020| ``SYSTEM_OFF`` | Yes\* | | 1021+-----------------------------+-------------+-------------------------------+ 1022| ``SYSTEM_RESET`` | Yes\* | | 1023+-----------------------------+-------------+-------------------------------+ 1024| ``PSCI_FEATURES`` | Yes | | 1025+-----------------------------+-------------+-------------------------------+ 1026| ``CPU_FREEZE`` | No | | 1027+-----------------------------+-------------+-------------------------------+ 1028| ``CPU_DEFAULT_SUSPEND`` | No | | 1029+-----------------------------+-------------+-------------------------------+ 1030| ``NODE_HW_STATE`` | Yes\* | | 1031+-----------------------------+-------------+-------------------------------+ 1032| ``SYSTEM_SUSPEND`` | Yes\* | | 1033+-----------------------------+-------------+-------------------------------+ 1034| ``PSCI_SET_SUSPEND_MODE`` | No | | 1035+-----------------------------+-------------+-------------------------------+ 1036| ``PSCI_STAT_RESIDENCY`` | Yes\* | | 1037+-----------------------------+-------------+-------------------------------+ 1038| ``PSCI_STAT_COUNT`` | Yes\* | | 1039+-----------------------------+-------------+-------------------------------+ 1040| ``SYSTEM_RESET2`` | Yes\* | | 1041+-----------------------------+-------------+-------------------------------+ 1042| ``MEM_PROTECT`` | Yes\* | | 1043+-----------------------------+-------------+-------------------------------+ 1044| ``MEM_PROTECT_CHECK_RANGE`` | Yes\* | | 1045+-----------------------------+-------------+-------------------------------+ 1046 1047\*Note : These PSCI APIs require platform power management hooks to be 1048registered with the generic PSCI code to be supported. 1049 1050\*\*Note : These PSCI APIs require appropriate Secure Payload Dispatcher 1051hooks to be registered with the generic PSCI code to be supported. 1052 1053The PSCI implementation in TF-A is a library which can be integrated with 1054AArch64 or AArch32 EL3 Runtime Software for Armv8-A systems. A guide to 1055integrating the PSCI library for EL3 Runtime Software can be found 1056at :ref:`Porting Guide`. 1057 1058DSU driver 1059---------- 1060 1061Platforms that include a DSU (DynamIQ Shared Unit) can define 1062the ``USE_DSU_DRIVER`` build flag to enable the DSU driver. 1063This driver is responsible for configuring DSU-related powerdown 1064and power feature settings, enabling access to PMU registers at EL1 1065using ``dsu_driver_init()`` and for preserving the context of DSU 1066PMU system registers. 1067 1068To support the DSU driver, platforms must define the ``plat_dsu_data`` 1069structure. 1070 1071.. _firmware_design_sel1_spd: 1072 1073Secure-EL1 Payloads and Dispatchers 1074----------------------------------- 1075 1076On a production system that includes a Trusted OS running in Secure-EL1/EL0, 1077the Trusted OS is coupled with a companion runtime service in the BL31 1078firmware. This service is responsible for the initialisation of the Trusted 1079OS and all communications with it. The Trusted OS is the BL32 stage of the 1080boot flow in TF-A. The firmware will attempt to locate, load and execute a 1081BL32 image. 1082 1083TF-A uses a more general term for the BL32 software that runs at Secure-EL1 - 1084the *Secure-EL1 Payload* - as it is not always a Trusted OS. 1085 1086TF-A provides a Test Secure-EL1 Payload (TSP) and a Test Secure-EL1 Payload 1087Dispatcher (TSPD) service as an example of how a Trusted OS is supported on a 1088production system using the Runtime Services Framework. On such a system, the 1089Test BL32 image and service are replaced by the Trusted OS and its dispatcher 1090service. The TF-A build system expects that the dispatcher will define the 1091build flag ``NEED_BL32`` to enable it to include the BL32 in the build either 1092as a binary or to compile from source depending on whether the ``BL32`` build 1093option is specified or not. 1094 1095The TSP runs in Secure-EL1. It is designed to demonstrate synchronous 1096communication with the normal-world software running in EL1/EL2. Communication 1097is initiated by the normal-world software 1098 1099- either directly through a Fast SMC (as defined in the `SMCCC`_) 1100 1101- or indirectly through a `PSCI`_ SMC. The `PSCI`_ implementation in turn 1102 informs the TSPD about the requested power management operation. This allows 1103 the TSP to prepare for or respond to the power state change 1104 1105The TSPD service is responsible for. 1106 1107- Initializing the TSP 1108 1109- Routing requests and responses between the secure and the non-secure 1110 states during the two types of communications just described 1111 1112Initializing a BL32 Image 1113~~~~~~~~~~~~~~~~~~~~~~~~~ 1114 1115The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing 1116the BL32 image. It needs access to the information passed by BL2 to BL31 to do 1117so. This is provided by: 1118 1119.. code:: c 1120 1121 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t); 1122 1123which returns a reference to the ``entry_point_info`` structure corresponding to 1124the image which will be run in the specified security state. The SPD uses this 1125API to get entry point information for the SECURE image, BL32. 1126 1127In the absence of a BL32 image, BL31 passes control to the normal world 1128bootloader image (BL33). When the BL32 image is present, it is typical 1129that the SPD wants control to be passed to BL32 first and then later to BL33. 1130 1131To do this the SPD has to register a BL32 initialization function during 1132initialization of the SPD service. The BL32 initialization function has this 1133prototype: 1134 1135.. code:: c 1136 1137 int32_t init(void); 1138 1139and is registered using the ``bl31_register_bl32_init()`` function. 1140 1141TF-A supports two approaches for the SPD to pass control to BL32 before 1142returning through EL3 and running the non-trusted firmware (BL33): 1143 1144#. In the BL32 setup function, use ``bl31_set_next_image_type()`` to 1145 request that the exit from ``bl31_main()`` is to the BL32 entrypoint in 1146 Secure-EL1. BL31 will exit to BL32 using the asynchronous method by 1147 calling ``bl31_prepare_next_image_entry()`` and ``el3_exit()``. 1148 1149 When the BL32 has completed initialization at Secure-EL1, it returns to 1150 BL31 by issuing an SMC, using a Function ID allocated to the SPD. On 1151 receipt of this SMC, the SPD service handler should switch the CPU context 1152 from trusted to normal world and use the ``bl31_set_next_image_type()`` and 1153 ``bl31_prepare_next_image_entry()`` functions to set up the initial return to 1154 the normal world firmware BL33. On return from the handler the framework 1155 will exit to EL2 and run BL33. 1156 1157#. The BL32 setup function registers an initialization function using 1158 ``bl31_register_bl32_init()`` which provides a SPD-defined mechanism to 1159 invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32 1160 entrypoint. 1161 1162 .. note:: 1163 The Test SPD service included with TF-A provides one implementation 1164 of such a mechanism. 1165 1166 On completion BL32 returns control to BL31 via a SMC, and on receipt the 1167 SPD service handler invokes the synchronous call return mechanism to return 1168 to the BL32 initialization function. On return from this function, 1169 ``bl31_main()`` will set up the return to the normal world firmware BL33 and 1170 continue the boot process in the normal world. 1171 1172Exception handling in BL31 1173-------------------------- 1174 1175When exception occurs, PE must execute handler corresponding to exception. The 1176location in memory where the handler is stored is called the exception vector. 1177For ARM architecture, exception vectors are stored in a table, called the exception 1178vector table. 1179 1180Each EL (except EL0) has its own vector table, VBAR_ELn register stores the base 1181of vector table. Refer to `AArch64 exception vector table`_ 1182 1183Current EL with SP_EL0 1184~~~~~~~~~~~~~~~~~~~~~~ 1185 1186- Sync exception : Not expected except for BRK instruction, its debugging tool which 1187 a programmer may place at specific points in a program, to check the state of 1188 processor flags at these points in the code. 1189 1190- IRQ/FIQ : Unexpected exception, panic 1191 1192- SError : "plat_handle_el3_ea", defaults to panic 1193 1194Current EL with SP_ELx 1195~~~~~~~~~~~~~~~~~~~~~~ 1196 1197- Sync exception : Unexpected exception, panic 1198 1199- IRQ/FIQ : Unexpected exception, panic 1200 1201- SError : "plat_handle_el3_ea" Except for special handling of lower EL's SError exception 1202 which gets triggered in EL3 when PSTATE.A is unmasked. Its only applicable when lower 1203 EL's EA is routed to EL3 (FFH_SUPPORT=1). 1204 1205Lower EL Exceptions 1206~~~~~~~~~~~~~~~~~~~ 1207 1208Applies to all the exceptions in both AArch64/AArch32 mode of lower EL. 1209 1210Before handling any lower EL exception, we synchronize the errors at EL3 entry to ensure 1211that any errors pertaining to lower EL is isolated/identified. If we continue without 1212identifying these errors early on then these errors will trigger in EL3 (as SError from 1213current EL) any time after PSTATE.A is unmasked. This is wrong because the error originated 1214in lower EL but exception happened in EL3. 1215 1216To solve this problem, synchronize the errors at EL3 entry and check for any pending 1217errors (async EA). If there is no pending error then continue with original exception. 1218If there is a pending error then, handle them based on routing model of EA's. Refer to 1219:ref:`Reliability, Availability, and Serviceability (RAS) Extensions` for details about 1220routing models. 1221 1222- KFH : Reflect it back to lower EL using **reflect_pending_async_ea_to_lower_el()** 1223 1224- FFH : Handle the synchronized error first using **handle_pending_async_ea()** after 1225 that continue with original exception. It is the only scenario where EL3 is capable 1226 of doing nested exception handling. 1227 1228After synchronizing and handling lower EL SErrors, unmask EA (PSTATE.A) to ensure 1229that any further EA's caused by EL3 are caught. 1230 1231Crash Reporting in BL31 1232----------------------- 1233 1234BL31 implements a scheme for reporting the processor state when an unhandled 1235exception is encountered. The reporting mechanism attempts to preserve all the 1236register contents and report it via a dedicated UART (PL011 console). BL31 1237reports the general purpose, EL3, Secure EL1 and some EL2 state registers. 1238 1239A dedicated per-CPU crash stack is maintained by BL31 and this is retrieved via 1240the per-CPU pointer cache. The implementation attempts to minimise the memory 1241required for this feature. The file ``crash_reporting.S`` contains the 1242implementation for crash reporting. 1243 1244The sample crash output is shown below. 1245 1246:: 1247 1248 x0 = 0x000000002a4a0000 1249 x1 = 0x0000000000000001 1250 x2 = 0x0000000000000002 1251 x3 = 0x0000000000000003 1252 x4 = 0x0000000000000004 1253 x5 = 0x0000000000000005 1254 x6 = 0x0000000000000006 1255 x7 = 0x0000000000000007 1256 x8 = 0x0000000000000008 1257 x9 = 0x0000000000000009 1258 x10 = 0x0000000000000010 1259 x11 = 0x0000000000000011 1260 x12 = 0x0000000000000012 1261 x13 = 0x0000000000000013 1262 x14 = 0x0000000000000014 1263 x15 = 0x0000000000000015 1264 x16 = 0x0000000000000016 1265 x17 = 0x0000000000000017 1266 x18 = 0x0000000000000018 1267 x19 = 0x0000000000000019 1268 x20 = 0x0000000000000020 1269 x21 = 0x0000000000000021 1270 x22 = 0x0000000000000022 1271 x23 = 0x0000000000000023 1272 x24 = 0x0000000000000024 1273 x25 = 0x0000000000000025 1274 x26 = 0x0000000000000026 1275 x27 = 0x0000000000000027 1276 x28 = 0x0000000000000028 1277 x29 = 0x0000000000000029 1278 x30 = 0x0000000088000b78 1279 scr_el3 = 0x000000000003073d 1280 sctlr_el3 = 0x00000000b0cd183f 1281 cptr_el3 = 0x0000000000000000 1282 tcr_el3 = 0x000000008080351c 1283 daif = 0x00000000000002c0 1284 mair_el3 = 0x00000000004404ff 1285 spsr_el3 = 0x0000000060000349 1286 elr_el3 = 0x0000000088000114 1287 ttbr0_el3 = 0x0000000004018201 1288 esr_el3 = 0x00000000be000000 1289 far_el3 = 0x0000000000000000 1290 spsr_el1 = 0x0000000000000000 1291 elr_el1 = 0x0000000000000000 1292 spsr_abt = 0x0000000000000000 1293 spsr_und = 0x0000000000000000 1294 spsr_irq = 0x0000000000000000 1295 spsr_fiq = 0x0000000000000000 1296 sctlr_el1 = 0x0000000030d00800 1297 actlr_el1 = 0x0000000000000000 1298 cpacr_el1 = 0x0000000000000000 1299 csselr_el1 = 0x0000000000000000 1300 sp_el1 = 0x0000000000000000 1301 esr_el1 = 0x0000000000000000 1302 ttbr0_el1 = 0x0000000000000000 1303 ttbr1_el1 = 0x0000000000000000 1304 mair_el1 = 0x0000000000000000 1305 amair_el1 = 0x0000000000000000 1306 tcr_el1 = 0x0000000000000000 1307 tpidr_el1 = 0x0000000000000000 1308 tpidr_el0 = 0x0000000000000000 1309 tpidrro_el0 = 0x0000000000000000 1310 par_el1 = 0x0000000000000000 1311 mpidr_el1 = 0x0000000080000000 1312 afsr0_el1 = 0x0000000000000000 1313 afsr1_el1 = 0x0000000000000000 1314 contextidr_el1 = 0x0000000000000000 1315 vbar_el1 = 0x0000000000000000 1316 cntp_ctl_el0 = 0x0000000000000000 1317 cntp_cval_el0 = 0x0000000000000000 1318 cntv_ctl_el0 = 0x0000000000000000 1319 cntv_cval_el0 = 0x0000000000000000 1320 cntkctl_el1 = 0x0000000000000000 1321 sp_el0 = 0x0000000004014940 1322 isr_el1 = 0x0000000000000000 1323 dacr32_el2 = 0x0000000000000000 1324 ifsr32_el2 = 0x0000000000000000 1325 icc_hppir0_el1 = 0x00000000000003ff 1326 icc_hppir1_el1 = 0x00000000000003ff 1327 icc_ctlr_el3 = 0x0000000000080400 1328 gicd_ispendr regs (Offsets 0x200-0x278) 1329 Offset Value 1330 0x200: 0x0000000000000000 1331 0x208: 0x0000000000000000 1332 0x210: 0x0000000000000000 1333 0x218: 0x0000000000000000 1334 0x220: 0x0000000000000000 1335 0x228: 0x0000000000000000 1336 0x230: 0x0000000000000000 1337 0x238: 0x0000000000000000 1338 0x240: 0x0000000000000000 1339 0x248: 0x0000000000000000 1340 0x250: 0x0000000000000000 1341 0x258: 0x0000000000000000 1342 0x260: 0x0000000000000000 1343 0x268: 0x0000000000000000 1344 0x270: 0x0000000000000000 1345 0x278: 0x0000000000000000 1346 1347Guidelines for Reset Handlers 1348----------------------------- 1349 1350TF-A implements a framework that allows CPU and platform ports to perform 1351actions very early after a CPU is released from reset in both the cold and warm 1352boot paths. This is done by calling the ``reset_handler`` macro/function in both 1353the BL1 and BL31 images. It in turn calls the platform and CPU specific reset 1354handling functions. 1355 1356Details for implementing a CPU specific reset handler can be found in 1357:ref:`firmware_design_cpu_specific_reset_handling`. Details for implementing a 1358platform specific reset handler can be found in the :ref:`Porting Guide` (see 1359the``plat_reset_handler()`` function). 1360 1361When adding functionality to a reset handler, keep in mind that if a different 1362reset handling behavior is required between the first and the subsequent 1363invocations of the reset handling code, this should be detected at runtime. 1364In other words, the reset handler should be able to detect whether an action has 1365already been performed and act as appropriate. Possible courses of actions are, 1366e.g. skip the action the second time, or undo/redo it. 1367 1368.. _configuring-secure-interrupts: 1369 1370Configuring secure interrupts 1371----------------------------- 1372 1373The GIC driver is responsible for performing initial configuration of secure 1374interrupts on the platform. To this end, the platform is expected to provide the 1375GIC driver (either GICv2 or GICv3, as selected by the platform) with the 1376interrupt configuration during the driver initialisation. 1377 1378Secure interrupt configuration are specified in an array of secure interrupt 1379properties. In this scheme, in both GICv2 and GICv3 driver data structures, the 1380``interrupt_props`` member points to an array of interrupt properties. Each 1381element of the array specifies the interrupt number and its attributes 1382(priority, group, configuration). Each element of the array shall be populated 1383by the macro ``INTR_PROP_DESC()``. The macro takes the following arguments: 1384 1385- 13-bit interrupt number, 1386 1387- 8-bit interrupt priority, 1388 1389- Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``, 1390 ``INTR_TYPE_NS``), 1391 1392- Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or 1393 ``GIC_INTR_CFG_EDGE``). 1394 1395.. _firmware_design_cpu_ops_fwk: 1396 1397CPU specific operations framework 1398--------------------------------- 1399 1400Certain aspects of the Armv8-A architecture are implementation defined, 1401that is, certain behaviours are not architecturally defined, but must be 1402defined and documented by individual processor implementations. TF-A 1403implements a framework which categorises the common implementation defined 1404behaviours and allows a processor to export its implementation of that 1405behaviour. The categories are: 1406 1407#. Processor specific reset sequence. 1408 1409#. Processor specific power down sequences. 1410 1411#. Processor specific register dumping as a part of crash reporting. 1412 1413#. Errata status reporting. 1414 1415Each of the above categories fulfils a different requirement. 1416 1417#. allows any processor specific initialization before the caches and MMU 1418 are turned on, like implementation of errata workarounds, entry into 1419 the intra-cluster coherency domain etc. 1420 1421#. allows each processor to implement the power down sequence mandated in 1422 its Technical Reference Manual (TRM). 1423 1424#. allows a processor to provide additional information to the developer 1425 in the event of a crash, for example Cortex-A53 has registers which 1426 can expose the data cache contents. 1427 1428#. allows a processor to define a function that inspects and reports the status 1429 of all errata workarounds on that processor. 1430 1431Please note that only 2. is mandated by the TRM. 1432 1433The CPU specific operations framework scales to accommodate a large number of 1434different CPUs during power down and reset handling. The platform can specify 1435any CPU optimization it wants to enable for each CPU. It can also specify 1436the CPU errata workarounds to be applied for each CPU type during reset 1437handling by defining CPU errata compile time macros. Details on these macros 1438can be found in the :ref:`Arm CPU Specific Build Macros` document. 1439 1440The CPU specific operations framework depends on the ``cpu_ops`` structure which 1441needs to be exported for each type of CPU in the platform. It is defined in 1442``include/lib/cpus/aarch64/cpu_macros.S`` and has the following fields : ``midr``, 1443``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and 1444``cpu_reg_dump()``. 1445 1446The CPU specific files in ``lib/cpus`` export a ``cpu_ops`` data structure with 1447suitable handlers for that CPU. For example, ``lib/cpus/aarch64/cortex_a53.S`` 1448exports the ``cpu_ops`` for Cortex-A53 CPU. According to the platform 1449configuration, these CPU specific files must be included in the build by 1450the platform makefile. The generic CPU specific operations framework code exists 1451in ``lib/cpus/aarch64/cpu_helpers.S``. 1452 1453CPU PCS 1454~~~~~~~ 1455 1456All assembly functions in CPU files are asked to follow a modified version of 1457the Procedure Call Standard (PCS) in their internals. This is done to ensure 1458calling these functions from outside the file doesn't unexpectedly corrupt 1459registers in the very early environment and to help the internals to be easier 1460to understand. Please see the :ref:`firmware_design_cpu_errata_implementation` 1461for any function specific restrictions. 1462 1463+--------------+---------------------------------+ 1464| register | use | 1465+==============+=================================+ 1466| x0 - x15 | scratch | 1467+--------------+---------------------------------+ 1468| x16, x17 | do not use (used by the linker) | 1469+--------------+---------------------------------+ 1470| x18 | do not use (platform register) | 1471+--------------+---------------------------------+ 1472| x19 - x28 | callee saved | 1473+--------------+---------------------------------+ 1474| x29, x30 | FP, LR | 1475+--------------+---------------------------------+ 1476 1477.. _firmware_design_cpu_specific_reset_handling: 1478 1479CPU specific Reset Handling 1480~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1481 1482After a reset, the state of the CPU when it calls generic reset handler is: 1483MMU turned off, both instruction and data caches turned off, not part 1484of any coherency domain and no stack. 1485 1486The BL entrypoint code first invokes the ``plat_reset_handler()`` to allow 1487the platform to perform any system initialization required and any system 1488errata workarounds that needs to be applied. The ``get_cpu_ops_ptr()`` reads 1489the current CPU midr, finds the matching ``cpu_ops`` entry in the ``cpu_ops`` 1490array and returns it. Note that only the part number and implementer fields 1491in midr are used to find the matching ``cpu_ops`` entry. The ``reset_func()`` in 1492the returned ``cpu_ops`` is then invoked which executes the required reset 1493handling for that CPU and also any errata workarounds enabled by the platform. 1494 1495It should be defined using the ``cpu_reset_func_{start,end}`` macros and its 1496body may only clobber x0 to x14 with x14 being the cpu_rev parameter. The cpu 1497file should also include a call to ``cpu_reset_prologue`` at the start of the 1498file for errata to work correctly. 1499 1500CPU specific power down sequence 1501~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1502 1503During the BL31 initialization sequence, the pointer to the matching ``cpu_ops`` 1504entry is stored in per-CPU data by ``cpu_data_init_cpu_ops()`` so that it can be quickly 1505retrieved during power down sequences. 1506 1507Various CPU drivers register handlers to perform power down at certain power 1508levels for that specific CPU. The PSCI service, upon receiving a power down 1509request, determines the highest power level at which to execute power down 1510sequence for a particular CPU. It uses the ``prepare_cpu_pwr_dwn()`` function to 1511pick the right power down handler for the requested level. The function 1512retrieves ``cpu_ops`` pointer member of per-CPU data, and from that, further 1513retrieves ``cpu_pwr_down_ops`` array, and indexes into the required level. If the 1514requested power level is higher than what a CPU driver supports, the handler 1515registered for highest level is invoked. 1516 1517At runtime the platform hooks for power down are invoked by the PSCI service to 1518perform platform specific operations during a power down sequence, for example 1519turning off CCI coherency during a cluster power down. 1520 1521Newer CPUs include a feature called "powerdown abandon". The feature is based on 1522the observation that events like GIC wakeups have a high likelihood of happening 1523while the core is in the middle of its powerdown sequence (at ``wfi``). Older 1524cores will powerdown and immediately power back up when this happens. To save on 1525the work and latency involved, the newer cores will "give up" mid way through if 1526no context has been lost yet. This is possible as the powerdown operation is 1527lengthy and a large part of it does not lose context. 1528 1529To cater for this possibility, the powerdown hook will be called a second time 1530after a wakeup. The expectation is that the first call will operate as before, 1531while the second call will undo anything the first call did. This should be done 1532statelessly, for example by toggling the relevant bits. 1533 1534CPU specific register reporting during crash 1535~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1536 1537If the crash reporting is enabled in BL31, when a crash occurs, the crash 1538reporting framework calls ``do_cpu_reg_dump`` which retrieves the matching 1539``cpu_ops`` using ``get_cpu_ops_ptr()`` function. The ``cpu_reg_dump()`` in 1540``cpu_ops`` is invoked, which then returns the CPU specific register values to 1541be reported and a pointer to the ASCII list of register names in a format 1542expected by the crash reporting framework. 1543 1544.. _firmware_design_cpu_errata_implementation: 1545 1546CPU errata implementation 1547~~~~~~~~~~~~~~~~~~~~~~~~~ 1548 1549Errata workarounds for CPUs supported in TF-A are applied during both cold and 1550warm boots, shortly after reset. Individual Errata workarounds are enabled as 1551build options. Some errata workarounds have potential run-time implications; 1552therefore some are enabled by default, others not. Platform ports shall 1553override build options to enable or disable errata as appropriate. The CPU 1554drivers take care of applying errata workarounds that are enabled and applicable 1555to a given CPU. 1556 1557Each erratum has a build flag in ``lib/cpus/cpu-ops.mk`` of the form: 1558``ERRATA_<cpu_num>_<erratum_id>``. It also has a short description in 1559:ref:`arm_cpu_macros_errata_workarounds` on when it should apply. 1560 1561Errata framework 1562^^^^^^^^^^^^^^^^ 1563 1564The errata framework is a convention and a small library to allow errata to be 1565automatically discovered. It enables compliant errata to be automatically 1566applied and reported at runtime (either by status reporting or the errata ABI). 1567 1568To write a compliant mitigation for erratum number ``erratum_id`` on a cpu that 1569declared itself (with ``declare_cpu_ops``) as ``cpu_name`` one needs 3 things: 1570 1571#. A CPU revision checker function: ``check_erratum_<cpu_name>_<erratum_id>`` 1572 1573 It should check whether this erratum applies on this revision of this CPU. 1574 It will be called with the CPU revision as its first parameter (x0) and 1575 should return one of ``ERRATA_APPLIES`` or ``ERRATA_NOT_APPLIES``. 1576 1577 It may only clobber x0 to x4. The rest should be treated as callee-saved. 1578 1579#. A workaround function: ``erratum_<cpu_name>_<erratum_id>_wa`` 1580 1581 It should obtain the cpu revision (with ``cpu_get_rev_var``), call its 1582 revision checker, and perform the mitigation, should the erratum apply. 1583 1584 It may only clobber x0 to x8. The rest should be treated as callee-saved. 1585 1586#. Register itself to the framework 1587 1588 Do this with 1589 ``add_erratum_entry <cpu_name>, ERRATUM(<erratum_id>), <errata_flag>`` 1590 where the ``errata_flag`` is the enable flag in ``cpu-ops.mk`` described 1591 above. 1592 1593See the next section on how to do this easily. 1594 1595.. note:: 1596 1597 CVEs have the format ``CVE_<year>_<number>``. To fit them in the framework, the 1598 ``erratum_id`` for the checker and the workaround functions become the 1599 ``number`` part of its name and the ``ERRATUM(<number>)`` part of the 1600 registration should instead be ``CVE(<year>, <number>)``. In the extremely 1601 unlikely scenario where a CVE and an erratum numbers clash, the CVE number 1602 should be prefixed with a zero. 1603 1604 Also, their build flag should be ``WORKAROUND_CVE_<year>_<number>``. 1605 1606.. note:: 1607 1608 AArch32 uses the legacy convention. The checker function has the format 1609 ``check_errata_<erratum_id>`` and the workaround has the format 1610 ``errata_<cpu_number>_<erratum_id>_wa`` where ``cpu_number`` is the shortform 1611 letter and number name of the CPU. 1612 1613 For CVEs the ``erratum_id`` also becomes ``cve_<year>_<number>``. 1614 1615Errata framework helpers 1616^^^^^^^^^^^^^^^^^^^^^^^^ 1617 1618Writing these errata involves lots of boilerplate and repetitive code. On 1619AArch64 there are helpers to omit most of this. They are located in 1620``include/lib/cpus/aarch64/cpu_macros.S`` and the preferred way to implement 1621errata. Please see their comments on how to use them. 1622 1623The most common type of erratum workaround, one that just sets a "chicken" bit 1624in some arbitrary register, would have an implementation for the Cortex-A77, 1625erratum #1925769 like:: 1626 1627 workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769 1628 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8 1629 workaround_reset_end cortex_a77, ERRATUM(1925769) 1630 1631 check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1) 1632 1633Status reporting 1634^^^^^^^^^^^^^^^^ 1635 1636In a debug build of TF-A, on a CPU that comes out of reset, both BL1 and the 1637runtime firmware (BL31 in AArch64, and BL32 in AArch32) will invoke a generic 1638errata status reporting function. It will read the ``errata_entries`` list of 1639that cpu and will report whether each known erratum was applied and, if not, 1640whether it should have been. 1641 1642Reporting the status of errata workaround is for informational purpose only; it 1643has no functional significance. 1644 1645Memory layout of BL images 1646-------------------------- 1647 1648Each bootloader image can be divided in 2 parts: 1649 1650- the static contents of the image. These are data actually stored in the 1651 binary on the disk. In the ELF terminology, they are called ``PROGBITS`` 1652 sections; 1653 1654- the run-time contents of the image. These are data that don't occupy any 1655 space in the binary on the disk. The ELF binary just contains some 1656 metadata indicating where these data will be stored at run-time and the 1657 corresponding sections need to be allocated and initialized at run-time. 1658 In the ELF terminology, they are called ``NOBITS`` sections. 1659 1660All PROGBITS sections are grouped together at the beginning of the image, 1661followed by all NOBITS sections. This is true for all TF-A images and it is 1662governed by the linker scripts. This ensures that the raw binary images are 1663as small as possible. If a NOBITS section was inserted in between PROGBITS 1664sections then the resulting binary file would contain zero bytes in place of 1665this NOBITS section, making the image unnecessarily bigger. Smaller images 1666allow faster loading from the FIP to the main memory. 1667 1668For BL31, a platform can specify an alternate location for NOBITS sections 1669(other than immediately following PROGBITS sections) by setting 1670``SEPARATE_NOBITS_REGION`` to 1 and defining ``BL31_NOBITS_BASE`` and 1671``BL31_NOBITS_LIMIT``. 1672 1673Linker scripts and symbols 1674~~~~~~~~~~~~~~~~~~~~~~~~~~ 1675 1676Each bootloader stage image layout is described by its own linker script. The 1677linker scripts export some symbols into the program symbol table. Their values 1678correspond to particular addresses. TF-A code can refer to these symbols to 1679figure out the image memory layout. 1680 1681Linker symbols follow the following naming convention in TF-A. 1682 1683- ``__<SECTION>_START__`` 1684 1685 Start address of a given section named ``<SECTION>``. 1686 1687- ``__<SECTION>_END__`` 1688 1689 End address of a given section named ``<SECTION>``. If there is an alignment 1690 constraint on the section's end address then ``__<SECTION>_END__`` corresponds 1691 to the end address of the section's actual contents, rounded up to the right 1692 boundary. Refer to the value of ``__<SECTION>_UNALIGNED_END__`` to know the 1693 actual end address of the section's contents. 1694 1695- ``__<SECTION>_UNALIGNED_END__`` 1696 1697 End address of a given section named ``<SECTION>`` without any padding or 1698 rounding up due to some alignment constraint. 1699 1700- ``__<SECTION>_SIZE__`` 1701 1702 Size (in bytes) of a given section named ``<SECTION>``. If there is an 1703 alignment constraint on the section's end address then ``__<SECTION>_SIZE__`` 1704 corresponds to the size of the section's actual contents, rounded up to the 1705 right boundary. In other words, ``__<SECTION>_SIZE__ = __<SECTION>_END__ - _<SECTION>_START__``. Refer to the value of ``__<SECTION>_UNALIGNED_SIZE__`` 1706 to know the actual size of the section's contents. 1707 1708- ``__<SECTION>_UNALIGNED_SIZE__`` 1709 1710 Size (in bytes) of a given section named ``<SECTION>`` without any padding or 1711 rounding up due to some alignment constraint. In other words, 1712 ``__<SECTION>_UNALIGNED_SIZE__ = __<SECTION>_UNALIGNED_END__ - __<SECTION>_START__``. 1713 1714Some of the linker symbols are mandatory as TF-A code relies on them to be 1715defined. They are listed in the following subsections. Some of them must be 1716provided for each bootloader stage and some are specific to a given bootloader 1717stage. 1718 1719The linker scripts define some extra, optional symbols. They are not actually 1720used by any code but they help in understanding the bootloader images' memory 1721layout as they are easy to spot in the link map files. 1722 1723Common linker symbols 1724^^^^^^^^^^^^^^^^^^^^^ 1725 1726All BL images share the following requirements: 1727 1728- The BSS section must be zero-initialised before executing any C code. 1729- The coherent memory section (if enabled) must be zero-initialised as well. 1730- The MMU setup code needs to know the extents of the coherent and read-only 1731 memory regions to set the right memory attributes. When 1732 ``SEPARATE_CODE_AND_RODATA=1``, it needs to know more specifically how the 1733 read-only memory region is divided between code and data. 1734 1735The following linker symbols are defined for this purpose: 1736 1737- ``__BSS_START__`` 1738- ``__BSS_SIZE__`` 1739- ``__COHERENT_RAM_START__`` Must be aligned on a page-size boundary. 1740- ``__COHERENT_RAM_END__`` Must be aligned on a page-size boundary. 1741- ``__COHERENT_RAM_UNALIGNED_SIZE__`` 1742- ``__RO_START__`` 1743- ``__RO_END__`` 1744- ``__TEXT_START__`` 1745- ``__TEXT_END_UNALIGNED__`` 1746- ``__TEXT_END__`` 1747- ``__RODATA_START__`` 1748- ``__RODATA_END_UNALIGNED__`` 1749- ``__RODATA_END__`` 1750 1751BL1's linker symbols 1752^^^^^^^^^^^^^^^^^^^^ 1753 1754BL1 being the ROM image, it has additional requirements. BL1 resides in ROM and 1755it is entirely executed in place but it needs some read-write memory for its 1756mutable data. Its ``.data`` section (i.e. its allocated read-write data) must be 1757relocated from ROM to RAM before executing any C code. 1758 1759The following additional linker symbols are defined for BL1: 1760 1761- ``__BL1_ROM_END__`` End address of BL1's ROM contents, covering its code 1762 and ``.data`` section in ROM. 1763- ``__DATA_ROM_START__`` Start address of the ``.data`` section in ROM. Must be 1764 aligned on a 16-byte boundary. 1765- ``__DATA_RAM_START__`` Address in RAM where the ``.data`` section should be 1766 copied over. Must be aligned on a 16-byte boundary. 1767- ``__DATA_SIZE__`` Size of the ``.data`` section (in ROM or RAM). 1768- ``__BL1_RAM_START__`` Start address of BL1 read-write data. 1769- ``__BL1_RAM_END__`` End address of BL1 read-write data. 1770 1771How to choose the right base addresses for each bootloader stage image 1772~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1773 1774There is currently no support for dynamic image loading in TF-A. This means 1775that all bootloader images need to be linked against their ultimate runtime 1776locations and the base addresses of each image must be chosen carefully such 1777that images don't overlap each other in an undesired way. As the code grows, 1778the base addresses might need adjustments to cope with the new memory layout. 1779 1780The memory layout is completely specific to the platform and so there is no 1781general recipe for choosing the right base addresses for each bootloader image. 1782However, there are tools to aid in understanding the memory layout. These are 1783the link map files: ``build/<platform>/<build-type>/bl<x>/bl<x>.map``, with ``<x>`` 1784being the stage bootloader. They provide a detailed view of the memory usage of 1785each image. Among other useful information, they provide the end address of 1786each image. 1787 1788- ``bl1.map`` link map file provides ``__BL1_RAM_END__`` address. 1789- ``bl2.map`` link map file provides ``__BL2_END__`` address. 1790- ``bl31.map`` link map file provides ``__BL31_END__`` address. 1791- ``bl32.map`` link map file provides ``__BL32_END__`` address. 1792 1793For each bootloader image, the platform code must provide its start address 1794as well as a limit address that it must not overstep. The latter is used in the 1795linker scripts to check that the image doesn't grow past that address. If that 1796happens, the linker will issue a message similar to the following: 1797 1798:: 1799 1800 aarch64-none-elf-ld: BLx has exceeded its limit. 1801 1802Additionally, if the platform memory layout implies some image overlaying like 1803on FVP, BL31 and TSP need to know the limit address that their PROGBITS 1804sections must not overstep. The platform code must provide those. 1805 1806TF-A does not provide any mechanism to verify at boot time that the memory 1807to load a new image is free to prevent overwriting a previously loaded image. 1808The platform must specify the memory available in the system for all the 1809relevant BL images to be loaded. 1810 1811For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will 1812return the region defined by the platform where BL1 intends to load BL2. The 1813``load_image()`` function performs bounds check for the image size based on the 1814base and maximum image size provided by the platforms. Platforms must take 1815this behaviour into account when defining the base/size for each of the images. 1816 1817Memory layout on Arm development platforms 1818^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1819 1820The following list describes the memory layout on the Arm development platforms: 1821 1822- A 4KB page of shared memory is used for communication between Trusted 1823 Firmware and the platform's power controller. This is located at the base of 1824 Trusted SRAM. The amount of Trusted SRAM available to load the bootloader 1825 images is reduced by the size of the shared memory. 1826 1827 The shared memory is used to store the CPUs' entrypoint mailbox. On Juno, 1828 this is also used for the MHU payload when passing messages to and from the 1829 SCP. 1830 1831- Another 4 KB page is reserved for passing memory layout between BL1 and BL2 1832 and also the dynamic firmware configurations. 1833 1834- On FVP, BL1 is originally sitting in the Trusted ROM at address ``0x0``. On 1835 Juno, BL1 resides in flash memory at address ``0x0BEC0000``. BL1 read-write 1836 data are relocated to the top of Trusted SRAM at runtime. 1837 1838- BL2 is loaded below BL1 RW 1839 1840- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP_MIN), 1841 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will 1842 overwrite BL1 R/W data and BL2. This implies that BL1 global variables 1843 remain valid only until execution reaches the EL3 Runtime Software entry 1844 point during a cold boot. 1845 1846- On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory 1847 region and transferred to the SCP before being overwritten by EL3 Runtime 1848 Software. 1849 1850- BL32 (for AArch64) can be loaded in one of the following locations: 1851 1852 - Trusted SRAM 1853 - Trusted DRAM (FVP only) 1854 - Secure region of DRAM (top 16MB of DRAM configured by the TrustZone 1855 controller) 1856 1857 When BL32 (for AArch64) is loaded into Trusted SRAM, it is loaded below 1858 BL31. 1859 1860The location of the BL32 image will result in different memory maps. This is 1861illustrated for both FVP and Juno in the following diagrams, using the TSP as 1862an example. 1863 1864.. note:: 1865 Loading the BL32 image in TZC secured DRAM doesn't change the memory 1866 layout of the other images in Trusted SRAM. 1867 1868CONFIG section in memory layouts shown below contains: 1869 1870:: 1871 1872 +--------------------+ 1873 |bl2_mem_params_descs| 1874 |--------------------| 1875 | fw_configs | 1876 +--------------------+ 1877 1878``bl2_mem_params_descs`` contains parameters passed from BL2 to next the 1879BL image during boot. 1880 1881``fw_configs`` includes soc_fw_config, tos_fw_config, tb_fw_config and fw_config. 1882 1883**FVP with TSP in Trusted SRAM with firmware configs :** 1884(These diagrams only cover the AArch64 case) 1885 1886:: 1887 1888 DRAM 1889 0xffffffff +----------+ 1890 | EL3 TZC | 1891 0xffe00000 |----------| (secure) 1892 | AP TZC | 1893 0xff000000 +----------+ 1894 : : 1895 0x82100000 |----------| 1896 |HW_CONFIG | 1897 0x82000000 |----------| (non-secure) 1898 | | 1899 0x80000000 +----------+ 1900 1901 Trusted DRAM 1902 0x08000000 +----------+ 1903 |HW_CONFIG | 1904 0x07f00000 |----------| 1905 : : 1906 | | 1907 0x06000000 +----------+ 1908 1909 Trusted SRAM 1910 0x04040000 +----------+ loaded by BL2 +----------------+ 1911 | BL1 (rw) | <<<<<<<<<<<<< | | 1912 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1913 | BL2 | <<<<<<<<<<<<< | | 1914 |----------| <<<<<<<<<<<<< |----------------| 1915 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1916 | | <<<<<<<<<<<<< |----------------| 1917 | | <<<<<<<<<<<<< | BL32 | 1918 0x04003000 +----------+ +----------------+ 1919 | CONFIG | 1920 0x04001000 +----------+ 1921 | Shared | 1922 0x04000000 +----------+ 1923 1924 Trusted ROM 1925 0x04000000 +----------+ 1926 | BL1 (ro) | 1927 0x00000000 +----------+ 1928 1929**FVP with TSP in Trusted DRAM with firmware configs (default option):** 1930 1931:: 1932 1933 DRAM 1934 0xffffffff +--------------+ 1935 | EL3 TZC | 1936 0xffe00000 |--------------| (secure) 1937 | AP TZC | 1938 0xff000000 +--------------+ 1939 : : 1940 0x82100000 |--------------| 1941 | HW_CONFIG | 1942 0x82000000 |--------------| (non-secure) 1943 | | 1944 0x80000000 +--------------+ 1945 1946 Trusted DRAM 1947 0x08000000 +--------------+ 1948 | HW_CONFIG | 1949 0x07f00000 |--------------| 1950 : : 1951 | BL32 | 1952 0x06000000 +--------------+ 1953 1954 Trusted SRAM 1955 0x04040000 +--------------+ loaded by BL2 +----------------+ 1956 | BL1 (rw) | <<<<<<<<<<<<< | | 1957 |--------------| <<<<<<<<<<<<< | BL31 NOBITS | 1958 | BL2 | <<<<<<<<<<<<< | | 1959 |--------------| <<<<<<<<<<<<< |----------------| 1960 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1961 | | +----------------+ 1962 0x04003000 +--------------+ 1963 | CONFIG | 1964 0x04001000 +--------------+ 1965 | Shared | 1966 0x04000000 +--------------+ 1967 1968 Trusted ROM 1969 0x04000000 +--------------+ 1970 | BL1 (ro) | 1971 0x00000000 +--------------+ 1972 1973**FVP with TSP in TZC-Secured DRAM with firmware configs :** 1974 1975:: 1976 1977 DRAM 1978 0xffffffff +----------+ 1979 | EL3 TZC | 1980 0xffe00000 |----------| (secure) 1981 | AP TZC | 1982 | (BL32) | 1983 0xff000000 +----------+ 1984 | | 1985 0x82100000 |----------| 1986 |HW_CONFIG | 1987 0x82000000 |----------| (non-secure) 1988 | | 1989 0x80000000 +----------+ 1990 1991 Trusted DRAM 1992 0x08000000 +----------+ 1993 |HW_CONFIG | 1994 0x7f000000 |----------| 1995 : : 1996 | | 1997 0x06000000 +----------+ 1998 1999 Trusted SRAM 2000 0x04040000 +----------+ loaded by BL2 +----------------+ 2001 | BL1 (rw) | <<<<<<<<<<<<< | | 2002 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 2003 | BL2 | <<<<<<<<<<<<< | | 2004 |----------| <<<<<<<<<<<<< |----------------| 2005 | | <<<<<<<<<<<<< | BL31 PROGBITS | 2006 | | +----------------+ 2007 0x04003000 +----------+ 2008 | CONFIG | 2009 0x04001000 +----------+ 2010 | Shared | 2011 0x04000000 +----------+ 2012 2013 Trusted ROM 2014 0x04000000 +----------+ 2015 | BL1 (ro) | 2016 0x00000000 +----------+ 2017 2018**Juno with BL32 in Trusted SRAM :** 2019 2020:: 2021 2022 DRAM 2023 0xFFFFFFFF +----------+ 2024 | SCP TZC | 2025 0xFFE00000 |----------| 2026 | EL3 TZC | 2027 0xFFC00000 |----------| (secure) 2028 | AP TZC | 2029 0xFF000000 +----------+ 2030 | | 2031 : : (non-secure) 2032 | | 2033 0x80000000 +----------+ 2034 2035 2036 Flash0 2037 0x0C000000 +----------+ 2038 : : 2039 0x0BED0000 |----------| 2040 | BL1 (ro) | 2041 0x0BEC0000 |----------| 2042 : : 2043 0x08000000 +----------+ BL31 is loaded 2044 after SCP_BL2 has 2045 Trusted SRAM been sent to SCP 2046 0x04040000 +----------+ loaded by BL2 +----------------+ 2047 | BL1 (rw) | <<<<<<<<<<<<< | | 2048 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 2049 | BL2 | <<<<<<<<<<<<< | | 2050 |----------| <<<<<<<<<<<<< |----------------| 2051 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 2052 | | <<<<<<<<<<<<< |----------------| 2053 | | <<<<<<<<<<<<< | BL32 | 2054 | | +----------------+ 2055 | | 2056 0x04001000 +----------+ 2057 | MHU | 2058 0x04000000 +----------+ 2059 2060**Juno with BL32 in TZC-secured DRAM :** 2061 2062:: 2063 2064 DRAM 2065 0xFFFFFFFF +----------+ 2066 | SCP TZC | 2067 0xFFE00000 |----------| 2068 | EL3 TZC | 2069 0xFFC00000 |----------| (secure) 2070 | AP TZC | 2071 | (BL32) | 2072 0xFF000000 +----------+ 2073 | | 2074 : : (non-secure) 2075 | | 2076 0x80000000 +----------+ 2077 2078 Flash0 2079 0x0C000000 +----------+ 2080 : : 2081 0x0BED0000 |----------| 2082 | BL1 (ro) | 2083 0x0BEC0000 |----------| 2084 : : 2085 0x08000000 +----------+ BL31 is loaded 2086 after SCP_BL2 has 2087 Trusted SRAM been sent to SCP 2088 0x04040000 +----------+ loaded by BL2 +----------------+ 2089 | BL1 (rw) | <<<<<<<<<<<<< | | 2090 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 2091 | BL2 | <<<<<<<<<<<<< | | 2092 |----------| <<<<<<<<<<<<< |----------------| 2093 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 2094 | | +----------------+ 2095 0x04001000 +----------+ 2096 | MHU | 2097 0x04000000 +----------+ 2098 2099.. _firmware_design_fip: 2100 2101Firmware Image Package (FIP) 2102---------------------------- 2103 2104Using a Firmware Image Package (FIP) allows for packing bootloader images (and 2105potentially other payloads) into a single archive that can be loaded by TF-A 2106from non-volatile platform storage. A driver to load images from a FIP has 2107been added to the storage layer and allows a package to be read from supported 2108platform storage. A tool to create Firmware Image Packages is also provided 2109and described below. 2110 2111Firmware Image Package layout 2112~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2113 2114The FIP layout consists of a table of contents (ToC) followed by payload data. 2115The ToC itself has a header followed by one or more table entries. The ToC is 2116terminated by an end marker entry, and since the size of the ToC is 0 bytes, 2117the offset equals the total size of the FIP file. All ToC entries describe some 2118payload data that has been appended to the end of the binary package. With the 2119information provided in the ToC entry the corresponding payload data can be 2120retrieved. 2121 2122:: 2123 2124 ------------------ 2125 | ToC Header | 2126 |----------------| 2127 | ToC Entry 0 | 2128 |----------------| 2129 | ToC Entry 1 | 2130 |----------------| 2131 | ToC End Marker | 2132 |----------------| 2133 | | 2134 | Data 0 | 2135 | | 2136 |----------------| 2137 | | 2138 | Data 1 | 2139 | | 2140 ------------------ 2141 2142The ToC header and entry formats are described in the header file 2143``include/tools_share/firmware_image_package.h``. This file is used by both the 2144tool and TF-A. 2145 2146The ToC header has the following fields: 2147 2148:: 2149 2150 `name`: The name of the ToC. This is currently used to validate the header. 2151 `serial_number`: A non-zero number provided by the creation tool 2152 `flags`: Flags associated with this data. 2153 Bits 0-31: Reserved 2154 Bits 32-47: Platform defined 2155 Bits 48-63: Reserved 2156 2157A ToC entry has the following fields: 2158 2159:: 2160 2161 `uuid`: All files are referred to by a pre-defined Universally Unique 2162 IDentifier [UUID] . The UUIDs are defined in 2163 `include/tools_share/firmware_image_package.h`. The platform translates 2164 the requested image name into the corresponding UUID when accessing the 2165 package. 2166 `offset_address`: The offset address at which the corresponding payload data 2167 can be found. The offset is calculated from the ToC base address. 2168 `size`: The size of the corresponding payload data in bytes. 2169 `flags`: Flags associated with this entry. None are yet defined. 2170 2171Firmware Image Package creation tool 2172~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2173 2174The FIP creation tool can be used to pack specified images into a binary 2175package that can be loaded by TF-A from platform storage. The tool currently 2176only supports packing bootloader images. Additional image definitions can be 2177added to the tool as required. 2178 2179The tool can be found in ``tools/fiptool``. 2180 2181Loading from a Firmware Image Package (FIP) 2182~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2183 2184The Firmware Image Package (FIP) driver can load images from a binary package on 2185non-volatile platform storage. For the Arm development platforms, this is 2186currently NOR FLASH. 2187 2188Bootloader images are loaded according to the platform policy as specified by 2189the function ``plat_get_image_source()``. For the Arm development platforms, this 2190means the platform will attempt to load images from a Firmware Image Package 2191located at the start of NOR FLASH0. 2192 2193The Arm development platforms' policy is to only allow loading of a known set of 2194images. The platform policy can be modified to allow additional images. 2195 2196Use of coherent memory in TF-A 2197------------------------------ 2198 2199There might be loss of coherency when physical memory with mismatched 2200shareability, cacheability and memory attributes is accessed by multiple CPUs 2201(refer to section B2.9 of `Arm ARM`_ for more details). This possibility occurs 2202in TF-A during power up/down sequences when coherency, MMU and caches are 2203turned on/off incrementally. 2204 2205TF-A defines coherent memory as a region of memory with Device nGnRE attributes 2206in the translation tables. The translation granule size in TF-A is 4KB. This 2207is the smallest possible size of the coherent memory region. 2208 2209By default, all data structures which are susceptible to accesses with 2210mismatched attributes from various CPUs are allocated in a coherent memory 2211region (refer to section 2.1 of :ref:`Porting Guide`). The coherent memory 2212region accesses are Outer Shareable, non-cacheable and they can be accessed with 2213the Device nGnRE attributes when the MMU is turned on. Hence, at the expense of 2214at least an extra page of memory, TF-A is able to work around coherency issues 2215due to mismatched memory attributes. 2216 2217The alternative to the above approach is to allocate the susceptible data 2218structures in Normal WriteBack WriteAllocate Inner shareable memory. This 2219approach requires the data structures to be designed so that it is possible to 2220work around the issue of mismatched memory attributes by performing software 2221cache maintenance on them. 2222 2223Disabling the use of coherent memory in TF-A 2224~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2225 2226It might be desirable to avoid the cost of allocating coherent memory on 2227platforms which are memory constrained. TF-A enables inclusion of coherent 2228memory in firmware images through the build flag ``USE_COHERENT_MEM``. 2229This flag is enabled by default. It can be disabled to choose the second 2230approach described above. 2231 2232The below sections analyze the data structures allocated in the coherent memory 2233region and the changes required to allocate them in normal memory. 2234 2235Coherent memory usage in PSCI implementation 2236~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2237 2238The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain 2239tree information for state management of power domains. By default, this data 2240structure is allocated in the coherent memory region in TF-A because it can be 2241accessed by multiple CPUs, either with caches enabled or disabled. 2242 2243.. code:: c 2244 2245 typedef struct non_cpu_pwr_domain_node { 2246 /* 2247 * Index of the first CPU power domain node level 0 which has this node 2248 * as its parent. 2249 */ 2250 unsigned int cpu_start_idx; 2251 2252 /* 2253 * Number of CPU power domains which are siblings of the domain indexed 2254 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx 2255 * -> cpu_start_idx + ncpus' have this node as their parent. 2256 */ 2257 unsigned int ncpus; 2258 2259 /* 2260 * Index of the parent power domain node. 2261 */ 2262 unsigned int parent_node; 2263 2264 plat_local_state_t local_state; 2265 2266 unsigned char level; 2267 2268 /* For indexing the psci_lock array*/ 2269 unsigned char lock_index; 2270 } non_cpu_pd_node_t; 2271 2272In order to move this data structure to normal memory, the use of each of its 2273fields must be analyzed. Fields like ``cpu_start_idx``, ``ncpus``, ``parent_node`` 2274``level`` and ``lock_index`` are only written once during cold boot. Hence removing 2275them from coherent memory involves only doing a clean and invalidate of the 2276cache lines after these fields are written. 2277 2278The field ``local_state`` can be concurrently accessed by multiple CPUs in 2279different cache states. A Lamport's Bakery lock ``psci_locks`` is used to ensure 2280mutual exclusion to this field and a clean and invalidate is needed after it 2281is written. 2282 2283Bakery lock data 2284~~~~~~~~~~~~~~~~ 2285 2286The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory 2287and is accessed by multiple CPUs with mismatched attributes. ``bakery_lock_t`` is 2288defined as follows: 2289 2290.. code:: c 2291 2292 typedef struct bakery_lock { 2293 /* 2294 * The lock_data is a bit-field of 2 members: 2295 * Bit[0] : choosing. This field is set when the CPU is 2296 * choosing its bakery number. 2297 * Bits[1 - 15] : number. This is the bakery number allocated. 2298 */ 2299 volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS]; 2300 } bakery_lock_t; 2301 2302It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU 2303fields can be read by all CPUs but only written to by the owning CPU. 2304 2305Depending upon the data cache line size, the per-CPU fields of the 2306``bakery_lock_t`` structure for multiple CPUs may exist on a single cache line. 2307These per-CPU fields can be read and written during lock contention by multiple 2308CPUs with mismatched memory attributes. Since these fields are a part of the 2309lock implementation, they do not have access to any other locking primitive to 2310safeguard against the resulting coherency issues. As a result, simple software 2311cache maintenance is not enough to allocate them in coherent memory. Consider 2312the following example. 2313 2314CPU0 updates its per-CPU field with data cache enabled. This write updates a 2315local cache line which contains a copy of the fields for other CPUs as well. Now 2316CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache 2317disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of 2318its field in any other cache line in the system. This operation will invalidate 2319the update made by CPU0 as well. 2320 2321To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure 2322has been redesigned. The changes utilise the characteristic of Lamport's Bakery 2323algorithm mentioned earlier. The bakery_lock structure only allocates the memory 2324for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks 2325needed for a CPU into a section ``.bakery_lock``. The linker allocates the memory 2326for other cores by using the total size allocated for the bakery_lock section 2327and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to 2328perform software cache maintenance on the lock data structure without running 2329into coherency issues associated with mismatched attributes. 2330 2331The bakery lock data structure ``bakery_info_t`` is defined for use when 2332``USE_COHERENT_MEM`` is disabled as follows: 2333 2334.. code:: c 2335 2336 typedef struct bakery_info { 2337 /* 2338 * The lock_data is a bit-field of 2 members: 2339 * Bit[0] : choosing. This field is set when the CPU is 2340 * choosing its bakery number. 2341 * Bits[1 - 15] : number. This is the bakery number allocated. 2342 */ 2343 volatile uint16_t lock_data; 2344 } bakery_info_t; 2345 2346The ``bakery_info_t`` represents a single per-CPU field of one lock and 2347the combination of corresponding ``bakery_info_t`` structures for all CPUs in the 2348system represents the complete bakery lock. The view in memory for a system 2349with n bakery locks are: 2350 2351:: 2352 2353 .bakery_lock section start 2354 |----------------| 2355 | `bakery_info_t`| <-- Lock_0 per-CPU field 2356 | Lock_0 | for CPU0 2357 |----------------| 2358 | `bakery_info_t`| <-- Lock_1 per-CPU field 2359 | Lock_1 | for CPU0 2360 |----------------| 2361 | .... | 2362 |----------------| 2363 | `bakery_info_t`| <-- Lock_N per-CPU field 2364 | Lock_N | for CPU0 2365 ------------------ 2366 | XXXXX | 2367 | Padding to | 2368 | next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate 2369 | Granule | continuous memory for remaining CPUs. 2370 ------------------ 2371 | `bakery_info_t`| <-- Lock_0 per-CPU field 2372 | Lock_0 | for CPU1 2373 |----------------| 2374 | `bakery_info_t`| <-- Lock_1 per-CPU field 2375 | Lock_1 | for CPU1 2376 |----------------| 2377 | .... | 2378 |----------------| 2379 | `bakery_info_t`| <-- Lock_N per-CPU field 2380 | Lock_N | for CPU1 2381 ------------------ 2382 | XXXXX | 2383 | Padding to | 2384 | next Cache WB | 2385 | Granule | 2386 ------------------ 2387 2388Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an 2389operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1 2390``.bakery_lock`` section need to be fetched and appropriate cache operations need 2391to be performed for each access. 2392 2393On Arm Platforms, bakery locks are used in psci (``psci_locks``) and power controller 2394driver (``arm_lock``). 2395 2396Non Functional Impact of removing coherent memory 2397~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2398 2399Removal of the coherent memory region leads to the additional software overhead 2400of performing cache maintenance for the affected data structures. However, since 2401the memory where the data structures are allocated is cacheable, the overhead is 2402mostly mitigated by an increase in performance. 2403 2404There is however a performance impact for bakery locks, due to: 2405 2406- Additional cache maintenance operations, and 2407- Multiple cache line reads for each lock operation, since the bakery locks 2408 for each CPU are distributed across different cache lines. 2409 2410The implementation has been optimized to minimize this additional overhead. 2411Measurements indicate that when bakery locks are allocated in Normal memory, the 2412minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas 2413in Device memory the same is 2 micro seconds. The measurements were done on the 2414Juno Arm development platform. 2415 2416As mentioned earlier, almost a page of memory can be saved by disabling 2417``USE_COHERENT_MEM``. Each platform needs to consider these trade-offs to decide 2418whether coherent memory should be used. If a platform disables 2419``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can 2420optionally define macro ``PLAT_PERCPU_BAKERY_LOCK_SIZE`` (see the 2421:ref:`Porting Guide`). Refer to the reference platform code for examples. 2422 2423Isolating code and read-only data on separate memory pages 2424---------------------------------------------------------- 2425 2426In the Armv8-A VMSA, translation table entries include fields that define the 2427properties of the target memory region, such as its access permissions. The 2428smallest unit of memory that can be addressed by a translation table entry is 2429a memory page. Therefore, if software needs to set different permissions on two 2430memory regions then it needs to map them using different memory pages. 2431 2432The default memory layout for each BL image is as follows: 2433 2434:: 2435 2436 | ... | 2437 +-------------------+ 2438 | Read-write data | 2439 +-------------------+ Page boundary 2440 | <Padding> | 2441 +-------------------+ 2442 | Exception vectors | 2443 +-------------------+ 2 KB boundary 2444 | <Padding> | 2445 +-------------------+ 2446 | Read-only data | 2447 +-------------------+ 2448 | Code | 2449 +-------------------+ BLx_BASE 2450 2451.. note:: 2452 The 2KB alignment for the exception vectors is an architectural 2453 requirement. 2454 2455The read-write data start on a new memory page so that they can be mapped with 2456read-write permissions, whereas the code and read-only data below are configured 2457as read-only. 2458 2459However, the read-only data are not aligned on a page boundary. They are 2460contiguous to the code. Therefore, the end of the code section and the beginning 2461of the read-only data one might share a memory page. This forces both to be 2462mapped with the same memory attributes. As the code needs to be executable, this 2463means that the read-only data stored on the same memory page as the code are 2464executable as well. This could potentially be exploited as part of a security 2465attack. 2466 2467TF provides the build flag ``SEPARATE_CODE_AND_RODATA`` to isolate the code and 2468read-only data on separate memory pages. This in turn allows independent control 2469of the access permissions for the code and read-only data. In this case, 2470platform code gets a finer-grained view of the image layout and can 2471appropriately map the code region as executable and the read-only data as 2472execute-never. 2473 2474This has an impact on memory footprint, as padding bytes need to be introduced 2475between the code and read-only data to ensure the segregation of the two. To 2476limit the memory cost, this flag also changes the memory layout such that the 2477code and exception vectors are now contiguous, like so: 2478 2479:: 2480 2481 | ... | 2482 +-------------------+ 2483 | Read-write data | 2484 +-------------------+ Page boundary 2485 | <Padding> | 2486 +-------------------+ 2487 | Read-only data | 2488 +-------------------+ Page boundary 2489 | <Padding> | 2490 +-------------------+ 2491 | Exception vectors | 2492 +-------------------+ 2 KB boundary 2493 | <Padding> | 2494 +-------------------+ 2495 | Code | 2496 +-------------------+ BLx_BASE 2497 2498With this more condensed memory layout, the separation of read-only data will 2499add zero or one page to the memory footprint of each BL image. Each platform 2500should consider the trade-off between memory footprint and security. 2501 2502This build flag is disabled by default, minimising memory footprint. On Arm 2503platforms, it is enabled. 2504 2505Publish and Subscribe Framework 2506------------------------------- 2507 2508The Publish and Subscribe Framework allows EL3 components to define and publish 2509events, to which other EL3 components can subscribe. 2510 2511The following macros are provided by the framework: 2512 2513- ``REGISTER_PUBSUB_EVENT(event)``: Defines an event, and takes one argument, 2514 the event name, which must be a valid C identifier. All calls to 2515 ``REGISTER_PUBSUB_EVENT`` macro must be placed in the file 2516 ``pubsub_events.h``. 2517 2518- ``PUBLISH_EVENT_ARG(event, arg)``: Publishes a defined event, by iterating 2519 subscribed handlers and calling them in turn. The handlers will be passed the 2520 parameter ``arg``. The expected use-case is to broadcast an event. 2521 2522- ``PUBLISH_EVENT(event)``: Like ``PUBLISH_EVENT_ARG``, except that the value 2523 ``NULL`` is passed to subscribed handlers. 2524 2525- ``SUBSCRIBE_TO_EVENT(event, handler)``: Registers the ``handler`` to 2526 subscribe to ``event``. The handler will be executed whenever the ``event`` 2527 is published. 2528 2529- ``for_each_subscriber(event, subscriber)``: Iterates through all handlers 2530 subscribed for ``event``. ``subscriber`` must be a local variable of type 2531 ``pubsub_cb_t *``, and will point to each subscribed handler in turn during 2532 iteration. This macro can be used for those patterns that none of the 2533 ``PUBLISH_EVENT_*()`` macros cover. 2534 2535Publishing an event that wasn't defined using ``REGISTER_PUBSUB_EVENT`` will 2536result in build error. Subscribing to an undefined event however won't. 2537 2538Subscribed handlers must be of type ``pubsub_cb_t``, with following function 2539signature: 2540 2541.. code:: c 2542 2543 typedef void* (*pubsub_cb_t)(const void *arg); 2544 2545There may be arbitrary number of handlers registered to the same event. The 2546order in which subscribed handlers are notified when that event is published is 2547not defined. Subscribed handlers may be executed in any order; handlers should 2548not assume any relative ordering amongst them. 2549 2550Publishing an event on a PE will result in subscribed handlers executing on that 2551PE only; it won't cause handlers to execute on a different PE. 2552 2553Note that publishing an event on a PE blocks until all the subscribed handlers 2554finish executing on the PE. 2555 2556TF-A generic code publishes and subscribes to some events within. Platform 2557ports are discouraged from subscribing to them. These events may be withdrawn, 2558renamed, or have their semantics altered in the future. Platforms may however 2559register, publish, and subscribe to platform-specific events. 2560 2561Publish and Subscribe Example 2562~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2563 2564A publisher that wants to publish event ``foo`` would: 2565 2566- Define the event ``foo`` in the ``pubsub_events.h``. 2567 2568 .. code:: c 2569 2570 REGISTER_PUBSUB_EVENT(foo); 2571 2572- Depending on the nature of event, use one of ``PUBLISH_EVENT_*()`` macros to 2573 publish the event at the appropriate path and time of execution. 2574 2575A subscriber that wants to subscribe to event ``foo`` published above would 2576implement: 2577 2578.. code:: c 2579 2580 void *foo_handler(const void *arg) 2581 { 2582 void *result; 2583 2584 /* Do handling ... */ 2585 2586 return result; 2587 } 2588 2589 SUBSCRIBE_TO_EVENT(foo, foo_handler); 2590 2591 2592Reclaiming the BL31 initialization code 2593~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2594 2595A significant amount of the code used for the initialization of BL31 is never 2596needed again after boot time. In order to reduce the runtime memory 2597footprint, the memory used for this code can be reclaimed after initialization 2598has finished and be used for runtime data. 2599 2600The build option ``RECLAIM_INIT_CODE`` can be set to mark this boot time code 2601with a ``.text.init.*`` attribute which can be filtered and placed suitably 2602within the BL image for later reclamation by the platform. The platform can 2603specify the filter and the memory region for this init section in BL31 via the 2604plat.ld.S linker script. For example, on the FVP, this section is placed 2605overlapping the secondary CPU stacks so that after the cold boot is done, this 2606memory can be reclaimed for the stacks. The init memory section is initially 2607mapped with ``RO``, ``EXECUTE`` attributes. After BL31 initialization has 2608completed, the FVP changes the attributes of this section to ``RW``, 2609``EXECUTE_NEVER`` allowing it to be used for runtime data. The memory attributes 2610are changed within the ``bl31_plat_runtime_setup`` platform hook. The init 2611section section can be reclaimed for any data which is accessed after cold 2612boot initialization and it is upto the platform to make the decision. 2613 2614Please note that this will disable inlining for any functions with the __init 2615attribute. 2616 2617.. _firmware_design_pmf: 2618 2619Performance Measurement Framework 2620--------------------------------- 2621 2622The Performance Measurement Framework (PMF) facilitates collection of 2623timestamps by registered services and provides interfaces to retrieve them 2624from within TF-A. A platform can choose to expose appropriate SMCs to 2625retrieve these collected timestamps. 2626 2627By default, the global physical counter is used for the timestamp 2628value and is read via ``CNTPCT_EL0``. The framework allows to retrieve 2629timestamps captured by other CPUs. 2630 2631Timestamp identifier format 2632~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2633 2634A PMF timestamp is uniquely identified across the system via the 2635timestamp ID or ``tid``. The ``tid`` is composed as follows: 2636 2637:: 2638 2639 Bits 0-7: The local timestamp identifier. 2640 Bits 8-9: Reserved. 2641 Bits 10-15: The service identifier. 2642 Bits 16-31: Reserved. 2643 2644#. The service identifier. Each PMF service is identified by a 2645 service name and a service identifier. Both the service name and 2646 identifier are unique within the system as a whole. 2647 2648#. The local timestamp identifier. This identifier is unique within a given 2649 service. 2650 2651Registering a PMF service 2652~~~~~~~~~~~~~~~~~~~~~~~~~ 2653 2654To register a PMF service, the ``PMF_REGISTER_SERVICE()`` macro from ``pmf.h`` 2655is used. The arguments required are the service name, the service ID, 2656the total number of local timestamps to be captured and a set of flags. 2657 2658The ``flags`` field can be specified as a bitwise-OR of the following values: 2659 2660:: 2661 2662 PMF_STORE_ENABLE: The timestamp is stored in memory for later retrieval. 2663 PMF_DUMP_ENABLE: The timestamp is dumped on the serial console. 2664 2665The ``PMF_REGISTER_SERVICE()`` reserves memory to store captured 2666timestamps in a PMF specific linker section at build time. 2667Additionally, it defines necessary functions to capture and 2668retrieve a particular timestamp for the given service at runtime. 2669 2670The macro ``PMF_REGISTER_SERVICE()`` only enables capturing PMF timestamps 2671from within TF-A. In order to retrieve timestamps from outside of TF-A, the 2672``PMF_REGISTER_SERVICE_SMC()`` macro must be used instead. This macro 2673accepts the same set of arguments as the ``PMF_REGISTER_SERVICE()`` 2674macro but additionally supports retrieving timestamps using SMCs. 2675 2676Capturing a timestamp 2677~~~~~~~~~~~~~~~~~~~~~ 2678 2679PMF timestamps are stored in a per-service timestamp region. On a 2680system with multiple CPUs, each timestamp is captured and stored 2681in a per-CPU cache line aligned memory region. 2682 2683Having registered the service, the ``PMF_CAPTURE_TIMESTAMP()`` macro can be 2684used to capture a timestamp at the location where it is used. The macro 2685takes the service name, a local timestamp identifier and a flag as arguments. 2686 2687The ``flags`` field argument can be zero, or ``PMF_CACHE_MAINT`` which 2688instructs PMF to do cache maintenance following the capture. Cache 2689maintenance is required if any of the service's timestamps are captured 2690with data cache disabled. 2691 2692To capture a timestamp in assembly code, the caller should use 2693``pmf_calc_timestamp_addr`` macro (defined in ``pmf_asm_macros.S``) to 2694calculate the address of where the timestamp would be stored. The 2695caller should then read ``CNTPCT_EL0`` register to obtain the timestamp 2696and store it at the determined address for later retrieval. 2697 2698Retrieving a timestamp 2699~~~~~~~~~~~~~~~~~~~~~~ 2700 2701From within TF-A, timestamps for individual CPUs can be retrieved using either 2702``PMF_GET_TIMESTAMP_BY_MPIDR()`` or ``PMF_GET_TIMESTAMP_BY_INDEX()`` macros. 2703These macros accept the CPU's MPIDR value, or its ordinal position 2704respectively. 2705 2706From outside TF-A, timestamps for individual CPUs can be retrieved by calling 2707into ``pmf_smc_handler()``. 2708 2709:: 2710 2711 Interface : pmf_smc_handler() 2712 Argument : unsigned int smc_fid, u_register_t x1, 2713 u_register_t x2, u_register_t x3, 2714 u_register_t x4, void *cookie, 2715 void *handle, u_register_t flags 2716 Return : uintptr_t 2717 2718 smc_fid: Holds the SMC identifier which is either `PMF_SMC_GET_TIMESTAMP_32` 2719 when the caller of the SMC is running in AArch32 mode 2720 or `PMF_SMC_GET_TIMESTAMP_64` when the caller is running in AArch64 mode. 2721 x1: Timestamp identifier. 2722 x2: The `mpidr` of the CPU for which the timestamp has to be retrieved. 2723 This can be the `mpidr` of a different core to the one initiating 2724 the SMC. In that case, service specific cache maintenance may be 2725 required to ensure the updated copy of the timestamp is returned. 2726 x3: A flags value that is either 0 or `PMF_CACHE_MAINT`. If 2727 `PMF_CACHE_MAINT` is passed, then the PMF code will perform a 2728 cache invalidate before reading the timestamp. This ensures 2729 an updated copy is returned. 2730 2731The remaining arguments, ``x4``, ``cookie``, ``handle`` and ``flags`` are unused 2732in this implementation. 2733 2734PMF code structure 2735~~~~~~~~~~~~~~~~~~ 2736 2737#. ``pmf_main.c`` consists of core functions that implement service registration, 2738 initialization, storing, dumping and retrieving timestamps. 2739 2740#. ``pmf_smc.c`` contains the SMC handling for registered PMF services. 2741 2742#. ``pmf.h`` contains the public interface to Performance Measurement Framework. 2743 2744#. ``pmf_asm_macros.S`` consists of macros to facilitate capturing timestamps in 2745 assembly code. 2746 2747#. ``pmf_helpers.h`` is an internal header used by ``pmf.h``. 2748 2749Armv8-A Architecture Extensions 2750------------------------------- 2751 2752TF-A makes use of Armv8-A Architecture Extensions where applicable. This 2753section lists the usage of Architecture Extensions, and build flags 2754controlling them. 2755 2756Build options 2757~~~~~~~~~~~~~ 2758 2759``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` 2760 2761These build options serve dual purpose 2762 2763- Determine the architecture extension support in TF-A build: All the mandatory 2764 architectural features up to ``ARM_ARCH_MAJOR.ARM_ARCH_MINOR`` are included 2765 and unconditionally enabled by TF-A build system. 2766 2767- ``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` are passed to a march.mk build utility 2768 this will try to come up with an appropriate -march value to be passed to compiler 2769 by probing the compiler and checking what's supported by the compiler and what's best 2770 that can be used. But if platform provides a ``MARCH_DIRECTIVE`` then it will used 2771 directly and compiler probing will be skipped. 2772 2773The build system requires that the platform provides a valid numeric value based on 2774CPU architecture extension, otherwise it defaults to base Armv8.0-A architecture. 2775Subsequent Arm Architecture versions also support extensions which were introduced 2776in previous versions. 2777 2778.. seealso:: :ref:`Build Options` 2779 2780For details on the Architecture Extension and available features, please refer 2781to the respective Architecture Extension Supplement. 2782 2783Armv8.1-A 2784~~~~~~~~~ 2785 2786This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when 2787``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` >= 1. 2788 2789- By default, a load-/store-exclusive instruction pair is used to implement 2790 spinlocks. The ``USE_SPINLOCK_CAS`` build option when set to 1 selects the 2791 spinlock implementation using the ARMv8.1-LSE Compare and Swap instruction. 2792 Notice this instruction is only available in AArch64 execution state, so 2793 the option is only available to AArch64 builds. 2794 2795Armv8.2-A 2796~~~~~~~~~ 2797 2798- The presence of ARMv8.2-TTCNP is detected at runtime. When it is present, the 2799 Common not Private (TTBRn_ELx.CnP) bit is enabled to indicate that multiple 2800 Processing Elements in the same Inner Shareable domain use the same 2801 translation table entries for a given stage of translation for a particular 2802 translation regime. 2803 2804Armv8.3-A 2805~~~~~~~~~ 2806 2807- Pointer authentication features of Armv8.3-A are unconditionally enabled in 2808 the Non-secure world so that lower ELs are allowed to use them without 2809 causing a trap to EL3. 2810 2811 In order to enable the Secure world to use it, ``CTX_INCLUDE_PAUTH_REGS`` 2812 must be set to 1. This will add all pointer authentication system registers 2813 to the context that is saved when doing a world switch. 2814 2815 The TF-A itself has support for pointer authentication at runtime 2816 that can be enabled by setting ``BRANCH_PROTECTION`` option to non-zero and 2817 ``CTX_INCLUDE_PAUTH_REGS`` to 1. This enables pointer authentication in BL1, 2818 BL2, BL31, and the TSP if it is used. 2819 2820 Note that Pointer Authentication is enabled for Non-secure world irrespective 2821 of the value of these build flags if the CPU supports it. 2822 2823 If ``ARM_ARCH_MAJOR == 8`` and ``ARM_ARCH_MINOR >= 3`` the code footprint of 2824 enabling PAuth is lower because the compiler will use the optimized 2825 PAuth instructions rather than the backwards-compatible ones. 2826 2827Armv8.5-A 2828~~~~~~~~~ 2829 2830- Branch Target Identification feature is selected by ``BRANCH_PROTECTION`` 2831 option set to 1. This option defaults to 0. 2832 2833- Memory Tagging Extension feature has few variants but not all of them require 2834 enablement from EL3 to be used at lower EL. e.g. Memory tagging only at 2835 EL0(MTE) does not require EL3 configuration however memory tagging at 2836 EL2/EL1 (MTE2) does require EL3 enablement and we need to set this option 2837 ``ENABLE_FEAT_MTE2`` to 1. This option defaults to 0. 2838 2839Armv7-A 2840~~~~~~~ 2841 2842This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 7. 2843 2844There are several Armv7-A extensions available. Obviously the TrustZone 2845extension is mandatory to support the TF-A bootloader and runtime services. 2846 2847Platform implementing an Armv7-A system can to define from its target 2848Cortex-A architecture through ``ARM_CORTEX_A<X> = yes`` in their 2849``platform.mk`` script. For example ``ARM_CORTEX_A15=yes`` for a 2850Cortex-A15 target. 2851 2852Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support. 2853Note that using neon at runtime has constraints on non secure world context. 2854TF-A does not yet provide VFP context management. 2855 2856Directive ``ARM_CORTEX_A<x>`` and ``ARM_WITH_NEON`` are used to set 2857the toolchain target architecture directive. 2858 2859Platform may choose to not define straight the toolchain target architecture 2860directive by defining ``MARCH_DIRECTIVE``. 2861I.e: 2862 2863.. code:: make 2864 2865 MARCH_DIRECTIVE := -march=armv7-a 2866 2867Code Structure 2868-------------- 2869 2870TF-A code is logically divided between the three boot loader stages mentioned 2871in the previous sections. The code is also divided into the following 2872categories (present as directories in the source code): 2873 2874- **Platform specific.** Choice of architecture specific code depends upon 2875 the platform. 2876- **Common code.** This is platform and architecture agnostic code. 2877- **Library code.** This code comprises of functionality commonly used by all 2878 other code. The PSCI implementation and other EL3 runtime frameworks reside 2879 as Library components. 2880- **Stage specific.** Code specific to a boot stage. 2881- **Drivers.** 2882- **Services.** EL3 runtime services (eg: SPD). Specific SPD services 2883 reside in the ``services/spd`` directory (e.g. ``services/spd/tspd``). 2884 2885Each boot loader stage uses code from one or more of the above mentioned 2886categories. Based upon the above, the code layout looks like this: 2887 2888:: 2889 2890 Directory Used by BL1? Used by BL2? Used by BL31? 2891 bl1 Yes No No 2892 bl2 No Yes No 2893 bl31 No No Yes 2894 plat Yes Yes Yes 2895 drivers Yes No Yes 2896 common Yes Yes Yes 2897 lib Yes Yes Yes 2898 services No No Yes 2899 2900The build system provides a non configurable build option IMAGE_BLx for each 2901boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE_BL1 will be 2902defined by the build system. This enables TF-A to compile certain code only 2903for specific boot loader stages 2904 2905All assembler files have the ``.S`` extension. The linker source files for each 2906boot stage have the extension ``.ld.S``. These are processed by GCC to create the 2907linker scripts which have the extension ``.ld``. 2908 2909FDTs provide a description of the hardware platform and are used by the Linux 2910kernel at boot time. These can be found in the ``fdts`` directory. 2911 2912.. rubric:: References 2913 2914- `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D)`_ 2915 2916- `PSCI`_ 2917 2918- `SMC Calling Convention`_ 2919 2920- :ref:`Interrupt Management Framework` 2921 2922-------------- 2923 2924*Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.* 2925 2926.. _SMCCC: https://developer.arm.com/docs/den0028/latest 2927.. _PSCI: https://developer.arm.com/documentation/den0022/latest/ 2928.. _Arm ARM: https://developer.arm.com/docs/ddi0487/latest 2929.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest 2930.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D): https://developer.arm.com/docs/den0006/latest 2931.. _Arm Confidential Compute Architecture (Arm CCA): https://www.arm.com/why-arm/architecture/security-features/arm-confidential-compute-architecture 2932.. _AArch64 exception vector table: https://developer.arm.com/documentation/100933/0100/AArch64-exception-vector-table 2933 2934.. |Image 1| image:: ../resources/diagrams/rt-svc-descs-layout.png 2935
