1Firmware Design 2=============== 3 4Trusted Firmware-A (TF-A) implements a subset of the Trusted Board Boot 5Requirements (TBBR) Platform Design Document (PDD) for Arm reference 6platforms. 7 8The TBB sequence starts when the platform is powered on and runs up 9to the stage where it hands-off control to firmware running in the normal 10world in DRAM. This is the cold boot path. 11 12TF-A also implements the `PSCI`_ as a runtime service. PSCI is the interface 13from normal world software to firmware implementing power management use-cases 14(for example, secondary CPU boot, hotplug and idle). Normal world software can 15access TF-A runtime services via the Arm SMC (Secure Monitor Call) instruction. 16The SMC instruction must be used as mandated by the SMC Calling Convention 17(`SMCCC`_). 18 19TF-A implements a framework for configuring and managing interrupts generated 20in either security state. The details of the interrupt management framework 21and its design can be found in :ref:`Interrupt Management Framework`. 22 23TF-A also implements a library for setting up and managing the translation 24tables. The details of this library can be found in 25:ref:`Translation (XLAT) Tables Library`. 26 27TF-A can be built to support either AArch64 or AArch32 execution state. 28 29.. note:: 30 The descriptions in this chapter are for the Arm TrustZone architecture. 31 For changes to the firmware design for the `Arm Confidential Compute 32 Architecture (Arm CCA)`_ please refer to the chapter :ref:`Realm Management 33 Extension (RME)`. 34 35Cold boot 36--------- 37 38The cold boot path starts when the platform is physically turned on. If 39``COLD_BOOT_SINGLE_CPU=0``, one of the CPUs released from reset is chosen as the 40primary CPU, and the remaining CPUs are considered secondary CPUs. The primary 41CPU is chosen through platform-specific means. The cold boot path is mainly 42executed by the primary CPU, other than essential CPU initialization executed by 43all CPUs. The secondary CPUs are kept in a safe platform-specific state until 44the primary CPU has performed enough initialization to boot them. 45 46Refer to the :ref:`CPU Reset` for more information on the effect of the 47``COLD_BOOT_SINGLE_CPU`` platform build option. 48 49The cold boot path in this implementation of TF-A depends on the execution 50state. For AArch64, it is divided into five steps (in order of execution): 51 52- Boot Loader stage 1 (BL1) *AP Trusted ROM* 53- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 54- Boot Loader stage 3-1 (BL31) *EL3 Runtime Software* 55- Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional) 56- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 57 58For AArch32, it is divided into four steps (in order of execution): 59 60- Boot Loader stage 1 (BL1) *AP Trusted ROM* 61- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 62- Boot Loader stage 3-2 (BL32) *EL3 Runtime Software* 63- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 64 65Arm development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a 66combination of the following types of memory regions. Each bootloader stage uses 67one or more of these memory regions. 68 69- Regions accessible from both non-secure and secure states. For example, 70 non-trusted SRAM, ROM and DRAM. 71- Regions accessible from only the secure state. For example, trusted SRAM and 72 ROM. The FVPs also implement the trusted DRAM which is statically 73 configured. Additionally, the Base FVPs and Juno development platform 74 configure the TrustZone Controller (TZC) to create a region in the DRAM 75 which is accessible only from the secure state. 76 77The sections below provide the following details: 78 79- dynamic configuration of Boot Loader stages 80- initialization and execution of the first three stages during cold boot 81- specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for 82 AArch32) entrypoint requirements for use by alternative Trusted Boot 83 Firmware in place of the provided BL1 and BL2 84 85Dynamic Configuration during cold boot 86~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 87 88Each of the Boot Loader stages may be dynamically configured if required by the 89platform. The Boot Loader stage may optionally specify a firmware 90configuration file and/or hardware configuration file as listed below: 91 92- FW_CONFIG - The firmware configuration file. Holds properties shared across 93 all BLx images. 94 An example is the "dtb-registry" node, which contains the information about 95 the other device tree configurations (load-address, size, image_id). 96- HW_CONFIG - The hardware configuration file. Can be shared by all Boot Loader 97 stages and also by the Normal World Rich OS. 98- TB_FW_CONFIG - Trusted Boot Firmware configuration file. Shared between BL1 99 and BL2. 100- SOC_FW_CONFIG - SoC Firmware configuration file. Used by BL31. 101- TOS_FW_CONFIG - Trusted OS Firmware configuration file. Used by Trusted OS 102 (BL32). 103- NT_FW_CONFIG - Non Trusted Firmware configuration file. Used by Non-trusted 104 firmware (BL33). 105 106The Arm development platforms use the Flattened Device Tree format for the 107dynamic configuration files. 108 109Each Boot Loader stage can pass up to 4 arguments via registers to the next 110stage. BL2 passes the list of the next images to execute to the *EL3 Runtime 111Software* (BL31 for AArch64 and BL32 for AArch32) via `arg0`. All the other 112arguments are platform defined. The Arm development platforms use the following 113convention: 114 115- BL1 passes the address of a meminfo_t structure to BL2 via ``arg1``. This 116 structure contains the memory layout available to BL2. 117- When dynamic configuration files are present, the firmware configuration for 118 the next Boot Loader stage is populated in the first available argument and 119 the generic hardware configuration is passed the next available argument. 120 For example, 121 122 - FW_CONFIG is loaded by BL1, then its address is passed in ``arg0`` to BL2. 123 - TB_FW_CONFIG address is retrieved by BL2 from FW_CONFIG device tree. 124 - If HW_CONFIG is loaded by BL1, then its address is passed in ``arg2`` to 125 BL2. Note, ``arg1`` is already used for meminfo_t. 126 - If SOC_FW_CONFIG is loaded by BL2, then its address is passed in ``arg1`` 127 to BL31. Note, ``arg0`` is used to pass the list of executable images. 128 - Similarly, if HW_CONFIG is loaded by BL1 or BL2, then its address is 129 passed in ``arg2`` to BL31. 130 - For other BL3x images, if the firmware configuration file is loaded by 131 BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded 132 then its address is passed in ``arg1``. 133 - In case of the Arm FVP platform, FW_CONFIG address passed in ``arg1`` to 134 BL31/SP_MIN, and the SOC_FW_CONFIG and HW_CONFIG details are retrieved 135 from FW_CONFIG device tree. 136 137BL1 138~~~ 139 140This stage begins execution from the platform's reset vector at EL3. The reset 141address is platform dependent but it is usually located in a Trusted ROM area. 142The BL1 data section is copied to trusted SRAM at runtime. 143 144On the Arm development platforms, BL1 code starts execution from the reset 145vector defined by the constant ``BL1_RO_BASE``. The BL1 data section is copied 146to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``. 147 148The functionality implemented by this stage is as follows. 149 150Determination of boot path 151^^^^^^^^^^^^^^^^^^^^^^^^^^ 152 153Whenever a CPU is released from reset, BL1 needs to distinguish between a warm 154boot and a cold boot. This is done using platform-specific mechanisms (see the 155``plat_get_my_entrypoint()`` function in the :ref:`Porting Guide`). In the case 156of a warm boot, a CPU is expected to continue execution from a separate 157entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe 158platform-specific state (see the ``plat_secondary_cold_boot_setup()`` function in 159the :ref:`Porting Guide`) while the primary CPU executes the remaining cold boot 160path as described in the following sections. 161 162This step only applies when ``PROGRAMMABLE_RESET_ADDRESS=0``. Refer to the 163:ref:`CPU Reset` for more information on the effect of the 164``PROGRAMMABLE_RESET_ADDRESS`` platform build option. 165 166Architectural initialization 167^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 168 169BL1 performs minimal architectural initialization as follows. 170 171- Exception vectors 172 173 BL1 sets up simple exception vectors for both synchronous and asynchronous 174 exceptions. The default behavior upon receiving an exception is to populate 175 a status code in the general purpose register ``X0/R0`` and call the 176 ``plat_report_exception()`` function (see the :ref:`Porting Guide`). The 177 status code is one of: 178 179 For AArch64: 180 181 :: 182 183 0x0 : Synchronous exception from Current EL with SP_EL0 184 0x1 : IRQ exception from Current EL with SP_EL0 185 0x2 : FIQ exception from Current EL with SP_EL0 186 0x3 : System Error exception from Current EL with SP_EL0 187 0x4 : Synchronous exception from Current EL with SP_ELx 188 0x5 : IRQ exception from Current EL with SP_ELx 189 0x6 : FIQ exception from Current EL with SP_ELx 190 0x7 : System Error exception from Current EL with SP_ELx 191 0x8 : Synchronous exception from Lower EL using aarch64 192 0x9 : IRQ exception from Lower EL using aarch64 193 0xa : FIQ exception from Lower EL using aarch64 194 0xb : System Error exception from Lower EL using aarch64 195 0xc : Synchronous exception from Lower EL using aarch32 196 0xd : IRQ exception from Lower EL using aarch32 197 0xe : FIQ exception from Lower EL using aarch32 198 0xf : System Error exception from Lower EL using aarch32 199 200 For AArch32: 201 202 :: 203 204 0x10 : User mode 205 0x11 : FIQ mode 206 0x12 : IRQ mode 207 0x13 : SVC mode 208 0x16 : Monitor mode 209 0x17 : Abort mode 210 0x1a : Hypervisor mode 211 0x1b : Undefined mode 212 0x1f : System mode 213 214 The ``plat_report_exception()`` implementation on the Arm FVP port programs 215 the Versatile Express System LED register in the following format to 216 indicate the occurrence of an unexpected exception: 217 218 :: 219 220 SYS_LED[0] - Security state (Secure=0/Non-Secure=1) 221 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0) 222 For AArch32 it is always 0x0 223 SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value 224 of the status code 225 226 A write to the LED register reflects in the System LEDs (S6LED0..7) in the 227 CLCD window of the FVP. 228 229 BL1 does not expect to receive any exceptions other than the SMC exception. 230 For the latter, BL1 installs a simple stub. The stub expects to receive a 231 limited set of SMC types (determined by their function IDs in the general 232 purpose register ``X0/R0``): 233 234 - ``BL1_SMC_RUN_IMAGE``: This SMC is raised by BL2 to make BL1 pass control 235 to EL3 Runtime Software. 236 - All SMCs listed in section "BL1 SMC Interface" in the :ref:`Firmware Update (FWU)` 237 Design Guide are supported for AArch64 only. These SMCs are currently 238 not supported when BL1 is built for AArch32. 239 240 Any other SMC leads to an assertion failure. 241 242- CPU initialization 243 244 BL1 calls the ``reset_handler()`` function which in turn calls the CPU 245 specific reset handler function (see the section: "CPU specific operations 246 framework"). 247 248Platform initialization 249^^^^^^^^^^^^^^^^^^^^^^^ 250 251On Arm platforms, BL1 performs the following platform initializations: 252 253- Enable the Trusted Watchdog. 254- Initialize the console. 255- Configure the Interconnect to enable hardware coherency. 256- Enable the MMU and map the memory it needs to access. 257- Configure any required platform storage to load the next bootloader image 258 (BL2). 259- If the BL1 dynamic configuration file, ``TB_FW_CONFIG``, is available, then 260 load it to the platform defined address and make it available to BL2 via 261 ``arg0``. 262- Configure the system timer and program the `CNTFRQ_EL0` for use by NS-BL1U 263 and NS-BL2U firmware update images. 264 265Firmware Update detection and execution 266^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 267 268After performing platform setup, BL1 common code calls 269``bl1_plat_get_next_image_id()`` to determine if :ref:`Firmware Update (FWU)` is 270required or to proceed with the normal boot process. If the platform code 271returns ``BL2_IMAGE_ID`` then the normal boot sequence is executed as described 272in the next section, else BL1 assumes that :ref:`Firmware Update (FWU)` is 273required and execution passes to the first image in the 274:ref:`Firmware Update (FWU)` process. In either case, BL1 retrieves a descriptor 275of the next image by calling ``bl1_plat_get_image_desc()``. The image descriptor 276contains an ``entry_point_info_t`` structure, which BL1 uses to initialize the 277execution state of the next image. 278 279BL2 image load and execution 280^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 281 282In the normal boot flow, BL1 execution continues as follows: 283 284#. BL1 prints the following string from the primary CPU to indicate successful 285 execution of the BL1 stage: 286 287 :: 288 289 "Booting Trusted Firmware" 290 291#. BL1 loads a BL2 raw binary image from platform storage, at a 292 platform-specific base address. Prior to the load, BL1 invokes 293 ``bl1_plat_handle_pre_image_load()`` which allows the platform to update or 294 use the image information. If the BL2 image file is not present or if 295 there is not enough free trusted SRAM the following error message is 296 printed: 297 298 :: 299 300 "Failed to load BL2 firmware." 301 302#. BL1 invokes ``bl1_plat_handle_post_image_load()`` which again is intended 303 for platforms to take further action after image load. This function must 304 populate the necessary arguments for BL2, which may also include the memory 305 layout. Further description of the memory layout can be found later 306 in this document. 307 308#. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at 309 Secure SVC mode (for AArch32), starting from its load address. 310 311BL2 312~~~ 313 314BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure 315SVC mode (for AArch32) . BL2 is linked against and loaded at a platform-specific 316base address (more information can be found later in this document). 317The functionality implemented by BL2 is as follows. 318 319Architectural initialization 320^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 321 322For AArch64, BL2 performs the minimal architectural initialization required 323for subsequent stages of TF-A and normal world software. EL1 and EL0 are given 324access to Floating Point and Advanced SIMD registers by setting the 325``CPACR.FPEN`` bits. 326 327For AArch32, the minimal architectural initialization required for subsequent 328stages of TF-A and normal world software is taken care of in BL1 as both BL1 329and BL2 execute at PL1. 330 331Platform initialization 332^^^^^^^^^^^^^^^^^^^^^^^ 333 334On Arm platforms, BL2 performs the following platform initializations: 335 336- Initialize the console. 337- Configure any required platform storage to allow loading further bootloader 338 images. 339- Enable the MMU and map the memory it needs to access. 340- Perform platform security setup to allow access to controlled components. 341- Reserve some memory for passing information to the next bootloader image 342 EL3 Runtime Software and populate it. 343- Define the extents of memory available for loading each subsequent 344 bootloader image. 345- If BL1 has passed TB_FW_CONFIG dynamic configuration file in ``arg0``, 346 then parse it. 347 348Image loading in BL2 349^^^^^^^^^^^^^^^^^^^^ 350 351BL2 generic code loads the images based on the list of loadable images 352provided by the platform. BL2 passes the list of executable images 353provided by the platform to the next handover BL image. 354 355The list of loadable images provided by the platform may also contain 356dynamic configuration files. The files are loaded and can be parsed as 357needed in the ``bl2_plat_handle_post_image_load()`` function. These 358configuration files can be passed to next Boot Loader stages as arguments 359by updating the corresponding entrypoint information in this function. 360 361SCP_BL2 (System Control Processor Firmware) image load 362^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 363 364Some systems have a separate System Control Processor (SCP) for power, clock, 365reset and system control. BL2 loads the optional SCP_BL2 image from platform 366storage into a platform-specific region of secure memory. The subsequent 367handling of SCP_BL2 is platform specific. For example, on the Juno Arm 368development platform port the image is transferred into SCP's internal memory 369using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM 370memory. The SCP executes SCP_BL2 and signals to the Application Processor (AP) 371for BL2 execution to continue. 372 373EL3 Runtime Software image load 374^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 375 376BL2 loads the EL3 Runtime Software image from platform storage into a platform- 377specific address in trusted SRAM. If there is not enough memory to load the 378image or image is missing it leads to an assertion failure. 379 380AArch64 BL32 (Secure-EL1 Payload) image load 381^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 382 383BL2 loads the optional BL32 image from platform storage into a platform- 384specific region of secure memory. The image executes in the secure world. BL2 385relies on BL31 to pass control to the BL32 image, if present. Hence, BL2 386populates a platform-specific area of memory with the entrypoint/load-address 387of the BL32 image. The value of the Saved Processor Status Register (``SPSR``) 388for entry into BL32 is not determined by BL2, it is initialized by the 389Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for 390managing interaction with BL32. This information is passed to BL31. 391 392BL33 (Non-trusted Firmware) image load 393^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 394 395BL2 loads the BL33 image (e.g. UEFI or other test or boot software) from 396platform storage into non-secure memory as defined by the platform. 397 398BL2 relies on EL3 Runtime Software to pass control to BL33 once secure state 399initialization is complete. Hence, BL2 populates a platform-specific area of 400memory with the entrypoint and Saved Program Status Register (``SPSR``) of the 401normal world software image. The entrypoint is the load address of the BL33 402image. The ``SPSR`` is determined as specified in Section 5.13 of the 403`PSCI`_. This information is passed to the EL3 Runtime Software. 404 405AArch64 BL31 (EL3 Runtime Software) execution 406^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 407 408BL2 execution continues as follows: 409 410#. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the 411 BL31 entrypoint. The exception is handled by the SMC exception handler 412 installed by BL1. 413 414#. BL1 turns off the MMU and flushes the caches. It clears the 415 ``SCTLR_EL3.M/I/C`` bits, flushes the data cache to the point of coherency 416 and invalidates the TLBs. 417 418#. BL1 passes control to BL31 at the specified entrypoint at EL3. 419 420Running BL2 at EL3 execution level 421~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 422 423Some platforms have a non-TF-A Boot ROM that expects the next boot stage 424to execute at EL3. On these platforms, TF-A BL1 is a waste of memory 425as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid 426this waste, a special mode enables BL2 to execute at EL3, which allows 427a non-TF-A Boot ROM to load and jump directly to BL2. This mode is selected 428when the build flag RESET_TO_BL2 is enabled. 429The main differences in this mode are: 430 431#. BL2 includes the reset code and the mailbox mechanism to differentiate 432 cold boot and warm boot. It runs at EL3 doing the arch 433 initialization required for EL3. 434 435#. BL2 does not receive the meminfo information from BL1 anymore. This 436 information can be passed by the Boot ROM or be internal to the 437 BL2 image. 438 439#. Since BL2 executes at EL3, BL2 jumps directly to the next image, 440 instead of invoking the RUN_IMAGE SMC call. 441 442 443We assume 3 different types of BootROM support on the platform: 444 445#. The Boot ROM always jumps to the same address, for both cold 446 and warm boot. In this case, we will need to keep a resident part 447 of BL2 whose memory cannot be reclaimed by any other image. The 448 linker script defines the symbols __TEXT_RESIDENT_START__ and 449 __TEXT_RESIDENT_END__ that allows the platform to configure 450 correctly the memory map. 451#. The platform has some mechanism to indicate the jump address to the 452 Boot ROM. Platform code can then program the jump address with 453 psci_warmboot_entrypoint during cold boot. 454#. The platform has some mechanism to program the reset address using 455 the PROGRAMMABLE_RESET_ADDRESS feature. Platform code can then 456 program the reset address with psci_warmboot_entrypoint during 457 cold boot, bypassing the boot ROM for warm boot. 458 459In the last 2 cases, no part of BL2 needs to remain resident at 460runtime. In the first 2 cases, we expect the Boot ROM to be able to 461differentiate between warm and cold boot, to avoid loading BL2 again 462during warm boot. 463 464This functionality can be tested with FVP loading the image directly 465in memory and changing the address where the system jumps at reset. 466For example: 467 468 -C cluster0.cpu0.RVBAR=0x4022000 469 --data cluster0.cpu0=bl2.bin@0x4022000 470 471With this configuration, FVP is like a platform of the first case, 472where the Boot ROM jumps always to the same address. For simplification, 473BL32 is loaded in DRAM in this case, to avoid other images reclaiming 474BL2 memory. 475 476 477AArch64 BL31 478~~~~~~~~~~~~ 479 480The image for this stage is loaded by BL2 and BL1 passes control to BL31 at 481EL3. BL31 executes solely in trusted SRAM. BL31 is linked against and 482loaded at a platform-specific base address (more information can be found later 483in this document). The functionality implemented by BL31 is as follows. 484 485Architectural initialization 486^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 487 488Currently, BL31 performs a similar architectural initialization to BL1 as 489far as system register settings are concerned. Since BL1 code resides in ROM, 490architectural initialization in BL31 allows override of any previous 491initialization done by BL1. 492 493BL31 initializes the per-CPU data framework, which provides a cache of 494frequently accessed per-CPU data optimised for fast, concurrent manipulation 495on different CPUs. This buffer includes pointers to per-CPU contexts, crash 496buffer, CPU reset and power down operations, PSCI data, platform data and so on. 497 498It then replaces the exception vectors populated by BL1 with its own. BL31 499exception vectors implement more elaborate support for handling SMCs since this 500is the only mechanism to access the runtime services implemented by BL31 (PSCI 501for example). BL31 checks each SMC for validity as specified by the 502`SMC Calling Convention`_ before passing control to the required SMC 503handler routine. 504 505BL31 programs the ``CNTFRQ_EL0`` register with the clock frequency of the system 506counter, which is provided by the platform. 507 508Platform initialization 509^^^^^^^^^^^^^^^^^^^^^^^ 510 511BL31 performs detailed platform initialization, which enables normal world 512software to function correctly. 513 514On Arm platforms, this consists of the following: 515 516- Initialize the console. 517- Configure the Interconnect to enable hardware coherency. 518- Enable the MMU and map the memory it needs to access. 519- Initialize the generic interrupt controller. 520- Initialize the power controller device. 521- Detect the system topology. 522 523Runtime services initialization 524^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 525 526BL31 is responsible for initializing the runtime services. One of them is PSCI. 527 528As part of the PSCI initializations, BL31 detects the system topology. It also 529initializes the data structures that implement the state machine used to track 530the state of power domain nodes. The state can be one of ``OFF``, ``RUN`` or 531``RETENTION``. All secondary CPUs are initially in the ``OFF`` state. The cluster 532that the primary CPU belongs to is ``ON``; any other cluster is ``OFF``. It also 533initializes the locks that protect them. BL31 accesses the state of a CPU or 534cluster immediately after reset and before the data cache is enabled in the 535warm boot path. It is not currently possible to use 'exclusive' based spinlocks, 536therefore BL31 uses locks based on Lamport's Bakery algorithm instead. 537 538The runtime service framework and its initialization is described in more 539detail in the "EL3 runtime services framework" section below. 540 541Details about the status of the PSCI implementation are provided in the 542"Power State Coordination Interface" section below. 543 544AArch64 BL32 (Secure-EL1 Payload) image initialization 545^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 546 547If a BL32 image is present then there must be a matching Secure-EL1 Payload 548Dispatcher (SPD) service (see later for details). During initialization 549that service must register a function to carry out initialization of BL32 550once the runtime services are fully initialized. BL31 invokes such a 551registered function to initialize BL32 before running BL33. This initialization 552is not necessary for AArch32 SPs. 553 554Details on BL32 initialization and the SPD's role are described in the 555:ref:`firmware_design_sel1_spd` section below. 556 557BL33 (Non-trusted Firmware) execution 558^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 559 560EL3 Runtime Software initializes the EL2 or EL1 processor context for normal- 561world cold boot, ensuring that no secure state information finds its way into 562the non-secure execution state. EL3 Runtime Software uses the entrypoint 563information provided by BL2 to jump to the Non-trusted firmware image (BL33) 564at the highest available Exception Level (EL2 if available, otherwise EL1). 565 566Using alternative Trusted Boot Firmware in place of BL1 & BL2 (AArch64 only) 567~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 568 569Some platforms have existing implementations of Trusted Boot Firmware that 570would like to use TF-A BL31 for the EL3 Runtime Software. To enable this 571firmware architecture it is important to provide a fully documented and stable 572interface between the Trusted Boot Firmware and BL31. 573 574Future changes to the BL31 interface will be done in a backwards compatible 575way, and this enables these firmware components to be independently enhanced/ 576updated to develop and exploit new functionality. 577 578Required CPU state when calling ``bl31_entrypoint()`` during cold boot 579^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 580 581This function must only be called by the primary CPU. 582 583On entry to this function the calling primary CPU must be executing in AArch64 584EL3, little-endian data access, and all interrupt sources masked: 585 586:: 587 588 PSTATE.EL = 3 589 PSTATE.RW = 1 590 PSTATE.DAIF = 0xf 591 SCTLR_EL3.EE = 0 592 593X0 and X1 can be used to pass information from the Trusted Boot Firmware to the 594platform code in BL31: 595 596:: 597 598 X0 : Reserved for common TF-A information 599 X1 : Platform specific information 600 601BL31 zero-init sections (e.g. ``.bss``) should not contain valid data on entry, 602these will be zero filled prior to invoking platform setup code. 603 604Use of the X0 and X1 parameters 605''''''''''''''''''''''''''''''' 606 607The parameters are platform specific and passed from ``bl31_entrypoint()`` to 608``bl31_early_platform_setup()``. The value of these parameters is never directly 609used by the common BL31 code. 610 611The convention is that ``X0`` conveys information regarding the BL31, BL32 and 612BL33 images from the Trusted Boot firmware and ``X1`` can be used for other 613platform specific purpose. This convention allows platforms which use TF-A's 614BL1 and BL2 images to transfer additional platform specific information from 615Secure Boot without conflicting with future evolution of TF-A using ``X0`` to 616pass a ``bl31_params`` structure. 617 618BL31 common and SPD initialization code depends on image and entrypoint 619information about BL33 and BL32, which is provided via BL31 platform APIs. 620This information is required until the start of execution of BL33. This 621information can be provided in a platform defined manner, e.g. compiled into 622the platform code in BL31, or provided in a platform defined memory location 623by the Trusted Boot firmware, or passed from the Trusted Boot Firmware via the 624Cold boot Initialization parameters. This data may need to be cleaned out of 625the CPU caches if it is provided by an earlier boot stage and then accessed by 626BL31 platform code before the caches are enabled. 627 628TF-A's BL2 implementation passes a ``bl31_params`` structure in 629``X0`` and the Arm development platforms interpret this in the BL31 platform 630code. 631 632MMU, Data caches & Coherency 633'''''''''''''''''''''''''''' 634 635BL31 does not depend on the enabled state of the MMU, data caches or 636interconnect coherency on entry to ``bl31_entrypoint()``. If these are disabled 637on entry, these should be enabled during ``bl31_plat_arch_setup()``. 638 639Data structures used in the BL31 cold boot interface 640'''''''''''''''''''''''''''''''''''''''''''''''''''' 641 642These structures are designed to support compatibility and independent 643evolution of the structures and the firmware images. For example, a version of 644BL31 that can interpret the BL3x image information from different versions of 645BL2, a platform that uses an extended entry_point_info structure to convey 646additional register information to BL31, or a ELF image loader that can convey 647more details about the firmware images. 648 649To support these scenarios the structures are versioned and sized, which enables 650BL31 to detect which information is present and respond appropriately. The 651``param_header`` is defined to capture this information: 652 653.. code:: c 654 655 typedef struct param_header { 656 uint8_t type; /* type of the structure */ 657 uint8_t version; /* version of this structure */ 658 uint16_t size; /* size of this structure in bytes */ 659 uint32_t attr; /* attributes: unused bits SBZ */ 660 } param_header_t; 661 662The structures using this format are ``entry_point_info``, ``image_info`` and 663``bl31_params``. The code that allocates and populates these structures must set 664the header fields appropriately, and the ``SET_PARAM_HEAD()`` a macro is defined 665to simplify this action. 666 667Required CPU state for BL31 Warm boot initialization 668^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 669 670When requesting a CPU power-on, or suspending a running CPU, TF-A provides 671the platform power management code with a Warm boot initialization 672entry-point, to be invoked by the CPU immediately after the reset handler. 673On entry to the Warm boot initialization function the calling CPU must be in 674AArch64 EL3, little-endian data access and all interrupt sources masked: 675 676:: 677 678 PSTATE.EL = 3 679 PSTATE.RW = 1 680 PSTATE.DAIF = 0xf 681 SCTLR_EL3.EE = 0 682 683The PSCI implementation will initialize the processor state and ensure that the 684platform power management code is then invoked as required to initialize all 685necessary system, cluster and CPU resources. 686 687AArch32 EL3 Runtime Software entrypoint interface 688~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 689 690To enable this firmware architecture it is important to provide a fully 691documented and stable interface between the Trusted Boot Firmware and the 692AArch32 EL3 Runtime Software. 693 694Future changes to the entrypoint interface will be done in a backwards 695compatible way, and this enables these firmware components to be independently 696enhanced/updated to develop and exploit new functionality. 697 698Required CPU state when entering during cold boot 699^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 700 701This function must only be called by the primary CPU. 702 703On entry to this function the calling primary CPU must be executing in AArch32 704EL3, little-endian data access, and all interrupt sources masked: 705 706:: 707 708 PSTATE.AIF = 0x7 709 SCTLR.EE = 0 710 711R0 and R1 are used to pass information from the Trusted Boot Firmware to the 712platform code in AArch32 EL3 Runtime Software: 713 714:: 715 716 R0 : Reserved for common TF-A information 717 R1 : Platform specific information 718 719Use of the R0 and R1 parameters 720''''''''''''''''''''''''''''''' 721 722The parameters are platform specific and the convention is that ``R0`` conveys 723information regarding the BL3x images from the Trusted Boot firmware and ``R1`` 724can be used for other platform specific purpose. This convention allows 725platforms which use TF-A's BL1 and BL2 images to transfer additional platform 726specific information from Secure Boot without conflicting with future 727evolution of TF-A using ``R0`` to pass a ``bl_params`` structure. 728 729The AArch32 EL3 Runtime Software is responsible for entry into BL33. This 730information can be obtained in a platform defined manner, e.g. compiled into 731the AArch32 EL3 Runtime Software, or provided in a platform defined memory 732location by the Trusted Boot firmware, or passed from the Trusted Boot Firmware 733via the Cold boot Initialization parameters. This data may need to be cleaned 734out of the CPU caches if it is provided by an earlier boot stage and then 735accessed by AArch32 EL3 Runtime Software before the caches are enabled. 736 737When using AArch32 EL3 Runtime Software, the Arm development platforms pass a 738``bl_params`` structure in ``R0`` from BL2 to be interpreted by AArch32 EL3 Runtime 739Software platform code. 740 741MMU, Data caches & Coherency 742'''''''''''''''''''''''''''' 743 744AArch32 EL3 Runtime Software must not depend on the enabled state of the MMU, 745data caches or interconnect coherency in its entrypoint. They must be explicitly 746enabled if required. 747 748Data structures used in cold boot interface 749''''''''''''''''''''''''''''''''''''''''''' 750 751The AArch32 EL3 Runtime Software cold boot interface uses ``bl_params`` instead 752of ``bl31_params``. The ``bl_params`` structure is based on the convention 753described in AArch64 BL31 cold boot interface section. 754 755Required CPU state for warm boot initialization 756^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 757 758When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3 759Runtime Software must ensure execution of a warm boot initialization entrypoint. 760If TF-A BL1 is used and the PROGRAMMABLE_RESET_ADDRESS build flag is false, 761then AArch32 EL3 Runtime Software must ensure that BL1 branches to the warm 762boot entrypoint by arranging for the BL1 platform function, 763plat_get_my_entrypoint(), to return a non-zero value. 764 765In this case, the warm boot entrypoint must be in AArch32 EL3, little-endian 766data access and all interrupt sources masked: 767 768:: 769 770 PSTATE.AIF = 0x7 771 SCTLR.EE = 0 772 773The warm boot entrypoint may be implemented by using TF-A 774``psci_warmboot_entrypoint()`` function. In that case, the platform must fulfil 775the pre-requisites mentioned in the 776:ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`. 777 778EL3 runtime services framework 779------------------------------ 780 781Software executing in the non-secure state and in the secure state at exception 782levels lower than EL3 will request runtime services using the Secure Monitor 783Call (SMC) instruction. These requests will follow the convention described in 784the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function 785identifiers to each SMC request and describes how arguments are passed and 786returned. 787 788The EL3 runtime services framework enables the development of services by 789different providers that can be easily integrated into final product firmware. 790The following sections describe the framework which facilitates the 791registration, initialization and use of runtime services in EL3 Runtime 792Software (BL31). 793 794The design of the runtime services depends heavily on the concepts and 795definitions described in the `SMCCC`_, in particular SMC Function IDs, Owning 796Entity Numbers (OEN), Fast and Yielding calls, and the SMC32 and SMC64 calling 797conventions. Please refer to that document for more detailed explanation of 798these terms. 799 800The following runtime services are expected to be implemented first. They have 801not all been instantiated in the current implementation. 802 803#. Standard service calls 804 805 This service is for management of the entire system. The Power State 806 Coordination Interface (`PSCI`_) is the first set of standard service calls 807 defined by Arm (see PSCI section later). 808 809#. Secure-EL1 Payload Dispatcher service 810 811 If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then 812 it also requires a *Secure Monitor* at EL3 to switch the EL1 processor 813 context between the normal world (EL1/EL2) and trusted world (Secure-EL1). 814 The Secure Monitor will make these world switches in response to SMCs. The 815 `SMCCC`_ provides for such SMCs with the Trusted OS Call and Trusted 816 Application Call OEN ranges. 817 818 The interface between the EL3 Runtime Software and the Secure-EL1 Payload is 819 not defined by the `SMCCC`_ or any other standard. As a result, each 820 Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime 821 service - within TF-A this service is referred to as the Secure-EL1 Payload 822 Dispatcher (SPD). 823 824 TF-A provides a Test Secure-EL1 Payload (TSP) and its associated Dispatcher 825 (TSPD). Details of SPD design and TSP/TSPD operation are described in the 826 :ref:`firmware_design_sel1_spd` section below. 827 828#. CPU implementation service 829 830 This service will provide an interface to CPU implementation specific 831 services for a given platform e.g. access to processor errata workarounds. 832 This service is currently unimplemented. 833 834Additional services for Arm Architecture, SiP and OEM calls can be implemented. 835Each implemented service handles a range of SMC function identifiers as 836described in the `SMCCC`_. 837 838Registration 839~~~~~~~~~~~~ 840 841A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying 842the name of the service, the range of OENs covered, the type of service and 843initialization and call handler functions. This macro instantiates a ``const struct rt_svc_desc`` for the service with these details (see ``runtime_svc.h``). 844This structure is allocated in a special ELF section ``.rt_svc_descs``, enabling 845the framework to find all service descriptors included into BL31. 846 847The specific service for a SMC Function is selected based on the OEN and call 848type of the Function ID, and the framework uses that information in the service 849descriptor to identify the handler for the SMC Call. 850 851The service descriptors do not include information to identify the precise set 852of SMC function identifiers supported by this service implementation, the 853security state from which such calls are valid nor the capability to support 85464-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately 855to these aspects of a SMC call is the responsibility of the service 856implementation, the framework is focused on integration of services from 857different providers and minimizing the time taken by the framework before the 858service handler is invoked. 859 860Details of the parameters, requirements and behavior of the initialization and 861call handling functions are provided in the following sections. 862 863Initialization 864~~~~~~~~~~~~~~ 865 866``runtime_svc_init()`` in ``runtime_svc.c`` initializes the runtime services 867framework running on the primary CPU during cold boot as part of the BL31 868initialization. This happens prior to initializing a Trusted OS and running 869Normal world boot firmware that might in turn use these services. 870Initialization involves validating each of the declared runtime service 871descriptors, calling the service initialization function and populating the 872index used for runtime lookup of the service. 873 874The BL31 linker script collects all of the declared service descriptors into a 875single array and defines symbols that allow the framework to locate and traverse 876the array, and determine its size. 877 878The framework does basic validation of each descriptor to halt firmware 879initialization if service declaration errors are detected. The framework does 880not check descriptors for the following error conditions, and may behave in an 881unpredictable manner under such scenarios: 882 883#. Overlapping OEN ranges 884#. Multiple descriptors for the same range of OENs and ``call_type`` 885#. Incorrect range of owning entity numbers for a given ``call_type`` 886 887Once validated, the service ``init()`` callback is invoked. This function carries 888out any essential EL3 initialization before servicing requests. The ``init()`` 889function is only invoked on the primary CPU during cold boot. If the service 890uses per-CPU data this must either be initialized for all CPUs during this call, 891or be done lazily when a CPU first issues an SMC call to that service. If 892``init()`` returns anything other than ``0``, this is treated as an initialization 893error and the service is ignored: this does not cause the firmware to halt. 894 895The OEN and call type fields present in the SMC Function ID cover a total of 896128 distinct services, but in practice a single descriptor can cover a range of 897OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a 898service handler, the framework uses an array of 128 indices that map every 899distinct OEN/call-type combination either to one of the declared services or to 900indicate the service is not handled. This ``rt_svc_descs_indices[]`` array is 901populated for all of the OENs covered by a service after the service ``init()`` 902function has reported success. So a service that fails to initialize will never 903have it's ``handle()`` function invoked. 904 905The following figure shows how the ``rt_svc_descs_indices[]`` index maps the SMC 906Function ID call type and OEN onto a specific service handler in the 907``rt_svc_descs[]`` array. 908 909|Image 1| 910 911.. _handling-an-smc: 912 913Handling an SMC 914~~~~~~~~~~~~~~~ 915 916When the EL3 runtime services framework receives a Secure Monitor Call, the SMC 917Function ID is passed in W0 from the lower exception level (as per the 918`SMCCC`_). If the calling register width is AArch32, it is invalid to invoke an 919SMC Function which indicates the SMC64 calling convention: such calls are 920ignored and return the Unknown SMC Function Identifier result code ``0xFFFFFFFF`` 921in R0/X0. 922 923Bit[31] (fast/yielding call) and bits[29:24] (owning entity number) of the SMC 924Function ID are combined to index into the ``rt_svc_descs_indices[]`` array. The 925resulting value might indicate a service that has no handler, in this case the 926framework will also report an Unknown SMC Function ID. Otherwise, the value is 927used as a further index into the ``rt_svc_descs[]`` array to locate the required 928service and handler. 929 930The service's ``handle()`` callback is provided with five of the SMC parameters 931directly, the others are saved into memory for retrieval (if needed) by the 932handler. The handler is also provided with an opaque ``handle`` for use with the 933supporting library for parameter retrieval, setting return values and context 934manipulation. The ``flags`` parameter indicates the security state of the caller 935and the state of the SVE hint bit per the SMCCCv1.3. The framework finally sets 936up the execution stack for the handler, and invokes the services ``handle()`` 937function. 938 939On return from the handler the result registers are populated in X0-X7 as needed 940before restoring the stack and CPU state and returning from the original SMC. 941 942Exception Handling Framework 943---------------------------- 944 945Please refer to the :ref:`Exception Handling Framework` document. 946 947Power State Coordination Interface 948---------------------------------- 949 950TODO: Provide design walkthrough of PSCI implementation. 951 952The PSCI v1.1 specification categorizes APIs as optional and mandatory. All the 953mandatory APIs in PSCI v1.1, PSCI v1.0 and in PSCI v0.2 draft specification 954`PSCI`_ are implemented. The table lists the PSCI v1.1 APIs and their support 955in generic code. 956 957An API implementation might have a dependency on platform code e.g. CPU_SUSPEND 958requires the platform to export a part of the implementation. Hence the level 959of support of the mandatory APIs depends upon the support exported by the 960platform port as well. The Juno and FVP (all variants) platforms export all the 961required support. 962 963+-----------------------------+-------------+-------------------------------+ 964| PSCI v1.1 API | Supported | Comments | 965+=============================+=============+===============================+ 966| ``PSCI_VERSION`` | Yes | The version returned is 1.1 | 967+-----------------------------+-------------+-------------------------------+ 968| ``CPU_SUSPEND`` | Yes\* | | 969+-----------------------------+-------------+-------------------------------+ 970| ``CPU_OFF`` | Yes\* | | 971+-----------------------------+-------------+-------------------------------+ 972| ``CPU_ON`` | Yes\* | | 973+-----------------------------+-------------+-------------------------------+ 974| ``AFFINITY_INFO`` | Yes | | 975+-----------------------------+-------------+-------------------------------+ 976| ``MIGRATE`` | Yes\*\* | | 977+-----------------------------+-------------+-------------------------------+ 978| ``MIGRATE_INFO_TYPE`` | Yes\*\* | | 979+-----------------------------+-------------+-------------------------------+ 980| ``MIGRATE_INFO_CPU`` | Yes\*\* | | 981+-----------------------------+-------------+-------------------------------+ 982| ``SYSTEM_OFF`` | Yes\* | | 983+-----------------------------+-------------+-------------------------------+ 984| ``SYSTEM_RESET`` | Yes\* | | 985+-----------------------------+-------------+-------------------------------+ 986| ``PSCI_FEATURES`` | Yes | | 987+-----------------------------+-------------+-------------------------------+ 988| ``CPU_FREEZE`` | No | | 989+-----------------------------+-------------+-------------------------------+ 990| ``CPU_DEFAULT_SUSPEND`` | No | | 991+-----------------------------+-------------+-------------------------------+ 992| ``NODE_HW_STATE`` | Yes\* | | 993+-----------------------------+-------------+-------------------------------+ 994| ``SYSTEM_SUSPEND`` | Yes\* | | 995+-----------------------------+-------------+-------------------------------+ 996| ``PSCI_SET_SUSPEND_MODE`` | No | | 997+-----------------------------+-------------+-------------------------------+ 998| ``PSCI_STAT_RESIDENCY`` | Yes\* | | 999+-----------------------------+-------------+-------------------------------+ 1000| ``PSCI_STAT_COUNT`` | Yes\* | | 1001+-----------------------------+-------------+-------------------------------+ 1002| ``SYSTEM_RESET2`` | Yes\* | | 1003+-----------------------------+-------------+-------------------------------+ 1004| ``MEM_PROTECT`` | Yes\* | | 1005+-----------------------------+-------------+-------------------------------+ 1006| ``MEM_PROTECT_CHECK_RANGE`` | Yes\* | | 1007+-----------------------------+-------------+-------------------------------+ 1008 1009\*Note : These PSCI APIs require platform power management hooks to be 1010registered with the generic PSCI code to be supported. 1011 1012\*\*Note : These PSCI APIs require appropriate Secure Payload Dispatcher 1013hooks to be registered with the generic PSCI code to be supported. 1014 1015The PSCI implementation in TF-A is a library which can be integrated with 1016AArch64 or AArch32 EL3 Runtime Software for Armv8-A systems. A guide to 1017integrating PSCI library with AArch32 EL3 Runtime Software can be found 1018at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`. 1019 1020.. _firmware_design_sel1_spd: 1021 1022Secure-EL1 Payloads and Dispatchers 1023----------------------------------- 1024 1025On a production system that includes a Trusted OS running in Secure-EL1/EL0, 1026the Trusted OS is coupled with a companion runtime service in the BL31 1027firmware. This service is responsible for the initialisation of the Trusted 1028OS and all communications with it. The Trusted OS is the BL32 stage of the 1029boot flow in TF-A. The firmware will attempt to locate, load and execute a 1030BL32 image. 1031 1032TF-A uses a more general term for the BL32 software that runs at Secure-EL1 - 1033the *Secure-EL1 Payload* - as it is not always a Trusted OS. 1034 1035TF-A provides a Test Secure-EL1 Payload (TSP) and a Test Secure-EL1 Payload 1036Dispatcher (TSPD) service as an example of how a Trusted OS is supported on a 1037production system using the Runtime Services Framework. On such a system, the 1038Test BL32 image and service are replaced by the Trusted OS and its dispatcher 1039service. The TF-A build system expects that the dispatcher will define the 1040build flag ``NEED_BL32`` to enable it to include the BL32 in the build either 1041as a binary or to compile from source depending on whether the ``BL32`` build 1042option is specified or not. 1043 1044The TSP runs in Secure-EL1. It is designed to demonstrate synchronous 1045communication with the normal-world software running in EL1/EL2. Communication 1046is initiated by the normal-world software 1047 1048- either directly through a Fast SMC (as defined in the `SMCCC`_) 1049 1050- or indirectly through a `PSCI`_ SMC. The `PSCI`_ implementation in turn 1051 informs the TSPD about the requested power management operation. This allows 1052 the TSP to prepare for or respond to the power state change 1053 1054The TSPD service is responsible for. 1055 1056- Initializing the TSP 1057 1058- Routing requests and responses between the secure and the non-secure 1059 states during the two types of communications just described 1060 1061Initializing a BL32 Image 1062~~~~~~~~~~~~~~~~~~~~~~~~~ 1063 1064The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing 1065the BL32 image. It needs access to the information passed by BL2 to BL31 to do 1066so. This is provided by: 1067 1068.. code:: c 1069 1070 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t); 1071 1072which returns a reference to the ``entry_point_info`` structure corresponding to 1073the image which will be run in the specified security state. The SPD uses this 1074API to get entry point information for the SECURE image, BL32. 1075 1076In the absence of a BL32 image, BL31 passes control to the normal world 1077bootloader image (BL33). When the BL32 image is present, it is typical 1078that the SPD wants control to be passed to BL32 first and then later to BL33. 1079 1080To do this the SPD has to register a BL32 initialization function during 1081initialization of the SPD service. The BL32 initialization function has this 1082prototype: 1083 1084.. code:: c 1085 1086 int32_t init(void); 1087 1088and is registered using the ``bl31_register_bl32_init()`` function. 1089 1090TF-A supports two approaches for the SPD to pass control to BL32 before 1091returning through EL3 and running the non-trusted firmware (BL33): 1092 1093#. In the BL32 setup function, use ``bl31_set_next_image_type()`` to 1094 request that the exit from ``bl31_main()`` is to the BL32 entrypoint in 1095 Secure-EL1. BL31 will exit to BL32 using the asynchronous method by 1096 calling ``bl31_prepare_next_image_entry()`` and ``el3_exit()``. 1097 1098 When the BL32 has completed initialization at Secure-EL1, it returns to 1099 BL31 by issuing an SMC, using a Function ID allocated to the SPD. On 1100 receipt of this SMC, the SPD service handler should switch the CPU context 1101 from trusted to normal world and use the ``bl31_set_next_image_type()`` and 1102 ``bl31_prepare_next_image_entry()`` functions to set up the initial return to 1103 the normal world firmware BL33. On return from the handler the framework 1104 will exit to EL2 and run BL33. 1105 1106#. The BL32 setup function registers an initialization function using 1107 ``bl31_register_bl32_init()`` which provides a SPD-defined mechanism to 1108 invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32 1109 entrypoint. 1110 1111 .. note:: 1112 The Test SPD service included with TF-A provides one implementation 1113 of such a mechanism. 1114 1115 On completion BL32 returns control to BL31 via a SMC, and on receipt the 1116 SPD service handler invokes the synchronous call return mechanism to return 1117 to the BL32 initialization function. On return from this function, 1118 ``bl31_main()`` will set up the return to the normal world firmware BL33 and 1119 continue the boot process in the normal world. 1120 1121Exception handling in BL31 1122-------------------------- 1123 1124When exception occurs, PE must execute handler corresponding to exception. The 1125location in memory where the handler is stored is called the exception vector. 1126For ARM architecture, exception vectors are stored in a table, called the exception 1127vector table. 1128 1129Each EL (except EL0) has its own vector table, VBAR_ELn register stores the base 1130of vector table. Refer to `AArch64 exception vector table`_ 1131 1132Current EL with SP_EL0 1133~~~~~~~~~~~~~~~~~~~~~~ 1134 1135- Sync exception : Not expected except for BRK instruction, its debugging tool which 1136 a programmer may place at specific points in a program, to check the state of 1137 processor flags at these points in the code. 1138 1139- IRQ/FIQ : Unexpected exception, panic 1140 1141- SError : "plat_handle_el3_ea", defaults to panic 1142 1143Current EL with SP_ELx 1144~~~~~~~~~~~~~~~~~~~~~~ 1145 1146- Sync exception : Unexpected exception, panic 1147 1148- IRQ/FIQ : Unexpected exception, panic 1149 1150- SError : "plat_handle_el3_ea" Except for special handling of lower EL's SError exception 1151 which gets triggered in EL3 when PSTATE.A is unmasked. Its only applicable when lower 1152 EL's EA is routed to EL3 (FFH_SUPPORT=1). 1153 1154Lower EL Exceptions 1155~~~~~~~~~~~~~~~~~~~ 1156 1157Applies to all the exceptions in both AArch64/AArch32 mode of lower EL. 1158 1159Before handling any lower EL exception, we synchronize the errors at EL3 entry to ensure 1160that any errors pertaining to lower EL is isolated/identified. If we continue without 1161identifying these errors early on then these errors will trigger in EL3 (as SError from 1162current EL) any time after PSTATE.A is unmasked. This is wrong because the error originated 1163in lower EL but exception happened in EL3. 1164 1165To solve this problem, synchronize the errors at EL3 entry and check for any pending 1166errors (async EA). If there is no pending error then continue with original exception. 1167If there is a pending error then, handle them based on routing model of EA's. Refer to 1168:ref:`Reliability, Availability, and Serviceability (RAS) Extensions` for details about 1169routing models. 1170 1171- KFH : Reflect it back to lower EL using **reflect_pending_async_ea_to_lower_el()** 1172 1173- FFH : Handle the synchronized error first using **handle_pending_async_ea()** after 1174 that continue with original exception. It is the only scenario where EL3 is capable 1175 of doing nested exception handling. 1176 1177After synchronizing and handling lower EL SErrors, unmask EA (PSTATE.A) to ensure 1178that any further EA's caused by EL3 are caught. 1179 1180Crash Reporting in BL31 1181----------------------- 1182 1183BL31 implements a scheme for reporting the processor state when an unhandled 1184exception is encountered. The reporting mechanism attempts to preserve all the 1185register contents and report it via a dedicated UART (PL011 console). BL31 1186reports the general purpose, EL3, Secure EL1 and some EL2 state registers. 1187 1188A dedicated per-CPU crash stack is maintained by BL31 and this is retrieved via 1189the per-CPU pointer cache. The implementation attempts to minimise the memory 1190required for this feature. The file ``crash_reporting.S`` contains the 1191implementation for crash reporting. 1192 1193The sample crash output is shown below. 1194 1195:: 1196 1197 x0 = 0x000000002a4a0000 1198 x1 = 0x0000000000000001 1199 x2 = 0x0000000000000002 1200 x3 = 0x0000000000000003 1201 x4 = 0x0000000000000004 1202 x5 = 0x0000000000000005 1203 x6 = 0x0000000000000006 1204 x7 = 0x0000000000000007 1205 x8 = 0x0000000000000008 1206 x9 = 0x0000000000000009 1207 x10 = 0x0000000000000010 1208 x11 = 0x0000000000000011 1209 x12 = 0x0000000000000012 1210 x13 = 0x0000000000000013 1211 x14 = 0x0000000000000014 1212 x15 = 0x0000000000000015 1213 x16 = 0x0000000000000016 1214 x17 = 0x0000000000000017 1215 x18 = 0x0000000000000018 1216 x19 = 0x0000000000000019 1217 x20 = 0x0000000000000020 1218 x21 = 0x0000000000000021 1219 x22 = 0x0000000000000022 1220 x23 = 0x0000000000000023 1221 x24 = 0x0000000000000024 1222 x25 = 0x0000000000000025 1223 x26 = 0x0000000000000026 1224 x27 = 0x0000000000000027 1225 x28 = 0x0000000000000028 1226 x29 = 0x0000000000000029 1227 x30 = 0x0000000088000b78 1228 scr_el3 = 0x000000000003073d 1229 sctlr_el3 = 0x00000000b0cd183f 1230 cptr_el3 = 0x0000000000000000 1231 tcr_el3 = 0x000000008080351c 1232 daif = 0x00000000000002c0 1233 mair_el3 = 0x00000000004404ff 1234 spsr_el3 = 0x0000000060000349 1235 elr_el3 = 0x0000000088000114 1236 ttbr0_el3 = 0x0000000004018201 1237 esr_el3 = 0x00000000be000000 1238 far_el3 = 0x0000000000000000 1239 spsr_el1 = 0x0000000000000000 1240 elr_el1 = 0x0000000000000000 1241 spsr_abt = 0x0000000000000000 1242 spsr_und = 0x0000000000000000 1243 spsr_irq = 0x0000000000000000 1244 spsr_fiq = 0x0000000000000000 1245 sctlr_el1 = 0x0000000030d00800 1246 actlr_el1 = 0x0000000000000000 1247 cpacr_el1 = 0x0000000000000000 1248 csselr_el1 = 0x0000000000000000 1249 sp_el1 = 0x0000000000000000 1250 esr_el1 = 0x0000000000000000 1251 ttbr0_el1 = 0x0000000000000000 1252 ttbr1_el1 = 0x0000000000000000 1253 mair_el1 = 0x0000000000000000 1254 amair_el1 = 0x0000000000000000 1255 tcr_el1 = 0x0000000000000000 1256 tpidr_el1 = 0x0000000000000000 1257 tpidr_el0 = 0x0000000000000000 1258 tpidrro_el0 = 0x0000000000000000 1259 par_el1 = 0x0000000000000000 1260 mpidr_el1 = 0x0000000080000000 1261 afsr0_el1 = 0x0000000000000000 1262 afsr1_el1 = 0x0000000000000000 1263 contextidr_el1 = 0x0000000000000000 1264 vbar_el1 = 0x0000000000000000 1265 cntp_ctl_el0 = 0x0000000000000000 1266 cntp_cval_el0 = 0x0000000000000000 1267 cntv_ctl_el0 = 0x0000000000000000 1268 cntv_cval_el0 = 0x0000000000000000 1269 cntkctl_el1 = 0x0000000000000000 1270 sp_el0 = 0x0000000004014940 1271 isr_el1 = 0x0000000000000000 1272 dacr32_el2 = 0x0000000000000000 1273 ifsr32_el2 = 0x0000000000000000 1274 icc_hppir0_el1 = 0x00000000000003ff 1275 icc_hppir1_el1 = 0x00000000000003ff 1276 icc_ctlr_el3 = 0x0000000000080400 1277 gicd_ispendr regs (Offsets 0x200-0x278) 1278 Offset Value 1279 0x200: 0x0000000000000000 1280 0x208: 0x0000000000000000 1281 0x210: 0x0000000000000000 1282 0x218: 0x0000000000000000 1283 0x220: 0x0000000000000000 1284 0x228: 0x0000000000000000 1285 0x230: 0x0000000000000000 1286 0x238: 0x0000000000000000 1287 0x240: 0x0000000000000000 1288 0x248: 0x0000000000000000 1289 0x250: 0x0000000000000000 1290 0x258: 0x0000000000000000 1291 0x260: 0x0000000000000000 1292 0x268: 0x0000000000000000 1293 0x270: 0x0000000000000000 1294 0x278: 0x0000000000000000 1295 1296Guidelines for Reset Handlers 1297----------------------------- 1298 1299TF-A implements a framework that allows CPU and platform ports to perform 1300actions very early after a CPU is released from reset in both the cold and warm 1301boot paths. This is done by calling the ``reset_handler()`` function in both 1302the BL1 and BL31 images. It in turn calls the platform and CPU specific reset 1303handling functions. 1304 1305Details for implementing a CPU specific reset handler can be found in 1306:ref:`firmware_design_cpu_specific_reset_handling`. Details for implementing a 1307platform specific reset handler can be found in the :ref:`Porting Guide` (see 1308the``plat_reset_handler()`` function). 1309 1310When adding functionality to a reset handler, keep in mind that if a different 1311reset handling behavior is required between the first and the subsequent 1312invocations of the reset handling code, this should be detected at runtime. 1313In other words, the reset handler should be able to detect whether an action has 1314already been performed and act as appropriate. Possible courses of actions are, 1315e.g. skip the action the second time, or undo/redo it. 1316 1317.. _configuring-secure-interrupts: 1318 1319Configuring secure interrupts 1320----------------------------- 1321 1322The GIC driver is responsible for performing initial configuration of secure 1323interrupts on the platform. To this end, the platform is expected to provide the 1324GIC driver (either GICv2 or GICv3, as selected by the platform) with the 1325interrupt configuration during the driver initialisation. 1326 1327Secure interrupt configuration are specified in an array of secure interrupt 1328properties. In this scheme, in both GICv2 and GICv3 driver data structures, the 1329``interrupt_props`` member points to an array of interrupt properties. Each 1330element of the array specifies the interrupt number and its attributes 1331(priority, group, configuration). Each element of the array shall be populated 1332by the macro ``INTR_PROP_DESC()``. The macro takes the following arguments: 1333 1334- 13-bit interrupt number, 1335 1336- 8-bit interrupt priority, 1337 1338- Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``, 1339 ``INTR_TYPE_NS``), 1340 1341- Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or 1342 ``GIC_INTR_CFG_EDGE``). 1343 1344.. _firmware_design_cpu_ops_fwk: 1345 1346CPU specific operations framework 1347--------------------------------- 1348 1349Certain aspects of the Armv8-A architecture are implementation defined, 1350that is, certain behaviours are not architecturally defined, but must be 1351defined and documented by individual processor implementations. TF-A 1352implements a framework which categorises the common implementation defined 1353behaviours and allows a processor to export its implementation of that 1354behaviour. The categories are: 1355 1356#. Processor specific reset sequence. 1357 1358#. Processor specific power down sequences. 1359 1360#. Processor specific register dumping as a part of crash reporting. 1361 1362#. Errata status reporting. 1363 1364Each of the above categories fulfils a different requirement. 1365 1366#. allows any processor specific initialization before the caches and MMU 1367 are turned on, like implementation of errata workarounds, entry into 1368 the intra-cluster coherency domain etc. 1369 1370#. allows each processor to implement the power down sequence mandated in 1371 its Technical Reference Manual (TRM). 1372 1373#. allows a processor to provide additional information to the developer 1374 in the event of a crash, for example Cortex-A53 has registers which 1375 can expose the data cache contents. 1376 1377#. allows a processor to define a function that inspects and reports the status 1378 of all errata workarounds on that processor. 1379 1380Please note that only 2. is mandated by the TRM. 1381 1382The CPU specific operations framework scales to accommodate a large number of 1383different CPUs during power down and reset handling. The platform can specify 1384any CPU optimization it wants to enable for each CPU. It can also specify 1385the CPU errata workarounds to be applied for each CPU type during reset 1386handling by defining CPU errata compile time macros. Details on these macros 1387can be found in the :ref:`Arm CPU Specific Build Macros` document. 1388 1389The CPU specific operations framework depends on the ``cpu_ops`` structure which 1390needs to be exported for each type of CPU in the platform. It is defined in 1391``include/lib/cpus/aarch64/cpu_macros.S`` and has the following fields : ``midr``, 1392``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and 1393``cpu_reg_dump()``. 1394 1395The CPU specific files in ``lib/cpus`` export a ``cpu_ops`` data structure with 1396suitable handlers for that CPU. For example, ``lib/cpus/aarch64/cortex_a53.S`` 1397exports the ``cpu_ops`` for Cortex-A53 CPU. According to the platform 1398configuration, these CPU specific files must be included in the build by 1399the platform makefile. The generic CPU specific operations framework code exists 1400in ``lib/cpus/aarch64/cpu_helpers.S``. 1401 1402CPU PCS 1403~~~~~~~ 1404 1405All assembly functions in CPU files are asked to follow a modified version of 1406the Procedure Call Standard (PCS) in their internals. This is done to ensure 1407calling these functions from outside the file doesn't unexpectedly corrupt 1408registers in the very early environment and to help the internals to be easier 1409to understand. Please see the :ref:`firmware_design_cpu_errata_implementation` 1410for any function specific restrictions. 1411 1412+--------------+---------------------------------+ 1413| register | use | 1414+==============+=================================+ 1415| x0 - x15 | scratch | 1416+--------------+---------------------------------+ 1417| x16, x17 | do not use (used by the linker) | 1418+--------------+---------------------------------+ 1419| x18 | do not use (platform register) | 1420+--------------+---------------------------------+ 1421| x19 - x28 | callee saved | 1422+--------------+---------------------------------+ 1423| x29, x30 | FP, LR | 1424+--------------+---------------------------------+ 1425 1426.. _firmware_design_cpu_specific_reset_handling: 1427 1428CPU specific Reset Handling 1429~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1430 1431After a reset, the state of the CPU when it calls generic reset handler is: 1432MMU turned off, both instruction and data caches turned off, not part 1433of any coherency domain and no stack. 1434 1435The BL entrypoint code first invokes the ``plat_reset_handler()`` to allow 1436the platform to perform any system initialization required and any system 1437errata workarounds that needs to be applied. The ``get_cpu_ops_ptr()`` reads 1438the current CPU midr, finds the matching ``cpu_ops`` entry in the ``cpu_ops`` 1439array and returns it. Note that only the part number and implementer fields 1440in midr are used to find the matching ``cpu_ops`` entry. The ``reset_func()`` in 1441the returned ``cpu_ops`` is then invoked which executes the required reset 1442handling for that CPU and also any errata workarounds enabled by the platform. 1443 1444It should be defined using the ``cpu_reset_func_{start,end}`` macros and its 1445body may only clobber x0 to x14 with x14 being the cpu_rev parameter. 1446 1447CPU specific power down sequence 1448~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1449 1450During the BL31 initialization sequence, the pointer to the matching ``cpu_ops`` 1451entry is stored in per-CPU data by ``init_cpu_ops()`` so that it can be quickly 1452retrieved during power down sequences. 1453 1454Various CPU drivers register handlers to perform power down at certain power 1455levels for that specific CPU. The PSCI service, upon receiving a power down 1456request, determines the highest power level at which to execute power down 1457sequence for a particular CPU. It uses the ``prepare_cpu_pwr_dwn()`` function to 1458pick the right power down handler for the requested level. The function 1459retrieves ``cpu_ops`` pointer member of per-CPU data, and from that, further 1460retrieves ``cpu_pwr_down_ops`` array, and indexes into the required level. If the 1461requested power level is higher than what a CPU driver supports, the handler 1462registered for highest level is invoked. 1463 1464At runtime the platform hooks for power down are invoked by the PSCI service to 1465perform platform specific operations during a power down sequence, for example 1466turning off CCI coherency during a cluster power down. 1467 1468CPU specific register reporting during crash 1469~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1470 1471If the crash reporting is enabled in BL31, when a crash occurs, the crash 1472reporting framework calls ``do_cpu_reg_dump`` which retrieves the matching 1473``cpu_ops`` using ``get_cpu_ops_ptr()`` function. The ``cpu_reg_dump()`` in 1474``cpu_ops`` is invoked, which then returns the CPU specific register values to 1475be reported and a pointer to the ASCII list of register names in a format 1476expected by the crash reporting framework. 1477 1478.. _firmware_design_cpu_errata_implementation: 1479 1480CPU errata implementation 1481~~~~~~~~~~~~~~~~~~~~~~~~~ 1482 1483Errata workarounds for CPUs supported in TF-A are applied during both cold and 1484warm boots, shortly after reset. Individual Errata workarounds are enabled as 1485build options. Some errata workarounds have potential run-time implications; 1486therefore some are enabled by default, others not. Platform ports shall 1487override build options to enable or disable errata as appropriate. The CPU 1488drivers take care of applying errata workarounds that are enabled and applicable 1489to a given CPU. 1490 1491Each erratum has a build flag in ``lib/cpus/cpu-ops.mk`` of the form: 1492``ERRATA_<cpu_num>_<erratum_id>``. It also has a short description in 1493:ref:`arm_cpu_macros_errata_workarounds` on when it should apply. 1494 1495Errata framework 1496^^^^^^^^^^^^^^^^ 1497 1498The errata framework is a convention and a small library to allow errata to be 1499automatically discovered. It enables compliant errata to be automatically 1500applied and reported at runtime (either by status reporting or the errata ABI). 1501 1502To write a compliant mitigation for erratum number ``erratum_id`` on a cpu that 1503declared itself (with ``declare_cpu_ops``) as ``cpu_name`` one needs 3 things: 1504 1505#. A CPU revision checker function: ``check_erratum_<cpu_name>_<erratum_id>`` 1506 1507 It should check whether this erratum applies on this revision of this CPU. 1508 It will be called with the CPU revision as its first parameter (x0) and 1509 should return one of ``ERRATA_APPLIES`` or ``ERRATA_NOT_APPLIES``. 1510 1511 It may only clobber x0 to x4. The rest should be treated as callee-saved. 1512 1513#. A workaround function: ``erratum_<cpu_name>_<erratum_id>_wa`` 1514 1515 It should obtain the cpu revision (with ``cpu_get_rev_var``), call its 1516 revision checker, and perform the mitigation, should the erratum apply. 1517 1518 It may only clobber x0 to x8. The rest should be treated as callee-saved. 1519 1520#. Register itself to the framework 1521 1522 Do this with 1523 ``add_erratum_entry <cpu_name>, ERRATUM(<erratum_id>), <errata_flag>`` 1524 where the ``errata_flag`` is the enable flag in ``cpu-ops.mk`` described 1525 above. 1526 1527See the next section on how to do this easily. 1528 1529.. note:: 1530 1531 CVEs have the format ``CVE_<year>_<number>``. To fit them in the framework, the 1532 ``erratum_id`` for the checker and the workaround functions become the 1533 ``number`` part of its name and the ``ERRATUM(<number>)`` part of the 1534 registration should instead be ``CVE(<year>, <number>)``. In the extremely 1535 unlikely scenario where a CVE and an erratum numbers clash, the CVE number 1536 should be prefixed with a zero. 1537 1538 Also, their build flag should be ``WORKAROUND_CVE_<year>_<number>``. 1539 1540.. note:: 1541 1542 AArch32 uses the legacy convention. The checker function has the format 1543 ``check_errata_<erratum_id>`` and the workaround has the format 1544 ``errata_<cpu_number>_<erratum_id>_wa`` where ``cpu_number`` is the shortform 1545 letter and number name of the CPU. 1546 1547 For CVEs the ``erratum_id`` also becomes ``cve_<year>_<number>``. 1548 1549Errata framework helpers 1550^^^^^^^^^^^^^^^^^^^^^^^^ 1551 1552Writing these errata involves lots of boilerplate and repetitive code. On 1553AArch64 there are helpers to omit most of this. They are located in 1554``include/lib/cpus/aarch64/cpu_macros.S`` and the preferred way to implement 1555errata. Please see their comments on how to use them. 1556 1557The most common type of erratum workaround, one that just sets a "chicken" bit 1558in some arbitrary register, would have an implementation for the Cortex-A77, 1559erratum #1925769 like:: 1560 1561 workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769 1562 sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8 1563 workaround_reset_end cortex_a77, ERRATUM(1925769) 1564 1565 check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1) 1566 1567Status reporting 1568^^^^^^^^^^^^^^^^ 1569 1570In a debug build of TF-A, on a CPU that comes out of reset, both BL1 and the 1571runtime firmware (BL31 in AArch64, and BL32 in AArch32) will invoke a generic 1572errata status reporting function. It will read the ``errata_entries`` list of 1573that cpu and will report whether each known erratum was applied and, if not, 1574whether it should have been. 1575 1576Reporting the status of errata workaround is for informational purpose only; it 1577has no functional significance. 1578 1579Memory layout of BL images 1580-------------------------- 1581 1582Each bootloader image can be divided in 2 parts: 1583 1584- the static contents of the image. These are data actually stored in the 1585 binary on the disk. In the ELF terminology, they are called ``PROGBITS`` 1586 sections; 1587 1588- the run-time contents of the image. These are data that don't occupy any 1589 space in the binary on the disk. The ELF binary just contains some 1590 metadata indicating where these data will be stored at run-time and the 1591 corresponding sections need to be allocated and initialized at run-time. 1592 In the ELF terminology, they are called ``NOBITS`` sections. 1593 1594All PROGBITS sections are grouped together at the beginning of the image, 1595followed by all NOBITS sections. This is true for all TF-A images and it is 1596governed by the linker scripts. This ensures that the raw binary images are 1597as small as possible. If a NOBITS section was inserted in between PROGBITS 1598sections then the resulting binary file would contain zero bytes in place of 1599this NOBITS section, making the image unnecessarily bigger. Smaller images 1600allow faster loading from the FIP to the main memory. 1601 1602For BL31, a platform can specify an alternate location for NOBITS sections 1603(other than immediately following PROGBITS sections) by setting 1604``SEPARATE_NOBITS_REGION`` to 1 and defining ``BL31_NOBITS_BASE`` and 1605``BL31_NOBITS_LIMIT``. 1606 1607Linker scripts and symbols 1608~~~~~~~~~~~~~~~~~~~~~~~~~~ 1609 1610Each bootloader stage image layout is described by its own linker script. The 1611linker scripts export some symbols into the program symbol table. Their values 1612correspond to particular addresses. TF-A code can refer to these symbols to 1613figure out the image memory layout. 1614 1615Linker symbols follow the following naming convention in TF-A. 1616 1617- ``__<SECTION>_START__`` 1618 1619 Start address of a given section named ``<SECTION>``. 1620 1621- ``__<SECTION>_END__`` 1622 1623 End address of a given section named ``<SECTION>``. If there is an alignment 1624 constraint on the section's end address then ``__<SECTION>_END__`` corresponds 1625 to the end address of the section's actual contents, rounded up to the right 1626 boundary. Refer to the value of ``__<SECTION>_UNALIGNED_END__`` to know the 1627 actual end address of the section's contents. 1628 1629- ``__<SECTION>_UNALIGNED_END__`` 1630 1631 End address of a given section named ``<SECTION>`` without any padding or 1632 rounding up due to some alignment constraint. 1633 1634- ``__<SECTION>_SIZE__`` 1635 1636 Size (in bytes) of a given section named ``<SECTION>``. If there is an 1637 alignment constraint on the section's end address then ``__<SECTION>_SIZE__`` 1638 corresponds to the size of the section's actual contents, rounded up to the 1639 right boundary. In other words, ``__<SECTION>_SIZE__ = __<SECTION>_END__ - _<SECTION>_START__``. Refer to the value of ``__<SECTION>_UNALIGNED_SIZE__`` 1640 to know the actual size of the section's contents. 1641 1642- ``__<SECTION>_UNALIGNED_SIZE__`` 1643 1644 Size (in bytes) of a given section named ``<SECTION>`` without any padding or 1645 rounding up due to some alignment constraint. In other words, 1646 ``__<SECTION>_UNALIGNED_SIZE__ = __<SECTION>_UNALIGNED_END__ - __<SECTION>_START__``. 1647 1648Some of the linker symbols are mandatory as TF-A code relies on them to be 1649defined. They are listed in the following subsections. Some of them must be 1650provided for each bootloader stage and some are specific to a given bootloader 1651stage. 1652 1653The linker scripts define some extra, optional symbols. They are not actually 1654used by any code but they help in understanding the bootloader images' memory 1655layout as they are easy to spot in the link map files. 1656 1657Common linker symbols 1658^^^^^^^^^^^^^^^^^^^^^ 1659 1660All BL images share the following requirements: 1661 1662- The BSS section must be zero-initialised before executing any C code. 1663- The coherent memory section (if enabled) must be zero-initialised as well. 1664- The MMU setup code needs to know the extents of the coherent and read-only 1665 memory regions to set the right memory attributes. When 1666 ``SEPARATE_CODE_AND_RODATA=1``, it needs to know more specifically how the 1667 read-only memory region is divided between code and data. 1668 1669The following linker symbols are defined for this purpose: 1670 1671- ``__BSS_START__`` 1672- ``__BSS_SIZE__`` 1673- ``__COHERENT_RAM_START__`` Must be aligned on a page-size boundary. 1674- ``__COHERENT_RAM_END__`` Must be aligned on a page-size boundary. 1675- ``__COHERENT_RAM_UNALIGNED_SIZE__`` 1676- ``__RO_START__`` 1677- ``__RO_END__`` 1678- ``__TEXT_START__`` 1679- ``__TEXT_END_UNALIGNED__`` 1680- ``__TEXT_END__`` 1681- ``__RODATA_START__`` 1682- ``__RODATA_END_UNALIGNED__`` 1683- ``__RODATA_END__`` 1684 1685BL1's linker symbols 1686^^^^^^^^^^^^^^^^^^^^ 1687 1688BL1 being the ROM image, it has additional requirements. BL1 resides in ROM and 1689it is entirely executed in place but it needs some read-write memory for its 1690mutable data. Its ``.data`` section (i.e. its allocated read-write data) must be 1691relocated from ROM to RAM before executing any C code. 1692 1693The following additional linker symbols are defined for BL1: 1694 1695- ``__BL1_ROM_END__`` End address of BL1's ROM contents, covering its code 1696 and ``.data`` section in ROM. 1697- ``__DATA_ROM_START__`` Start address of the ``.data`` section in ROM. Must be 1698 aligned on a 16-byte boundary. 1699- ``__DATA_RAM_START__`` Address in RAM where the ``.data`` section should be 1700 copied over. Must be aligned on a 16-byte boundary. 1701- ``__DATA_SIZE__`` Size of the ``.data`` section (in ROM or RAM). 1702- ``__BL1_RAM_START__`` Start address of BL1 read-write data. 1703- ``__BL1_RAM_END__`` End address of BL1 read-write data. 1704 1705How to choose the right base addresses for each bootloader stage image 1706~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1707 1708There is currently no support for dynamic image loading in TF-A. This means 1709that all bootloader images need to be linked against their ultimate runtime 1710locations and the base addresses of each image must be chosen carefully such 1711that images don't overlap each other in an undesired way. As the code grows, 1712the base addresses might need adjustments to cope with the new memory layout. 1713 1714The memory layout is completely specific to the platform and so there is no 1715general recipe for choosing the right base addresses for each bootloader image. 1716However, there are tools to aid in understanding the memory layout. These are 1717the link map files: ``build/<platform>/<build-type>/bl<x>/bl<x>.map``, with ``<x>`` 1718being the stage bootloader. They provide a detailed view of the memory usage of 1719each image. Among other useful information, they provide the end address of 1720each image. 1721 1722- ``bl1.map`` link map file provides ``__BL1_RAM_END__`` address. 1723- ``bl2.map`` link map file provides ``__BL2_END__`` address. 1724- ``bl31.map`` link map file provides ``__BL31_END__`` address. 1725- ``bl32.map`` link map file provides ``__BL32_END__`` address. 1726 1727For each bootloader image, the platform code must provide its start address 1728as well as a limit address that it must not overstep. The latter is used in the 1729linker scripts to check that the image doesn't grow past that address. If that 1730happens, the linker will issue a message similar to the following: 1731 1732:: 1733 1734 aarch64-none-elf-ld: BLx has exceeded its limit. 1735 1736Additionally, if the platform memory layout implies some image overlaying like 1737on FVP, BL31 and TSP need to know the limit address that their PROGBITS 1738sections must not overstep. The platform code must provide those. 1739 1740TF-A does not provide any mechanism to verify at boot time that the memory 1741to load a new image is free to prevent overwriting a previously loaded image. 1742The platform must specify the memory available in the system for all the 1743relevant BL images to be loaded. 1744 1745For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will 1746return the region defined by the platform where BL1 intends to load BL2. The 1747``load_image()`` function performs bounds check for the image size based on the 1748base and maximum image size provided by the platforms. Platforms must take 1749this behaviour into account when defining the base/size for each of the images. 1750 1751Memory layout on Arm development platforms 1752^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1753 1754The following list describes the memory layout on the Arm development platforms: 1755 1756- A 4KB page of shared memory is used for communication between Trusted 1757 Firmware and the platform's power controller. This is located at the base of 1758 Trusted SRAM. The amount of Trusted SRAM available to load the bootloader 1759 images is reduced by the size of the shared memory. 1760 1761 The shared memory is used to store the CPUs' entrypoint mailbox. On Juno, 1762 this is also used for the MHU payload when passing messages to and from the 1763 SCP. 1764 1765- Another 4 KB page is reserved for passing memory layout between BL1 and BL2 1766 and also the dynamic firmware configurations. 1767 1768- On FVP, BL1 is originally sitting in the Trusted ROM at address ``0x0``. On 1769 Juno, BL1 resides in flash memory at address ``0x0BEC0000``. BL1 read-write 1770 data are relocated to the top of Trusted SRAM at runtime. 1771 1772- BL2 is loaded below BL1 RW 1773 1774- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP_MIN), 1775 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will 1776 overwrite BL1 R/W data and BL2. This implies that BL1 global variables 1777 remain valid only until execution reaches the EL3 Runtime Software entry 1778 point during a cold boot. 1779 1780- On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory 1781 region and transferred to the SCP before being overwritten by EL3 Runtime 1782 Software. 1783 1784- BL32 (for AArch64) can be loaded in one of the following locations: 1785 1786 - Trusted SRAM 1787 - Trusted DRAM (FVP only) 1788 - Secure region of DRAM (top 16MB of DRAM configured by the TrustZone 1789 controller) 1790 1791 When BL32 (for AArch64) is loaded into Trusted SRAM, it is loaded below 1792 BL31. 1793 1794The location of the BL32 image will result in different memory maps. This is 1795illustrated for both FVP and Juno in the following diagrams, using the TSP as 1796an example. 1797 1798.. note:: 1799 Loading the BL32 image in TZC secured DRAM doesn't change the memory 1800 layout of the other images in Trusted SRAM. 1801 1802CONFIG section in memory layouts shown below contains: 1803 1804:: 1805 1806 +--------------------+ 1807 |bl2_mem_params_descs| 1808 |--------------------| 1809 | fw_configs | 1810 +--------------------+ 1811 1812``bl2_mem_params_descs`` contains parameters passed from BL2 to next the 1813BL image during boot. 1814 1815``fw_configs`` includes soc_fw_config, tos_fw_config, tb_fw_config and fw_config. 1816 1817**FVP with TSP in Trusted SRAM with firmware configs :** 1818(These diagrams only cover the AArch64 case) 1819 1820:: 1821 1822 DRAM 1823 0xffffffff +----------+ 1824 | EL3 TZC | 1825 0xffe00000 |----------| (secure) 1826 | AP TZC | 1827 0xff000000 +----------+ 1828 : : 1829 0x82100000 |----------| 1830 |HW_CONFIG | 1831 0x82000000 |----------| (non-secure) 1832 | | 1833 0x80000000 +----------+ 1834 1835 Trusted DRAM 1836 0x08000000 +----------+ 1837 |HW_CONFIG | 1838 0x07f00000 |----------| 1839 : : 1840 | | 1841 0x06000000 +----------+ 1842 1843 Trusted SRAM 1844 0x04040000 +----------+ loaded by BL2 +----------------+ 1845 | BL1 (rw) | <<<<<<<<<<<<< | | 1846 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1847 | BL2 | <<<<<<<<<<<<< | | 1848 |----------| <<<<<<<<<<<<< |----------------| 1849 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1850 | | <<<<<<<<<<<<< |----------------| 1851 | | <<<<<<<<<<<<< | BL32 | 1852 0x04003000 +----------+ +----------------+ 1853 | CONFIG | 1854 0x04001000 +----------+ 1855 | Shared | 1856 0x04000000 +----------+ 1857 1858 Trusted ROM 1859 0x04000000 +----------+ 1860 | BL1 (ro) | 1861 0x00000000 +----------+ 1862 1863**FVP with TSP in Trusted DRAM with firmware configs (default option):** 1864 1865:: 1866 1867 DRAM 1868 0xffffffff +--------------+ 1869 | EL3 TZC | 1870 0xffe00000 |--------------| (secure) 1871 | AP TZC | 1872 0xff000000 +--------------+ 1873 : : 1874 0x82100000 |--------------| 1875 | HW_CONFIG | 1876 0x82000000 |--------------| (non-secure) 1877 | | 1878 0x80000000 +--------------+ 1879 1880 Trusted DRAM 1881 0x08000000 +--------------+ 1882 | HW_CONFIG | 1883 0x07f00000 |--------------| 1884 : : 1885 | BL32 | 1886 0x06000000 +--------------+ 1887 1888 Trusted SRAM 1889 0x04040000 +--------------+ loaded by BL2 +----------------+ 1890 | BL1 (rw) | <<<<<<<<<<<<< | | 1891 |--------------| <<<<<<<<<<<<< | BL31 NOBITS | 1892 | BL2 | <<<<<<<<<<<<< | | 1893 |--------------| <<<<<<<<<<<<< |----------------| 1894 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1895 | | +----------------+ 1896 0x04003000 +--------------+ 1897 | CONFIG | 1898 0x04001000 +--------------+ 1899 | Shared | 1900 0x04000000 +--------------+ 1901 1902 Trusted ROM 1903 0x04000000 +--------------+ 1904 | BL1 (ro) | 1905 0x00000000 +--------------+ 1906 1907**FVP with TSP in TZC-Secured DRAM with firmware configs :** 1908 1909:: 1910 1911 DRAM 1912 0xffffffff +----------+ 1913 | EL3 TZC | 1914 0xffe00000 |----------| (secure) 1915 | AP TZC | 1916 | (BL32) | 1917 0xff000000 +----------+ 1918 | | 1919 0x82100000 |----------| 1920 |HW_CONFIG | 1921 0x82000000 |----------| (non-secure) 1922 | | 1923 0x80000000 +----------+ 1924 1925 Trusted DRAM 1926 0x08000000 +----------+ 1927 |HW_CONFIG | 1928 0x7f000000 |----------| 1929 : : 1930 | | 1931 0x06000000 +----------+ 1932 1933 Trusted SRAM 1934 0x04040000 +----------+ loaded by BL2 +----------------+ 1935 | BL1 (rw) | <<<<<<<<<<<<< | | 1936 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1937 | BL2 | <<<<<<<<<<<<< | | 1938 |----------| <<<<<<<<<<<<< |----------------| 1939 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1940 | | +----------------+ 1941 0x04003000 +----------+ 1942 | CONFIG | 1943 0x04001000 +----------+ 1944 | Shared | 1945 0x04000000 +----------+ 1946 1947 Trusted ROM 1948 0x04000000 +----------+ 1949 | BL1 (ro) | 1950 0x00000000 +----------+ 1951 1952**Juno with BL32 in Trusted SRAM :** 1953 1954:: 1955 1956 DRAM 1957 0xFFFFFFFF +----------+ 1958 | SCP TZC | 1959 0xFFE00000 |----------| 1960 | EL3 TZC | 1961 0xFFC00000 |----------| (secure) 1962 | AP TZC | 1963 0xFF000000 +----------+ 1964 | | 1965 : : (non-secure) 1966 | | 1967 0x80000000 +----------+ 1968 1969 1970 Flash0 1971 0x0C000000 +----------+ 1972 : : 1973 0x0BED0000 |----------| 1974 | BL1 (ro) | 1975 0x0BEC0000 |----------| 1976 : : 1977 0x08000000 +----------+ BL31 is loaded 1978 after SCP_BL2 has 1979 Trusted SRAM been sent to SCP 1980 0x04040000 +----------+ loaded by BL2 +----------------+ 1981 | BL1 (rw) | <<<<<<<<<<<<< | | 1982 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1983 | BL2 | <<<<<<<<<<<<< | | 1984 |----------| <<<<<<<<<<<<< |----------------| 1985 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 1986 | | <<<<<<<<<<<<< |----------------| 1987 | | <<<<<<<<<<<<< | BL32 | 1988 | | +----------------+ 1989 | | 1990 0x04001000 +----------+ 1991 | MHU | 1992 0x04000000 +----------+ 1993 1994**Juno with BL32 in TZC-secured DRAM :** 1995 1996:: 1997 1998 DRAM 1999 0xFFFFFFFF +----------+ 2000 | SCP TZC | 2001 0xFFE00000 |----------| 2002 | EL3 TZC | 2003 0xFFC00000 |----------| (secure) 2004 | AP TZC | 2005 | (BL32) | 2006 0xFF000000 +----------+ 2007 | | 2008 : : (non-secure) 2009 | | 2010 0x80000000 +----------+ 2011 2012 Flash0 2013 0x0C000000 +----------+ 2014 : : 2015 0x0BED0000 |----------| 2016 | BL1 (ro) | 2017 0x0BEC0000 |----------| 2018 : : 2019 0x08000000 +----------+ BL31 is loaded 2020 after SCP_BL2 has 2021 Trusted SRAM been sent to SCP 2022 0x04040000 +----------+ loaded by BL2 +----------------+ 2023 | BL1 (rw) | <<<<<<<<<<<<< | | 2024 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 2025 | BL2 | <<<<<<<<<<<<< | | 2026 |----------| <<<<<<<<<<<<< |----------------| 2027 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 2028 | | +----------------+ 2029 0x04001000 +----------+ 2030 | MHU | 2031 0x04000000 +----------+ 2032 2033.. _firmware_design_fip: 2034 2035Firmware Image Package (FIP) 2036---------------------------- 2037 2038Using a Firmware Image Package (FIP) allows for packing bootloader images (and 2039potentially other payloads) into a single archive that can be loaded by TF-A 2040from non-volatile platform storage. A driver to load images from a FIP has 2041been added to the storage layer and allows a package to be read from supported 2042platform storage. A tool to create Firmware Image Packages is also provided 2043and described below. 2044 2045Firmware Image Package layout 2046~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2047 2048The FIP layout consists of a table of contents (ToC) followed by payload data. 2049The ToC itself has a header followed by one or more table entries. The ToC is 2050terminated by an end marker entry, and since the size of the ToC is 0 bytes, 2051the offset equals the total size of the FIP file. All ToC entries describe some 2052payload data that has been appended to the end of the binary package. With the 2053information provided in the ToC entry the corresponding payload data can be 2054retrieved. 2055 2056:: 2057 2058 ------------------ 2059 | ToC Header | 2060 |----------------| 2061 | ToC Entry 0 | 2062 |----------------| 2063 | ToC Entry 1 | 2064 |----------------| 2065 | ToC End Marker | 2066 |----------------| 2067 | | 2068 | Data 0 | 2069 | | 2070 |----------------| 2071 | | 2072 | Data 1 | 2073 | | 2074 ------------------ 2075 2076The ToC header and entry formats are described in the header file 2077``include/tools_share/firmware_image_package.h``. This file is used by both the 2078tool and TF-A. 2079 2080The ToC header has the following fields: 2081 2082:: 2083 2084 `name`: The name of the ToC. This is currently used to validate the header. 2085 `serial_number`: A non-zero number provided by the creation tool 2086 `flags`: Flags associated with this data. 2087 Bits 0-31: Reserved 2088 Bits 32-47: Platform defined 2089 Bits 48-63: Reserved 2090 2091A ToC entry has the following fields: 2092 2093:: 2094 2095 `uuid`: All files are referred to by a pre-defined Universally Unique 2096 IDentifier [UUID] . The UUIDs are defined in 2097 `include/tools_share/firmware_image_package.h`. The platform translates 2098 the requested image name into the corresponding UUID when accessing the 2099 package. 2100 `offset_address`: The offset address at which the corresponding payload data 2101 can be found. The offset is calculated from the ToC base address. 2102 `size`: The size of the corresponding payload data in bytes. 2103 `flags`: Flags associated with this entry. None are yet defined. 2104 2105Firmware Image Package creation tool 2106~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2107 2108The FIP creation tool can be used to pack specified images into a binary 2109package that can be loaded by TF-A from platform storage. The tool currently 2110only supports packing bootloader images. Additional image definitions can be 2111added to the tool as required. 2112 2113The tool can be found in ``tools/fiptool``. 2114 2115Loading from a Firmware Image Package (FIP) 2116~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2117 2118The Firmware Image Package (FIP) driver can load images from a binary package on 2119non-volatile platform storage. For the Arm development platforms, this is 2120currently NOR FLASH. 2121 2122Bootloader images are loaded according to the platform policy as specified by 2123the function ``plat_get_image_source()``. For the Arm development platforms, this 2124means the platform will attempt to load images from a Firmware Image Package 2125located at the start of NOR FLASH0. 2126 2127The Arm development platforms' policy is to only allow loading of a known set of 2128images. The platform policy can be modified to allow additional images. 2129 2130Use of coherent memory in TF-A 2131------------------------------ 2132 2133There might be loss of coherency when physical memory with mismatched 2134shareability, cacheability and memory attributes is accessed by multiple CPUs 2135(refer to section B2.9 of `Arm ARM`_ for more details). This possibility occurs 2136in TF-A during power up/down sequences when coherency, MMU and caches are 2137turned on/off incrementally. 2138 2139TF-A defines coherent memory as a region of memory with Device nGnRE attributes 2140in the translation tables. The translation granule size in TF-A is 4KB. This 2141is the smallest possible size of the coherent memory region. 2142 2143By default, all data structures which are susceptible to accesses with 2144mismatched attributes from various CPUs are allocated in a coherent memory 2145region (refer to section 2.1 of :ref:`Porting Guide`). The coherent memory 2146region accesses are Outer Shareable, non-cacheable and they can be accessed with 2147the Device nGnRE attributes when the MMU is turned on. Hence, at the expense of 2148at least an extra page of memory, TF-A is able to work around coherency issues 2149due to mismatched memory attributes. 2150 2151The alternative to the above approach is to allocate the susceptible data 2152structures in Normal WriteBack WriteAllocate Inner shareable memory. This 2153approach requires the data structures to be designed so that it is possible to 2154work around the issue of mismatched memory attributes by performing software 2155cache maintenance on them. 2156 2157Disabling the use of coherent memory in TF-A 2158~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2159 2160It might be desirable to avoid the cost of allocating coherent memory on 2161platforms which are memory constrained. TF-A enables inclusion of coherent 2162memory in firmware images through the build flag ``USE_COHERENT_MEM``. 2163This flag is enabled by default. It can be disabled to choose the second 2164approach described above. 2165 2166The below sections analyze the data structures allocated in the coherent memory 2167region and the changes required to allocate them in normal memory. 2168 2169Coherent memory usage in PSCI implementation 2170~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2171 2172The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain 2173tree information for state management of power domains. By default, this data 2174structure is allocated in the coherent memory region in TF-A because it can be 2175accessed by multiple CPUs, either with caches enabled or disabled. 2176 2177.. code:: c 2178 2179 typedef struct non_cpu_pwr_domain_node { 2180 /* 2181 * Index of the first CPU power domain node level 0 which has this node 2182 * as its parent. 2183 */ 2184 unsigned int cpu_start_idx; 2185 2186 /* 2187 * Number of CPU power domains which are siblings of the domain indexed 2188 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx 2189 * -> cpu_start_idx + ncpus' have this node as their parent. 2190 */ 2191 unsigned int ncpus; 2192 2193 /* 2194 * Index of the parent power domain node. 2195 */ 2196 unsigned int parent_node; 2197 2198 plat_local_state_t local_state; 2199 2200 unsigned char level; 2201 2202 /* For indexing the psci_lock array*/ 2203 unsigned char lock_index; 2204 } non_cpu_pd_node_t; 2205 2206In order to move this data structure to normal memory, the use of each of its 2207fields must be analyzed. Fields like ``cpu_start_idx``, ``ncpus``, ``parent_node`` 2208``level`` and ``lock_index`` are only written once during cold boot. Hence removing 2209them from coherent memory involves only doing a clean and invalidate of the 2210cache lines after these fields are written. 2211 2212The field ``local_state`` can be concurrently accessed by multiple CPUs in 2213different cache states. A Lamport's Bakery lock ``psci_locks`` is used to ensure 2214mutual exclusion to this field and a clean and invalidate is needed after it 2215is written. 2216 2217Bakery lock data 2218~~~~~~~~~~~~~~~~ 2219 2220The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory 2221and is accessed by multiple CPUs with mismatched attributes. ``bakery_lock_t`` is 2222defined as follows: 2223 2224.. code:: c 2225 2226 typedef struct bakery_lock { 2227 /* 2228 * The lock_data is a bit-field of 2 members: 2229 * Bit[0] : choosing. This field is set when the CPU is 2230 * choosing its bakery number. 2231 * Bits[1 - 15] : number. This is the bakery number allocated. 2232 */ 2233 volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS]; 2234 } bakery_lock_t; 2235 2236It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU 2237fields can be read by all CPUs but only written to by the owning CPU. 2238 2239Depending upon the data cache line size, the per-CPU fields of the 2240``bakery_lock_t`` structure for multiple CPUs may exist on a single cache line. 2241These per-CPU fields can be read and written during lock contention by multiple 2242CPUs with mismatched memory attributes. Since these fields are a part of the 2243lock implementation, they do not have access to any other locking primitive to 2244safeguard against the resulting coherency issues. As a result, simple software 2245cache maintenance is not enough to allocate them in coherent memory. Consider 2246the following example. 2247 2248CPU0 updates its per-CPU field with data cache enabled. This write updates a 2249local cache line which contains a copy of the fields for other CPUs as well. Now 2250CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache 2251disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of 2252its field in any other cache line in the system. This operation will invalidate 2253the update made by CPU0 as well. 2254 2255To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure 2256has been redesigned. The changes utilise the characteristic of Lamport's Bakery 2257algorithm mentioned earlier. The bakery_lock structure only allocates the memory 2258for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks 2259needed for a CPU into a section ``.bakery_lock``. The linker allocates the memory 2260for other cores by using the total size allocated for the bakery_lock section 2261and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to 2262perform software cache maintenance on the lock data structure without running 2263into coherency issues associated with mismatched attributes. 2264 2265The bakery lock data structure ``bakery_info_t`` is defined for use when 2266``USE_COHERENT_MEM`` is disabled as follows: 2267 2268.. code:: c 2269 2270 typedef struct bakery_info { 2271 /* 2272 * The lock_data is a bit-field of 2 members: 2273 * Bit[0] : choosing. This field is set when the CPU is 2274 * choosing its bakery number. 2275 * Bits[1 - 15] : number. This is the bakery number allocated. 2276 */ 2277 volatile uint16_t lock_data; 2278 } bakery_info_t; 2279 2280The ``bakery_info_t`` represents a single per-CPU field of one lock and 2281the combination of corresponding ``bakery_info_t`` structures for all CPUs in the 2282system represents the complete bakery lock. The view in memory for a system 2283with n bakery locks are: 2284 2285:: 2286 2287 .bakery_lock section start 2288 |----------------| 2289 | `bakery_info_t`| <-- Lock_0 per-CPU field 2290 | Lock_0 | for CPU0 2291 |----------------| 2292 | `bakery_info_t`| <-- Lock_1 per-CPU field 2293 | Lock_1 | for CPU0 2294 |----------------| 2295 | .... | 2296 |----------------| 2297 | `bakery_info_t`| <-- Lock_N per-CPU field 2298 | Lock_N | for CPU0 2299 ------------------ 2300 | XXXXX | 2301 | Padding to | 2302 | next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate 2303 | Granule | continuous memory for remaining CPUs. 2304 ------------------ 2305 | `bakery_info_t`| <-- Lock_0 per-CPU field 2306 | Lock_0 | for CPU1 2307 |----------------| 2308 | `bakery_info_t`| <-- Lock_1 per-CPU field 2309 | Lock_1 | for CPU1 2310 |----------------| 2311 | .... | 2312 |----------------| 2313 | `bakery_info_t`| <-- Lock_N per-CPU field 2314 | Lock_N | for CPU1 2315 ------------------ 2316 | XXXXX | 2317 | Padding to | 2318 | next Cache WB | 2319 | Granule | 2320 ------------------ 2321 2322Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an 2323operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1 2324``.bakery_lock`` section need to be fetched and appropriate cache operations need 2325to be performed for each access. 2326 2327On Arm Platforms, bakery locks are used in psci (``psci_locks``) and power controller 2328driver (``arm_lock``). 2329 2330Non Functional Impact of removing coherent memory 2331~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2332 2333Removal of the coherent memory region leads to the additional software overhead 2334of performing cache maintenance for the affected data structures. However, since 2335the memory where the data structures are allocated is cacheable, the overhead is 2336mostly mitigated by an increase in performance. 2337 2338There is however a performance impact for bakery locks, due to: 2339 2340- Additional cache maintenance operations, and 2341- Multiple cache line reads for each lock operation, since the bakery locks 2342 for each CPU are distributed across different cache lines. 2343 2344The implementation has been optimized to minimize this additional overhead. 2345Measurements indicate that when bakery locks are allocated in Normal memory, the 2346minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas 2347in Device memory the same is 2 micro seconds. The measurements were done on the 2348Juno Arm development platform. 2349 2350As mentioned earlier, almost a page of memory can be saved by disabling 2351``USE_COHERENT_MEM``. Each platform needs to consider these trade-offs to decide 2352whether coherent memory should be used. If a platform disables 2353``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can 2354optionally define macro ``PLAT_PERCPU_BAKERY_LOCK_SIZE`` (see the 2355:ref:`Porting Guide`). Refer to the reference platform code for examples. 2356 2357Isolating code and read-only data on separate memory pages 2358---------------------------------------------------------- 2359 2360In the Armv8-A VMSA, translation table entries include fields that define the 2361properties of the target memory region, such as its access permissions. The 2362smallest unit of memory that can be addressed by a translation table entry is 2363a memory page. Therefore, if software needs to set different permissions on two 2364memory regions then it needs to map them using different memory pages. 2365 2366The default memory layout for each BL image is as follows: 2367 2368:: 2369 2370 | ... | 2371 +-------------------+ 2372 | Read-write data | 2373 +-------------------+ Page boundary 2374 | <Padding> | 2375 +-------------------+ 2376 | Exception vectors | 2377 +-------------------+ 2 KB boundary 2378 | <Padding> | 2379 +-------------------+ 2380 | Read-only data | 2381 +-------------------+ 2382 | Code | 2383 +-------------------+ BLx_BASE 2384 2385.. note:: 2386 The 2KB alignment for the exception vectors is an architectural 2387 requirement. 2388 2389The read-write data start on a new memory page so that they can be mapped with 2390read-write permissions, whereas the code and read-only data below are configured 2391as read-only. 2392 2393However, the read-only data are not aligned on a page boundary. They are 2394contiguous to the code. Therefore, the end of the code section and the beginning 2395of the read-only data one might share a memory page. This forces both to be 2396mapped with the same memory attributes. As the code needs to be executable, this 2397means that the read-only data stored on the same memory page as the code are 2398executable as well. This could potentially be exploited as part of a security 2399attack. 2400 2401TF provides the build flag ``SEPARATE_CODE_AND_RODATA`` to isolate the code and 2402read-only data on separate memory pages. This in turn allows independent control 2403of the access permissions for the code and read-only data. In this case, 2404platform code gets a finer-grained view of the image layout and can 2405appropriately map the code region as executable and the read-only data as 2406execute-never. 2407 2408This has an impact on memory footprint, as padding bytes need to be introduced 2409between the code and read-only data to ensure the segregation of the two. To 2410limit the memory cost, this flag also changes the memory layout such that the 2411code and exception vectors are now contiguous, like so: 2412 2413:: 2414 2415 | ... | 2416 +-------------------+ 2417 | Read-write data | 2418 +-------------------+ Page boundary 2419 | <Padding> | 2420 +-------------------+ 2421 | Read-only data | 2422 +-------------------+ Page boundary 2423 | <Padding> | 2424 +-------------------+ 2425 | Exception vectors | 2426 +-------------------+ 2 KB boundary 2427 | <Padding> | 2428 +-------------------+ 2429 | Code | 2430 +-------------------+ BLx_BASE 2431 2432With this more condensed memory layout, the separation of read-only data will 2433add zero or one page to the memory footprint of each BL image. Each platform 2434should consider the trade-off between memory footprint and security. 2435 2436This build flag is disabled by default, minimising memory footprint. On Arm 2437platforms, it is enabled. 2438 2439Publish and Subscribe Framework 2440------------------------------- 2441 2442The Publish and Subscribe Framework allows EL3 components to define and publish 2443events, to which other EL3 components can subscribe. 2444 2445The following macros are provided by the framework: 2446 2447- ``REGISTER_PUBSUB_EVENT(event)``: Defines an event, and takes one argument, 2448 the event name, which must be a valid C identifier. All calls to 2449 ``REGISTER_PUBSUB_EVENT`` macro must be placed in the file 2450 ``pubsub_events.h``. 2451 2452- ``PUBLISH_EVENT_ARG(event, arg)``: Publishes a defined event, by iterating 2453 subscribed handlers and calling them in turn. The handlers will be passed the 2454 parameter ``arg``. The expected use-case is to broadcast an event. 2455 2456- ``PUBLISH_EVENT(event)``: Like ``PUBLISH_EVENT_ARG``, except that the value 2457 ``NULL`` is passed to subscribed handlers. 2458 2459- ``SUBSCRIBE_TO_EVENT(event, handler)``: Registers the ``handler`` to 2460 subscribe to ``event``. The handler will be executed whenever the ``event`` 2461 is published. 2462 2463- ``for_each_subscriber(event, subscriber)``: Iterates through all handlers 2464 subscribed for ``event``. ``subscriber`` must be a local variable of type 2465 ``pubsub_cb_t *``, and will point to each subscribed handler in turn during 2466 iteration. This macro can be used for those patterns that none of the 2467 ``PUBLISH_EVENT_*()`` macros cover. 2468 2469Publishing an event that wasn't defined using ``REGISTER_PUBSUB_EVENT`` will 2470result in build error. Subscribing to an undefined event however won't. 2471 2472Subscribed handlers must be of type ``pubsub_cb_t``, with following function 2473signature: 2474 2475.. code:: c 2476 2477 typedef void* (*pubsub_cb_t)(const void *arg); 2478 2479There may be arbitrary number of handlers registered to the same event. The 2480order in which subscribed handlers are notified when that event is published is 2481not defined. Subscribed handlers may be executed in any order; handlers should 2482not assume any relative ordering amongst them. 2483 2484Publishing an event on a PE will result in subscribed handlers executing on that 2485PE only; it won't cause handlers to execute on a different PE. 2486 2487Note that publishing an event on a PE blocks until all the subscribed handlers 2488finish executing on the PE. 2489 2490TF-A generic code publishes and subscribes to some events within. Platform 2491ports are discouraged from subscribing to them. These events may be withdrawn, 2492renamed, or have their semantics altered in the future. Platforms may however 2493register, publish, and subscribe to platform-specific events. 2494 2495Publish and Subscribe Example 2496~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2497 2498A publisher that wants to publish event ``foo`` would: 2499 2500- Define the event ``foo`` in the ``pubsub_events.h``. 2501 2502 .. code:: c 2503 2504 REGISTER_PUBSUB_EVENT(foo); 2505 2506- Depending on the nature of event, use one of ``PUBLISH_EVENT_*()`` macros to 2507 publish the event at the appropriate path and time of execution. 2508 2509A subscriber that wants to subscribe to event ``foo`` published above would 2510implement: 2511 2512.. code:: c 2513 2514 void *foo_handler(const void *arg) 2515 { 2516 void *result; 2517 2518 /* Do handling ... */ 2519 2520 return result; 2521 } 2522 2523 SUBSCRIBE_TO_EVENT(foo, foo_handler); 2524 2525 2526Reclaiming the BL31 initialization code 2527~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2528 2529A significant amount of the code used for the initialization of BL31 is never 2530needed again after boot time. In order to reduce the runtime memory 2531footprint, the memory used for this code can be reclaimed after initialization 2532has finished and be used for runtime data. 2533 2534The build option ``RECLAIM_INIT_CODE`` can be set to mark this boot time code 2535with a ``.text.init.*`` attribute which can be filtered and placed suitably 2536within the BL image for later reclamation by the platform. The platform can 2537specify the filter and the memory region for this init section in BL31 via the 2538plat.ld.S linker script. For example, on the FVP, this section is placed 2539overlapping the secondary CPU stacks so that after the cold boot is done, this 2540memory can be reclaimed for the stacks. The init memory section is initially 2541mapped with ``RO``, ``EXECUTE`` attributes. After BL31 initialization has 2542completed, the FVP changes the attributes of this section to ``RW``, 2543``EXECUTE_NEVER`` allowing it to be used for runtime data. The memory attributes 2544are changed within the ``bl31_plat_runtime_setup`` platform hook. The init 2545section section can be reclaimed for any data which is accessed after cold 2546boot initialization and it is upto the platform to make the decision. 2547 2548.. _firmware_design_pmf: 2549 2550Performance Measurement Framework 2551--------------------------------- 2552 2553The Performance Measurement Framework (PMF) facilitates collection of 2554timestamps by registered services and provides interfaces to retrieve them 2555from within TF-A. A platform can choose to expose appropriate SMCs to 2556retrieve these collected timestamps. 2557 2558By default, the global physical counter is used for the timestamp 2559value and is read via ``CNTPCT_EL0``. The framework allows to retrieve 2560timestamps captured by other CPUs. 2561 2562Timestamp identifier format 2563~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2564 2565A PMF timestamp is uniquely identified across the system via the 2566timestamp ID or ``tid``. The ``tid`` is composed as follows: 2567 2568:: 2569 2570 Bits 0-7: The local timestamp identifier. 2571 Bits 8-9: Reserved. 2572 Bits 10-15: The service identifier. 2573 Bits 16-31: Reserved. 2574 2575#. The service identifier. Each PMF service is identified by a 2576 service name and a service identifier. Both the service name and 2577 identifier are unique within the system as a whole. 2578 2579#. The local timestamp identifier. This identifier is unique within a given 2580 service. 2581 2582Registering a PMF service 2583~~~~~~~~~~~~~~~~~~~~~~~~~ 2584 2585To register a PMF service, the ``PMF_REGISTER_SERVICE()`` macro from ``pmf.h`` 2586is used. The arguments required are the service name, the service ID, 2587the total number of local timestamps to be captured and a set of flags. 2588 2589The ``flags`` field can be specified as a bitwise-OR of the following values: 2590 2591:: 2592 2593 PMF_STORE_ENABLE: The timestamp is stored in memory for later retrieval. 2594 PMF_DUMP_ENABLE: The timestamp is dumped on the serial console. 2595 2596The ``PMF_REGISTER_SERVICE()`` reserves memory to store captured 2597timestamps in a PMF specific linker section at build time. 2598Additionally, it defines necessary functions to capture and 2599retrieve a particular timestamp for the given service at runtime. 2600 2601The macro ``PMF_REGISTER_SERVICE()`` only enables capturing PMF timestamps 2602from within TF-A. In order to retrieve timestamps from outside of TF-A, the 2603``PMF_REGISTER_SERVICE_SMC()`` macro must be used instead. This macro 2604accepts the same set of arguments as the ``PMF_REGISTER_SERVICE()`` 2605macro but additionally supports retrieving timestamps using SMCs. 2606 2607Capturing a timestamp 2608~~~~~~~~~~~~~~~~~~~~~ 2609 2610PMF timestamps are stored in a per-service timestamp region. On a 2611system with multiple CPUs, each timestamp is captured and stored 2612in a per-CPU cache line aligned memory region. 2613 2614Having registered the service, the ``PMF_CAPTURE_TIMESTAMP()`` macro can be 2615used to capture a timestamp at the location where it is used. The macro 2616takes the service name, a local timestamp identifier and a flag as arguments. 2617 2618The ``flags`` field argument can be zero, or ``PMF_CACHE_MAINT`` which 2619instructs PMF to do cache maintenance following the capture. Cache 2620maintenance is required if any of the service's timestamps are captured 2621with data cache disabled. 2622 2623To capture a timestamp in assembly code, the caller should use 2624``pmf_calc_timestamp_addr`` macro (defined in ``pmf_asm_macros.S``) to 2625calculate the address of where the timestamp would be stored. The 2626caller should then read ``CNTPCT_EL0`` register to obtain the timestamp 2627and store it at the determined address for later retrieval. 2628 2629Retrieving a timestamp 2630~~~~~~~~~~~~~~~~~~~~~~ 2631 2632From within TF-A, timestamps for individual CPUs can be retrieved using either 2633``PMF_GET_TIMESTAMP_BY_MPIDR()`` or ``PMF_GET_TIMESTAMP_BY_INDEX()`` macros. 2634These macros accept the CPU's MPIDR value, or its ordinal position 2635respectively. 2636 2637From outside TF-A, timestamps for individual CPUs can be retrieved by calling 2638into ``pmf_smc_handler()``. 2639 2640:: 2641 2642 Interface : pmf_smc_handler() 2643 Argument : unsigned int smc_fid, u_register_t x1, 2644 u_register_t x2, u_register_t x3, 2645 u_register_t x4, void *cookie, 2646 void *handle, u_register_t flags 2647 Return : uintptr_t 2648 2649 smc_fid: Holds the SMC identifier which is either `PMF_SMC_GET_TIMESTAMP_32` 2650 when the caller of the SMC is running in AArch32 mode 2651 or `PMF_SMC_GET_TIMESTAMP_64` when the caller is running in AArch64 mode. 2652 x1: Timestamp identifier. 2653 x2: The `mpidr` of the CPU for which the timestamp has to be retrieved. 2654 This can be the `mpidr` of a different core to the one initiating 2655 the SMC. In that case, service specific cache maintenance may be 2656 required to ensure the updated copy of the timestamp is returned. 2657 x3: A flags value that is either 0 or `PMF_CACHE_MAINT`. If 2658 `PMF_CACHE_MAINT` is passed, then the PMF code will perform a 2659 cache invalidate before reading the timestamp. This ensures 2660 an updated copy is returned. 2661 2662The remaining arguments, ``x4``, ``cookie``, ``handle`` and ``flags`` are unused 2663in this implementation. 2664 2665PMF code structure 2666~~~~~~~~~~~~~~~~~~ 2667 2668#. ``pmf_main.c`` consists of core functions that implement service registration, 2669 initialization, storing, dumping and retrieving timestamps. 2670 2671#. ``pmf_smc.c`` contains the SMC handling for registered PMF services. 2672 2673#. ``pmf.h`` contains the public interface to Performance Measurement Framework. 2674 2675#. ``pmf_asm_macros.S`` consists of macros to facilitate capturing timestamps in 2676 assembly code. 2677 2678#. ``pmf_helpers.h`` is an internal header used by ``pmf.h``. 2679 2680Armv8-A Architecture Extensions 2681------------------------------- 2682 2683TF-A makes use of Armv8-A Architecture Extensions where applicable. This 2684section lists the usage of Architecture Extensions, and build flags 2685controlling them. 2686 2687Build options 2688~~~~~~~~~~~~~ 2689 2690``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` 2691 2692These build options serve dual purpose 2693 2694- Determine the architecture extension support in TF-A build: All the mandatory 2695 architectural features up to ``ARM_ARCH_MAJOR.ARM_ARCH_MINOR`` are included 2696 and unconditionally enabled by TF-A build system. 2697 2698- ``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` are passed to a march.mk build utility 2699 this will try to come up with an appropriate -march value to be passed to compiler 2700 by probing the compiler and checking what's supported by the compiler and what's best 2701 that can be used. But if platform provides a ``MARCH_DIRECTIVE`` then it will used 2702 directly and compiler probing will be skipped. 2703 2704The build system requires that the platform provides a valid numeric value based on 2705CPU architecture extension, otherwise it defaults to base Armv8.0-A architecture. 2706Subsequent Arm Architecture versions also support extensions which were introduced 2707in previous versions. 2708 2709.. seealso:: :ref:`Build Options` 2710 2711For details on the Architecture Extension and available features, please refer 2712to the respective Architecture Extension Supplement. 2713 2714Armv8.1-A 2715~~~~~~~~~ 2716 2717This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when 2718``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` >= 1. 2719 2720- By default, a load-/store-exclusive instruction pair is used to implement 2721 spinlocks. The ``USE_SPINLOCK_CAS`` build option when set to 1 selects the 2722 spinlock implementation using the ARMv8.1-LSE Compare and Swap instruction. 2723 Notice this instruction is only available in AArch64 execution state, so 2724 the option is only available to AArch64 builds. 2725 2726Armv8.2-A 2727~~~~~~~~~ 2728 2729- The presence of ARMv8.2-TTCNP is detected at runtime. When it is present, the 2730 Common not Private (TTBRn_ELx.CnP) bit is enabled to indicate that multiple 2731 Processing Elements in the same Inner Shareable domain use the same 2732 translation table entries for a given stage of translation for a particular 2733 translation regime. 2734 2735Armv8.3-A 2736~~~~~~~~~ 2737 2738- Pointer authentication features of Armv8.3-A are unconditionally enabled in 2739 the Non-secure world so that lower ELs are allowed to use them without 2740 causing a trap to EL3. 2741 2742 In order to enable the Secure world to use it, ``CTX_INCLUDE_PAUTH_REGS`` 2743 must be set to 1. This will add all pointer authentication system registers 2744 to the context that is saved when doing a world switch. 2745 2746 The TF-A itself has support for pointer authentication at runtime 2747 that can be enabled by setting ``BRANCH_PROTECTION`` option to non-zero and 2748 ``CTX_INCLUDE_PAUTH_REGS`` to 1. This enables pointer authentication in BL1, 2749 BL2, BL31, and the TSP if it is used. 2750 2751 Note that Pointer Authentication is enabled for Non-secure world irrespective 2752 of the value of these build flags if the CPU supports it. 2753 2754 If ``ARM_ARCH_MAJOR == 8`` and ``ARM_ARCH_MINOR >= 3`` the code footprint of 2755 enabling PAuth is lower because the compiler will use the optimized 2756 PAuth instructions rather than the backwards-compatible ones. 2757 2758Armv8.5-A 2759~~~~~~~~~ 2760 2761- Branch Target Identification feature is selected by ``BRANCH_PROTECTION`` 2762 option set to 1. This option defaults to 0. 2763 2764- Memory Tagging Extension feature is unconditionally enabled for both worlds 2765 (at EL0 and S-EL0) if it is only supported at EL0. If instead it is 2766 implemented at all ELs, it is unconditionally enabled for only the normal 2767 world. To enable it for the secure world as well, the build option 2768 ``CTX_INCLUDE_MTE_REGS`` is required. If the hardware does not implement 2769 MTE support at all, it is always disabled, no matter what build options 2770 are used. 2771 2772Armv7-A 2773~~~~~~~ 2774 2775This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 7. 2776 2777There are several Armv7-A extensions available. Obviously the TrustZone 2778extension is mandatory to support the TF-A bootloader and runtime services. 2779 2780Platform implementing an Armv7-A system can to define from its target 2781Cortex-A architecture through ``ARM_CORTEX_A<X> = yes`` in their 2782``platform.mk`` script. For example ``ARM_CORTEX_A15=yes`` for a 2783Cortex-A15 target. 2784 2785Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support. 2786Note that using neon at runtime has constraints on non secure world context. 2787TF-A does not yet provide VFP context management. 2788 2789Directive ``ARM_CORTEX_A<x>`` and ``ARM_WITH_NEON`` are used to set 2790the toolchain target architecture directive. 2791 2792Platform may choose to not define straight the toolchain target architecture 2793directive by defining ``MARCH_DIRECTIVE``. 2794I.e: 2795 2796.. code:: make 2797 2798 MARCH_DIRECTIVE := -march=armv7-a 2799 2800Code Structure 2801-------------- 2802 2803TF-A code is logically divided between the three boot loader stages mentioned 2804in the previous sections. The code is also divided into the following 2805categories (present as directories in the source code): 2806 2807- **Platform specific.** Choice of architecture specific code depends upon 2808 the platform. 2809- **Common code.** This is platform and architecture agnostic code. 2810- **Library code.** This code comprises of functionality commonly used by all 2811 other code. The PSCI implementation and other EL3 runtime frameworks reside 2812 as Library components. 2813- **Stage specific.** Code specific to a boot stage. 2814- **Drivers.** 2815- **Services.** EL3 runtime services (eg: SPD). Specific SPD services 2816 reside in the ``services/spd`` directory (e.g. ``services/spd/tspd``). 2817 2818Each boot loader stage uses code from one or more of the above mentioned 2819categories. Based upon the above, the code layout looks like this: 2820 2821:: 2822 2823 Directory Used by BL1? Used by BL2? Used by BL31? 2824 bl1 Yes No No 2825 bl2 No Yes No 2826 bl31 No No Yes 2827 plat Yes Yes Yes 2828 drivers Yes No Yes 2829 common Yes Yes Yes 2830 lib Yes Yes Yes 2831 services No No Yes 2832 2833The build system provides a non configurable build option IMAGE_BLx for each 2834boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE_BL1 will be 2835defined by the build system. This enables TF-A to compile certain code only 2836for specific boot loader stages 2837 2838All assembler files have the ``.S`` extension. The linker source files for each 2839boot stage have the extension ``.ld.S``. These are processed by GCC to create the 2840linker scripts which have the extension ``.ld``. 2841 2842FDTs provide a description of the hardware platform and are used by the Linux 2843kernel at boot time. These can be found in the ``fdts`` directory. 2844 2845.. rubric:: References 2846 2847- `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D)`_ 2848 2849- `PSCI`_ 2850 2851- `SMC Calling Convention`_ 2852 2853- :ref:`Interrupt Management Framework` 2854 2855-------------- 2856 2857*Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.* 2858 2859.. _SMCCC: https://developer.arm.com/docs/den0028/latest 2860.. _PSCI: https://developer.arm.com/documentation/den0022/latest/ 2861.. _Arm ARM: https://developer.arm.com/docs/ddi0487/latest 2862.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest 2863.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a 2864.. _Arm Confidential Compute Architecture (Arm CCA): https://www.arm.com/why-arm/architecture/security-features/arm-confidential-compute-architecture 2865.. _AArch64 exception vector table: https://developer.arm.com/documentation/100933/0100/AArch64-exception-vector-table 2866 2867.. |Image 1| image:: ../resources/diagrams/rt-svc-descs-layout.png 2868
