1Firmware Design 2=============== 3 4Trusted Firmware-A (TF-A) implements a subset of the Trusted Board Boot 5Requirements (TBBR) Platform Design Document (PDD) for Arm reference 6platforms. 7 8The TBB sequence starts when the platform is powered on and runs up 9to the stage where it hands-off control to firmware running in the normal 10world in DRAM. This is the cold boot path. 11 12TF-A also implements the `Power State Coordination Interface PDD`_ as a 13runtime service. PSCI is the interface from normal world software to firmware 14implementing power management use-cases (for example, secondary CPU boot, 15hotplug and idle). Normal world software can access TF-A runtime services via 16the Arm SMC (Secure Monitor Call) instruction. The SMC instruction must be 17used as mandated by the SMC Calling Convention (`SMCCC`_). 18 19TF-A implements a framework for configuring and managing interrupts generated 20in either security state. The details of the interrupt management framework 21and its design can be found in :ref:`Interrupt Management Framework`. 22 23TF-A also implements a library for setting up and managing the translation 24tables. The details of this library can be found in 25:ref:`Translation (XLAT) Tables Library`. 26 27TF-A can be built to support either AArch64 or AArch32 execution state. 28 29Cold boot 30--------- 31 32The cold boot path starts when the platform is physically turned on. If 33``COLD_BOOT_SINGLE_CPU=0``, one of the CPUs released from reset is chosen as the 34primary CPU, and the remaining CPUs are considered secondary CPUs. The primary 35CPU is chosen through platform-specific means. The cold boot path is mainly 36executed by the primary CPU, other than essential CPU initialization executed by 37all CPUs. The secondary CPUs are kept in a safe platform-specific state until 38the primary CPU has performed enough initialization to boot them. 39 40Refer to the :ref:`CPU Reset` for more information on the effect of the 41``COLD_BOOT_SINGLE_CPU`` platform build option. 42 43The cold boot path in this implementation of TF-A depends on the execution 44state. For AArch64, it is divided into five steps (in order of execution): 45 46- Boot Loader stage 1 (BL1) *AP Trusted ROM* 47- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 48- Boot Loader stage 3-1 (BL31) *EL3 Runtime Software* 49- Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional) 50- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 51 52For AArch32, it is divided into four steps (in order of execution): 53 54- Boot Loader stage 1 (BL1) *AP Trusted ROM* 55- Boot Loader stage 2 (BL2) *Trusted Boot Firmware* 56- Boot Loader stage 3-2 (BL32) *EL3 Runtime Software* 57- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware* 58 59Arm development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a 60combination of the following types of memory regions. Each bootloader stage uses 61one or more of these memory regions. 62 63- Regions accessible from both non-secure and secure states. For example, 64 non-trusted SRAM, ROM and DRAM. 65- Regions accessible from only the secure state. For example, trusted SRAM and 66 ROM. The FVPs also implement the trusted DRAM which is statically 67 configured. Additionally, the Base FVPs and Juno development platform 68 configure the TrustZone Controller (TZC) to create a region in the DRAM 69 which is accessible only from the secure state. 70 71The sections below provide the following details: 72 73- dynamic configuration of Boot Loader stages 74- initialization and execution of the first three stages during cold boot 75- specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for 76 AArch32) entrypoint requirements for use by alternative Trusted Boot 77 Firmware in place of the provided BL1 and BL2 78 79Dynamic Configuration during cold boot 80~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 81 82Each of the Boot Loader stages may be dynamically configured if required by the 83platform. The Boot Loader stage may optionally specify a firmware 84configuration file and/or hardware configuration file as listed below: 85 86- FW_CONFIG - The firmware configuration file. Holds properties shared across 87 all BLx images. 88 An example is the "dtb-registry" node, which contains the information about 89 the other device tree configurations (load-address, size, image_id). 90- HW_CONFIG - The hardware configuration file. Can be shared by all Boot Loader 91 stages and also by the Normal World Rich OS. 92- TB_FW_CONFIG - Trusted Boot Firmware configuration file. Shared between BL1 93 and BL2. 94- SOC_FW_CONFIG - SoC Firmware configuration file. Used by BL31. 95- TOS_FW_CONFIG - Trusted OS Firmware configuration file. Used by Trusted OS 96 (BL32). 97- NT_FW_CONFIG - Non Trusted Firmware configuration file. Used by Non-trusted 98 firmware (BL33). 99 100The Arm development platforms use the Flattened Device Tree format for the 101dynamic configuration files. 102 103Each Boot Loader stage can pass up to 4 arguments via registers to the next 104stage. BL2 passes the list of the next images to execute to the *EL3 Runtime 105Software* (BL31 for AArch64 and BL32 for AArch32) via `arg0`. All the other 106arguments are platform defined. The Arm development platforms use the following 107convention: 108 109- BL1 passes the address of a meminfo_t structure to BL2 via ``arg1``. This 110 structure contains the memory layout available to BL2. 111- When dynamic configuration files are present, the firmware configuration for 112 the next Boot Loader stage is populated in the first available argument and 113 the generic hardware configuration is passed the next available argument. 114 For example, 115 116 - FW_CONFIG is loaded by BL1, then its address is passed in ``arg0`` to BL2. 117 - TB_FW_CONFIG address is retrieved by BL2 from FW_CONFIG device tree. 118 - If HW_CONFIG is loaded by BL1, then its address is passed in ``arg2`` to 119 BL2. Note, ``arg1`` is already used for meminfo_t. 120 - If SOC_FW_CONFIG is loaded by BL2, then its address is passed in ``arg1`` 121 to BL31. Note, ``arg0`` is used to pass the list of executable images. 122 - Similarly, if HW_CONFIG is loaded by BL1 or BL2, then its address is 123 passed in ``arg2`` to BL31. 124 - For other BL3x images, if the firmware configuration file is loaded by 125 BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded 126 then its address is passed in ``arg1``. 127 128BL1 129~~~ 130 131This stage begins execution from the platform's reset vector at EL3. The reset 132address is platform dependent but it is usually located in a Trusted ROM area. 133The BL1 data section is copied to trusted SRAM at runtime. 134 135On the Arm development platforms, BL1 code starts execution from the reset 136vector defined by the constant ``BL1_RO_BASE``. The BL1 data section is copied 137to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``. 138 139The functionality implemented by this stage is as follows. 140 141Determination of boot path 142^^^^^^^^^^^^^^^^^^^^^^^^^^ 143 144Whenever a CPU is released from reset, BL1 needs to distinguish between a warm 145boot and a cold boot. This is done using platform-specific mechanisms (see the 146``plat_get_my_entrypoint()`` function in the :ref:`Porting Guide`). In the case 147of a warm boot, a CPU is expected to continue execution from a separate 148entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe 149platform-specific state (see the ``plat_secondary_cold_boot_setup()`` function in 150the :ref:`Porting Guide`) while the primary CPU executes the remaining cold boot 151path as described in the following sections. 152 153This step only applies when ``PROGRAMMABLE_RESET_ADDRESS=0``. Refer to the 154:ref:`CPU Reset` for more information on the effect of the 155``PROGRAMMABLE_RESET_ADDRESS`` platform build option. 156 157Architectural initialization 158^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 159 160BL1 performs minimal architectural initialization as follows. 161 162- Exception vectors 163 164 BL1 sets up simple exception vectors for both synchronous and asynchronous 165 exceptions. The default behavior upon receiving an exception is to populate 166 a status code in the general purpose register ``X0/R0`` and call the 167 ``plat_report_exception()`` function (see the :ref:`Porting Guide`). The 168 status code is one of: 169 170 For AArch64: 171 172 :: 173 174 0x0 : Synchronous exception from Current EL with SP_EL0 175 0x1 : IRQ exception from Current EL with SP_EL0 176 0x2 : FIQ exception from Current EL with SP_EL0 177 0x3 : System Error exception from Current EL with SP_EL0 178 0x4 : Synchronous exception from Current EL with SP_ELx 179 0x5 : IRQ exception from Current EL with SP_ELx 180 0x6 : FIQ exception from Current EL with SP_ELx 181 0x7 : System Error exception from Current EL with SP_ELx 182 0x8 : Synchronous exception from Lower EL using aarch64 183 0x9 : IRQ exception from Lower EL using aarch64 184 0xa : FIQ exception from Lower EL using aarch64 185 0xb : System Error exception from Lower EL using aarch64 186 0xc : Synchronous exception from Lower EL using aarch32 187 0xd : IRQ exception from Lower EL using aarch32 188 0xe : FIQ exception from Lower EL using aarch32 189 0xf : System Error exception from Lower EL using aarch32 190 191 For AArch32: 192 193 :: 194 195 0x10 : User mode 196 0x11 : FIQ mode 197 0x12 : IRQ mode 198 0x13 : SVC mode 199 0x16 : Monitor mode 200 0x17 : Abort mode 201 0x1a : Hypervisor mode 202 0x1b : Undefined mode 203 0x1f : System mode 204 205 The ``plat_report_exception()`` implementation on the Arm FVP port programs 206 the Versatile Express System LED register in the following format to 207 indicate the occurrence of an unexpected exception: 208 209 :: 210 211 SYS_LED[0] - Security state (Secure=0/Non-Secure=1) 212 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0) 213 For AArch32 it is always 0x0 214 SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value 215 of the status code 216 217 A write to the LED register reflects in the System LEDs (S6LED0..7) in the 218 CLCD window of the FVP. 219 220 BL1 does not expect to receive any exceptions other than the SMC exception. 221 For the latter, BL1 installs a simple stub. The stub expects to receive a 222 limited set of SMC types (determined by their function IDs in the general 223 purpose register ``X0/R0``): 224 225 - ``BL1_SMC_RUN_IMAGE``: This SMC is raised by BL2 to make BL1 pass control 226 to EL3 Runtime Software. 227 - All SMCs listed in section "BL1 SMC Interface" in the :ref:`Firmware Update (FWU)` 228 Design Guide are supported for AArch64 only. These SMCs are currently 229 not supported when BL1 is built for AArch32. 230 231 Any other SMC leads to an assertion failure. 232 233- CPU initialization 234 235 BL1 calls the ``reset_handler()`` function which in turn calls the CPU 236 specific reset handler function (see the section: "CPU specific operations 237 framework"). 238 239- Control register setup (for AArch64) 240 241 - ``SCTLR_EL3``. Instruction cache is enabled by setting the ``SCTLR_EL3.I`` 242 bit. Alignment and stack alignment checking is enabled by setting the 243 ``SCTLR_EL3.A`` and ``SCTLR_EL3.SA`` bits. Exception endianness is set to 244 little-endian by clearing the ``SCTLR_EL3.EE`` bit. 245 246 - ``SCR_EL3``. The register width of the next lower exception level is set 247 to AArch64 by setting the ``SCR.RW`` bit. The ``SCR.EA`` bit is set to trap 248 both External Aborts and SError Interrupts in EL3. The ``SCR.SIF`` bit is 249 also set to disable instruction fetches from Non-secure memory when in 250 secure state. 251 252 - ``CPTR_EL3``. Accesses to the ``CPACR_EL1`` register from EL1 or EL2, or the 253 ``CPTR_EL2`` register from EL2 are configured to not trap to EL3 by 254 clearing the ``CPTR_EL3.TCPAC`` bit. Access to the trace functionality is 255 configured not to trap to EL3 by clearing the ``CPTR_EL3.TTA`` bit. 256 Instructions that access the registers associated with Floating Point 257 and Advanced SIMD execution are configured to not trap to EL3 by 258 clearing the ``CPTR_EL3.TFP`` bit. 259 260 - ``DAIF``. The SError interrupt is enabled by clearing the SError interrupt 261 mask bit. 262 263 - ``MDCR_EL3``. The trap controls, ``MDCR_EL3.TDOSA``, ``MDCR_EL3.TDA`` and 264 ``MDCR_EL3.TPM``, are set so that accesses to the registers they control 265 do not trap to EL3. AArch64 Secure self-hosted debug is disabled by 266 setting the ``MDCR_EL3.SDD`` bit. Also ``MDCR_EL3.SPD32`` is set to 267 disable AArch32 Secure self-hosted privileged debug from S-EL1. 268 269- Control register setup (for AArch32) 270 271 - ``SCTLR``. Instruction cache is enabled by setting the ``SCTLR.I`` bit. 272 Alignment checking is enabled by setting the ``SCTLR.A`` bit. 273 Exception endianness is set to little-endian by clearing the 274 ``SCTLR.EE`` bit. 275 276 - ``SCR``. The ``SCR.SIF`` bit is set to disable instruction fetches from 277 Non-secure memory when in secure state. 278 279 - ``CPACR``. Allow execution of Advanced SIMD instructions at PL0 and PL1, 280 by clearing the ``CPACR.ASEDIS`` bit. Access to the trace functionality 281 is configured not to trap to undefined mode by clearing the 282 ``CPACR.TRCDIS`` bit. 283 284 - ``NSACR``. Enable non-secure access to Advanced SIMD functionality and 285 system register access to implemented trace registers. 286 287 - ``FPEXC``. Enable access to the Advanced SIMD and floating-point 288 functionality from all Exception levels. 289 290 - ``CPSR.A``. The Asynchronous data abort interrupt is enabled by clearing 291 the Asynchronous data abort interrupt mask bit. 292 293 - ``SDCR``. The ``SDCR.SPD`` field is set to disable AArch32 Secure 294 self-hosted privileged debug. 295 296Platform initialization 297^^^^^^^^^^^^^^^^^^^^^^^ 298 299On Arm platforms, BL1 performs the following platform initializations: 300 301- Enable the Trusted Watchdog. 302- Initialize the console. 303- Configure the Interconnect to enable hardware coherency. 304- Enable the MMU and map the memory it needs to access. 305- Configure any required platform storage to load the next bootloader image 306 (BL2). 307- If the BL1 dynamic configuration file, ``TB_FW_CONFIG``, is available, then 308 load it to the platform defined address and make it available to BL2 via 309 ``arg0``. 310- Configure the system timer and program the `CNTFRQ_EL0` for use by NS-BL1U 311 and NS-BL2U firmware update images. 312 313Firmware Update detection and execution 314^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 315 316After performing platform setup, BL1 common code calls 317``bl1_plat_get_next_image_id()`` to determine if :ref:`Firmware Update (FWU)` is 318required or to proceed with the normal boot process. If the platform code 319returns ``BL2_IMAGE_ID`` then the normal boot sequence is executed as described 320in the next section, else BL1 assumes that :ref:`Firmware Update (FWU)` is 321required and execution passes to the first image in the 322:ref:`Firmware Update (FWU)` process. In either case, BL1 retrieves a descriptor 323of the next image by calling ``bl1_plat_get_image_desc()``. The image descriptor 324contains an ``entry_point_info_t`` structure, which BL1 uses to initialize the 325execution state of the next image. 326 327BL2 image load and execution 328^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 329 330In the normal boot flow, BL1 execution continues as follows: 331 332#. BL1 prints the following string from the primary CPU to indicate successful 333 execution of the BL1 stage: 334 335 :: 336 337 "Booting Trusted Firmware" 338 339#. BL1 loads a BL2 raw binary image from platform storage, at a 340 platform-specific base address. Prior to the load, BL1 invokes 341 ``bl1_plat_handle_pre_image_load()`` which allows the platform to update or 342 use the image information. If the BL2 image file is not present or if 343 there is not enough free trusted SRAM the following error message is 344 printed: 345 346 :: 347 348 "Failed to load BL2 firmware." 349 350#. BL1 invokes ``bl1_plat_handle_post_image_load()`` which again is intended 351 for platforms to take further action after image load. This function must 352 populate the necessary arguments for BL2, which may also include the memory 353 layout. Further description of the memory layout can be found later 354 in this document. 355 356#. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at 357 Secure SVC mode (for AArch32), starting from its load address. 358 359BL2 360~~~ 361 362BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure 363SVC mode (for AArch32) . BL2 is linked against and loaded at a platform-specific 364base address (more information can be found later in this document). 365The functionality implemented by BL2 is as follows. 366 367Architectural initialization 368^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 369 370For AArch64, BL2 performs the minimal architectural initialization required 371for subsequent stages of TF-A and normal world software. EL1 and EL0 are given 372access to Floating Point and Advanced SIMD registers by clearing the 373``CPACR.FPEN`` bits. 374 375For AArch32, the minimal architectural initialization required for subsequent 376stages of TF-A and normal world software is taken care of in BL1 as both BL1 377and BL2 execute at PL1. 378 379Platform initialization 380^^^^^^^^^^^^^^^^^^^^^^^ 381 382On Arm platforms, BL2 performs the following platform initializations: 383 384- Initialize the console. 385- Configure any required platform storage to allow loading further bootloader 386 images. 387- Enable the MMU and map the memory it needs to access. 388- Perform platform security setup to allow access to controlled components. 389- Reserve some memory for passing information to the next bootloader image 390 EL3 Runtime Software and populate it. 391- Define the extents of memory available for loading each subsequent 392 bootloader image. 393- If BL1 has passed TB_FW_CONFIG dynamic configuration file in ``arg0``, 394 then parse it. 395 396Image loading in BL2 397^^^^^^^^^^^^^^^^^^^^ 398 399BL2 generic code loads the images based on the list of loadable images 400provided by the platform. BL2 passes the list of executable images 401provided by the platform to the next handover BL image. 402 403The list of loadable images provided by the platform may also contain 404dynamic configuration files. The files are loaded and can be parsed as 405needed in the ``bl2_plat_handle_post_image_load()`` function. These 406configuration files can be passed to next Boot Loader stages as arguments 407by updating the corresponding entrypoint information in this function. 408 409SCP_BL2 (System Control Processor Firmware) image load 410^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 411 412Some systems have a separate System Control Processor (SCP) for power, clock, 413reset and system control. BL2 loads the optional SCP_BL2 image from platform 414storage into a platform-specific region of secure memory. The subsequent 415handling of SCP_BL2 is platform specific. For example, on the Juno Arm 416development platform port the image is transferred into SCP's internal memory 417using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM 418memory. The SCP executes SCP_BL2 and signals to the Application Processor (AP) 419for BL2 execution to continue. 420 421EL3 Runtime Software image load 422^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 423 424BL2 loads the EL3 Runtime Software image from platform storage into a platform- 425specific address in trusted SRAM. If there is not enough memory to load the 426image or image is missing it leads to an assertion failure. 427 428AArch64 BL32 (Secure-EL1 Payload) image load 429^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 430 431BL2 loads the optional BL32 image from platform storage into a platform- 432specific region of secure memory. The image executes in the secure world. BL2 433relies on BL31 to pass control to the BL32 image, if present. Hence, BL2 434populates a platform-specific area of memory with the entrypoint/load-address 435of the BL32 image. The value of the Saved Processor Status Register (``SPSR``) 436for entry into BL32 is not determined by BL2, it is initialized by the 437Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for 438managing interaction with BL32. This information is passed to BL31. 439 440BL33 (Non-trusted Firmware) image load 441^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 442 443BL2 loads the BL33 image (e.g. UEFI or other test or boot software) from 444platform storage into non-secure memory as defined by the platform. 445 446BL2 relies on EL3 Runtime Software to pass control to BL33 once secure state 447initialization is complete. Hence, BL2 populates a platform-specific area of 448memory with the entrypoint and Saved Program Status Register (``SPSR``) of the 449normal world software image. The entrypoint is the load address of the BL33 450image. The ``SPSR`` is determined as specified in Section 5.13 of the 451`Power State Coordination Interface PDD`_. This information is passed to the 452EL3 Runtime Software. 453 454AArch64 BL31 (EL3 Runtime Software) execution 455^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 456 457BL2 execution continues as follows: 458 459#. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the 460 BL31 entrypoint. The exception is handled by the SMC exception handler 461 installed by BL1. 462 463#. BL1 turns off the MMU and flushes the caches. It clears the 464 ``SCTLR_EL3.M/I/C`` bits, flushes the data cache to the point of coherency 465 and invalidates the TLBs. 466 467#. BL1 passes control to BL31 at the specified entrypoint at EL3. 468 469Running BL2 at EL3 execution level 470~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 471 472Some platforms have a non-TF-A Boot ROM that expects the next boot stage 473to execute at EL3. On these platforms, TF-A BL1 is a waste of memory 474as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid 475this waste, a special mode enables BL2 to execute at EL3, which allows 476a non-TF-A Boot ROM to load and jump directly to BL2. This mode is selected 477when the build flag BL2_AT_EL3 is enabled. The main differences in this 478mode are: 479 480#. BL2 includes the reset code and the mailbox mechanism to differentiate 481 cold boot and warm boot. It runs at EL3 doing the arch 482 initialization required for EL3. 483 484#. BL2 does not receive the meminfo information from BL1 anymore. This 485 information can be passed by the Boot ROM or be internal to the 486 BL2 image. 487 488#. Since BL2 executes at EL3, BL2 jumps directly to the next image, 489 instead of invoking the RUN_IMAGE SMC call. 490 491 492We assume 3 different types of BootROM support on the platform: 493 494#. The Boot ROM always jumps to the same address, for both cold 495 and warm boot. In this case, we will need to keep a resident part 496 of BL2 whose memory cannot be reclaimed by any other image. The 497 linker script defines the symbols __TEXT_RESIDENT_START__ and 498 __TEXT_RESIDENT_END__ that allows the platform to configure 499 correctly the memory map. 500#. The platform has some mechanism to indicate the jump address to the 501 Boot ROM. Platform code can then program the jump address with 502 psci_warmboot_entrypoint during cold boot. 503#. The platform has some mechanism to program the reset address using 504 the PROGRAMMABLE_RESET_ADDRESS feature. Platform code can then 505 program the reset address with psci_warmboot_entrypoint during 506 cold boot, bypassing the boot ROM for warm boot. 507 508In the last 2 cases, no part of BL2 needs to remain resident at 509runtime. In the first 2 cases, we expect the Boot ROM to be able to 510differentiate between warm and cold boot, to avoid loading BL2 again 511during warm boot. 512 513This functionality can be tested with FVP loading the image directly 514in memory and changing the address where the system jumps at reset. 515For example: 516 517 -C cluster0.cpu0.RVBAR=0x4022000 518 --data cluster0.cpu0=bl2.bin@0x4022000 519 520With this configuration, FVP is like a platform of the first case, 521where the Boot ROM jumps always to the same address. For simplification, 522BL32 is loaded in DRAM in this case, to avoid other images reclaiming 523BL2 memory. 524 525 526AArch64 BL31 527~~~~~~~~~~~~ 528 529The image for this stage is loaded by BL2 and BL1 passes control to BL31 at 530EL3. BL31 executes solely in trusted SRAM. BL31 is linked against and 531loaded at a platform-specific base address (more information can be found later 532in this document). The functionality implemented by BL31 is as follows. 533 534Architectural initialization 535^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 536 537Currently, BL31 performs a similar architectural initialization to BL1 as 538far as system register settings are concerned. Since BL1 code resides in ROM, 539architectural initialization in BL31 allows override of any previous 540initialization done by BL1. 541 542BL31 initializes the per-CPU data framework, which provides a cache of 543frequently accessed per-CPU data optimised for fast, concurrent manipulation 544on different CPUs. This buffer includes pointers to per-CPU contexts, crash 545buffer, CPU reset and power down operations, PSCI data, platform data and so on. 546 547It then replaces the exception vectors populated by BL1 with its own. BL31 548exception vectors implement more elaborate support for handling SMCs since this 549is the only mechanism to access the runtime services implemented by BL31 (PSCI 550for example). BL31 checks each SMC for validity as specified by the 551`SMC Calling Convention`_ before passing control to the required SMC 552handler routine. 553 554BL31 programs the ``CNTFRQ_EL0`` register with the clock frequency of the system 555counter, which is provided by the platform. 556 557Platform initialization 558^^^^^^^^^^^^^^^^^^^^^^^ 559 560BL31 performs detailed platform initialization, which enables normal world 561software to function correctly. 562 563On Arm platforms, this consists of the following: 564 565- Initialize the console. 566- Configure the Interconnect to enable hardware coherency. 567- Enable the MMU and map the memory it needs to access. 568- Initialize the generic interrupt controller. 569- Initialize the power controller device. 570- Detect the system topology. 571 572Runtime services initialization 573^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 574 575BL31 is responsible for initializing the runtime services. One of them is PSCI. 576 577As part of the PSCI initializations, BL31 detects the system topology. It also 578initializes the data structures that implement the state machine used to track 579the state of power domain nodes. The state can be one of ``OFF``, ``RUN`` or 580``RETENTION``. All secondary CPUs are initially in the ``OFF`` state. The cluster 581that the primary CPU belongs to is ``ON``; any other cluster is ``OFF``. It also 582initializes the locks that protect them. BL31 accesses the state of a CPU or 583cluster immediately after reset and before the data cache is enabled in the 584warm boot path. It is not currently possible to use 'exclusive' based spinlocks, 585therefore BL31 uses locks based on Lamport's Bakery algorithm instead. 586 587The runtime service framework and its initialization is described in more 588detail in the "EL3 runtime services framework" section below. 589 590Details about the status of the PSCI implementation are provided in the 591"Power State Coordination Interface" section below. 592 593AArch64 BL32 (Secure-EL1 Payload) image initialization 594^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 595 596If a BL32 image is present then there must be a matching Secure-EL1 Payload 597Dispatcher (SPD) service (see later for details). During initialization 598that service must register a function to carry out initialization of BL32 599once the runtime services are fully initialized. BL31 invokes such a 600registered function to initialize BL32 before running BL33. This initialization 601is not necessary for AArch32 SPs. 602 603Details on BL32 initialization and the SPD's role are described in the 604:ref:`firmware_design_sel1_spd` section below. 605 606BL33 (Non-trusted Firmware) execution 607^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 608 609EL3 Runtime Software initializes the EL2 or EL1 processor context for normal- 610world cold boot, ensuring that no secure state information finds its way into 611the non-secure execution state. EL3 Runtime Software uses the entrypoint 612information provided by BL2 to jump to the Non-trusted firmware image (BL33) 613at the highest available Exception Level (EL2 if available, otherwise EL1). 614 615Using alternative Trusted Boot Firmware in place of BL1 & BL2 (AArch64 only) 616~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 617 618Some platforms have existing implementations of Trusted Boot Firmware that 619would like to use TF-A BL31 for the EL3 Runtime Software. To enable this 620firmware architecture it is important to provide a fully documented and stable 621interface between the Trusted Boot Firmware and BL31. 622 623Future changes to the BL31 interface will be done in a backwards compatible 624way, and this enables these firmware components to be independently enhanced/ 625updated to develop and exploit new functionality. 626 627Required CPU state when calling ``bl31_entrypoint()`` during cold boot 628^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 629 630This function must only be called by the primary CPU. 631 632On entry to this function the calling primary CPU must be executing in AArch64 633EL3, little-endian data access, and all interrupt sources masked: 634 635:: 636 637 PSTATE.EL = 3 638 PSTATE.RW = 1 639 PSTATE.DAIF = 0xf 640 SCTLR_EL3.EE = 0 641 642X0 and X1 can be used to pass information from the Trusted Boot Firmware to the 643platform code in BL31: 644 645:: 646 647 X0 : Reserved for common TF-A information 648 X1 : Platform specific information 649 650BL31 zero-init sections (e.g. ``.bss``) should not contain valid data on entry, 651these will be zero filled prior to invoking platform setup code. 652 653Use of the X0 and X1 parameters 654''''''''''''''''''''''''''''''' 655 656The parameters are platform specific and passed from ``bl31_entrypoint()`` to 657``bl31_early_platform_setup()``. The value of these parameters is never directly 658used by the common BL31 code. 659 660The convention is that ``X0`` conveys information regarding the BL31, BL32 and 661BL33 images from the Trusted Boot firmware and ``X1`` can be used for other 662platform specific purpose. This convention allows platforms which use TF-A's 663BL1 and BL2 images to transfer additional platform specific information from 664Secure Boot without conflicting with future evolution of TF-A using ``X0`` to 665pass a ``bl31_params`` structure. 666 667BL31 common and SPD initialization code depends on image and entrypoint 668information about BL33 and BL32, which is provided via BL31 platform APIs. 669This information is required until the start of execution of BL33. This 670information can be provided in a platform defined manner, e.g. compiled into 671the platform code in BL31, or provided in a platform defined memory location 672by the Trusted Boot firmware, or passed from the Trusted Boot Firmware via the 673Cold boot Initialization parameters. This data may need to be cleaned out of 674the CPU caches if it is provided by an earlier boot stage and then accessed by 675BL31 platform code before the caches are enabled. 676 677TF-A's BL2 implementation passes a ``bl31_params`` structure in 678``X0`` and the Arm development platforms interpret this in the BL31 platform 679code. 680 681MMU, Data caches & Coherency 682'''''''''''''''''''''''''''' 683 684BL31 does not depend on the enabled state of the MMU, data caches or 685interconnect coherency on entry to ``bl31_entrypoint()``. If these are disabled 686on entry, these should be enabled during ``bl31_plat_arch_setup()``. 687 688Data structures used in the BL31 cold boot interface 689'''''''''''''''''''''''''''''''''''''''''''''''''''' 690 691These structures are designed to support compatibility and independent 692evolution of the structures and the firmware images. For example, a version of 693BL31 that can interpret the BL3x image information from different versions of 694BL2, a platform that uses an extended entry_point_info structure to convey 695additional register information to BL31, or a ELF image loader that can convey 696more details about the firmware images. 697 698To support these scenarios the structures are versioned and sized, which enables 699BL31 to detect which information is present and respond appropriately. The 700``param_header`` is defined to capture this information: 701 702.. code:: c 703 704 typedef struct param_header { 705 uint8_t type; /* type of the structure */ 706 uint8_t version; /* version of this structure */ 707 uint16_t size; /* size of this structure in bytes */ 708 uint32_t attr; /* attributes: unused bits SBZ */ 709 } param_header_t; 710 711The structures using this format are ``entry_point_info``, ``image_info`` and 712``bl31_params``. The code that allocates and populates these structures must set 713the header fields appropriately, and the ``SET_PARAM_HEAD()`` a macro is defined 714to simplify this action. 715 716Required CPU state for BL31 Warm boot initialization 717^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 718 719When requesting a CPU power-on, or suspending a running CPU, TF-A provides 720the platform power management code with a Warm boot initialization 721entry-point, to be invoked by the CPU immediately after the reset handler. 722On entry to the Warm boot initialization function the calling CPU must be in 723AArch64 EL3, little-endian data access and all interrupt sources masked: 724 725:: 726 727 PSTATE.EL = 3 728 PSTATE.RW = 1 729 PSTATE.DAIF = 0xf 730 SCTLR_EL3.EE = 0 731 732The PSCI implementation will initialize the processor state and ensure that the 733platform power management code is then invoked as required to initialize all 734necessary system, cluster and CPU resources. 735 736AArch32 EL3 Runtime Software entrypoint interface 737~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 738 739To enable this firmware architecture it is important to provide a fully 740documented and stable interface between the Trusted Boot Firmware and the 741AArch32 EL3 Runtime Software. 742 743Future changes to the entrypoint interface will be done in a backwards 744compatible way, and this enables these firmware components to be independently 745enhanced/updated to develop and exploit new functionality. 746 747Required CPU state when entering during cold boot 748^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 749 750This function must only be called by the primary CPU. 751 752On entry to this function the calling primary CPU must be executing in AArch32 753EL3, little-endian data access, and all interrupt sources masked: 754 755:: 756 757 PSTATE.AIF = 0x7 758 SCTLR.EE = 0 759 760R0 and R1 are used to pass information from the Trusted Boot Firmware to the 761platform code in AArch32 EL3 Runtime Software: 762 763:: 764 765 R0 : Reserved for common TF-A information 766 R1 : Platform specific information 767 768Use of the R0 and R1 parameters 769''''''''''''''''''''''''''''''' 770 771The parameters are platform specific and the convention is that ``R0`` conveys 772information regarding the BL3x images from the Trusted Boot firmware and ``R1`` 773can be used for other platform specific purpose. This convention allows 774platforms which use TF-A's BL1 and BL2 images to transfer additional platform 775specific information from Secure Boot without conflicting with future 776evolution of TF-A using ``R0`` to pass a ``bl_params`` structure. 777 778The AArch32 EL3 Runtime Software is responsible for entry into BL33. This 779information can be obtained in a platform defined manner, e.g. compiled into 780the AArch32 EL3 Runtime Software, or provided in a platform defined memory 781location by the Trusted Boot firmware, or passed from the Trusted Boot Firmware 782via the Cold boot Initialization parameters. This data may need to be cleaned 783out of the CPU caches if it is provided by an earlier boot stage and then 784accessed by AArch32 EL3 Runtime Software before the caches are enabled. 785 786When using AArch32 EL3 Runtime Software, the Arm development platforms pass a 787``bl_params`` structure in ``R0`` from BL2 to be interpreted by AArch32 EL3 Runtime 788Software platform code. 789 790MMU, Data caches & Coherency 791'''''''''''''''''''''''''''' 792 793AArch32 EL3 Runtime Software must not depend on the enabled state of the MMU, 794data caches or interconnect coherency in its entrypoint. They must be explicitly 795enabled if required. 796 797Data structures used in cold boot interface 798''''''''''''''''''''''''''''''''''''''''''' 799 800The AArch32 EL3 Runtime Software cold boot interface uses ``bl_params`` instead 801of ``bl31_params``. The ``bl_params`` structure is based on the convention 802described in AArch64 BL31 cold boot interface section. 803 804Required CPU state for warm boot initialization 805^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 806 807When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3 808Runtime Software must ensure execution of a warm boot initialization entrypoint. 809If TF-A BL1 is used and the PROGRAMMABLE_RESET_ADDRESS build flag is false, 810then AArch32 EL3 Runtime Software must ensure that BL1 branches to the warm 811boot entrypoint by arranging for the BL1 platform function, 812plat_get_my_entrypoint(), to return a non-zero value. 813 814In this case, the warm boot entrypoint must be in AArch32 EL3, little-endian 815data access and all interrupt sources masked: 816 817:: 818 819 PSTATE.AIF = 0x7 820 SCTLR.EE = 0 821 822The warm boot entrypoint may be implemented by using TF-A 823``psci_warmboot_entrypoint()`` function. In that case, the platform must fulfil 824the pre-requisites mentioned in the 825:ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`. 826 827EL3 runtime services framework 828------------------------------ 829 830Software executing in the non-secure state and in the secure state at exception 831levels lower than EL3 will request runtime services using the Secure Monitor 832Call (SMC) instruction. These requests will follow the convention described in 833the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function 834identifiers to each SMC request and describes how arguments are passed and 835returned. 836 837The EL3 runtime services framework enables the development of services by 838different providers that can be easily integrated into final product firmware. 839The following sections describe the framework which facilitates the 840registration, initialization and use of runtime services in EL3 Runtime 841Software (BL31). 842 843The design of the runtime services depends heavily on the concepts and 844definitions described in the `SMCCC`_, in particular SMC Function IDs, Owning 845Entity Numbers (OEN), Fast and Yielding calls, and the SMC32 and SMC64 calling 846conventions. Please refer to that document for more detailed explanation of 847these terms. 848 849The following runtime services are expected to be implemented first. They have 850not all been instantiated in the current implementation. 851 852#. Standard service calls 853 854 This service is for management of the entire system. The Power State 855 Coordination Interface (`PSCI`_) is the first set of standard service calls 856 defined by Arm (see PSCI section later). 857 858#. Secure-EL1 Payload Dispatcher service 859 860 If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then 861 it also requires a *Secure Monitor* at EL3 to switch the EL1 processor 862 context between the normal world (EL1/EL2) and trusted world (Secure-EL1). 863 The Secure Monitor will make these world switches in response to SMCs. The 864 `SMCCC`_ provides for such SMCs with the Trusted OS Call and Trusted 865 Application Call OEN ranges. 866 867 The interface between the EL3 Runtime Software and the Secure-EL1 Payload is 868 not defined by the `SMCCC`_ or any other standard. As a result, each 869 Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime 870 service - within TF-A this service is referred to as the Secure-EL1 Payload 871 Dispatcher (SPD). 872 873 TF-A provides a Test Secure-EL1 Payload (TSP) and its associated Dispatcher 874 (TSPD). Details of SPD design and TSP/TSPD operation are described in the 875 :ref:`firmware_design_sel1_spd` section below. 876 877#. CPU implementation service 878 879 This service will provide an interface to CPU implementation specific 880 services for a given platform e.g. access to processor errata workarounds. 881 This service is currently unimplemented. 882 883Additional services for Arm Architecture, SiP and OEM calls can be implemented. 884Each implemented service handles a range of SMC function identifiers as 885described in the `SMCCC`_. 886 887Registration 888~~~~~~~~~~~~ 889 890A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying 891the name of the service, the range of OENs covered, the type of service and 892initialization and call handler functions. This macro instantiates a ``const struct rt_svc_desc`` for the service with these details (see ``runtime_svc.h``). 893This structure is allocated in a special ELF section ``rt_svc_descs``, enabling 894the framework to find all service descriptors included into BL31. 895 896The specific service for a SMC Function is selected based on the OEN and call 897type of the Function ID, and the framework uses that information in the service 898descriptor to identify the handler for the SMC Call. 899 900The service descriptors do not include information to identify the precise set 901of SMC function identifiers supported by this service implementation, the 902security state from which such calls are valid nor the capability to support 90364-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately 904to these aspects of a SMC call is the responsibility of the service 905implementation, the framework is focused on integration of services from 906different providers and minimizing the time taken by the framework before the 907service handler is invoked. 908 909Details of the parameters, requirements and behavior of the initialization and 910call handling functions are provided in the following sections. 911 912Initialization 913~~~~~~~~~~~~~~ 914 915``runtime_svc_init()`` in ``runtime_svc.c`` initializes the runtime services 916framework running on the primary CPU during cold boot as part of the BL31 917initialization. This happens prior to initializing a Trusted OS and running 918Normal world boot firmware that might in turn use these services. 919Initialization involves validating each of the declared runtime service 920descriptors, calling the service initialization function and populating the 921index used for runtime lookup of the service. 922 923The BL31 linker script collects all of the declared service descriptors into a 924single array and defines symbols that allow the framework to locate and traverse 925the array, and determine its size. 926 927The framework does basic validation of each descriptor to halt firmware 928initialization if service declaration errors are detected. The framework does 929not check descriptors for the following error conditions, and may behave in an 930unpredictable manner under such scenarios: 931 932#. Overlapping OEN ranges 933#. Multiple descriptors for the same range of OENs and ``call_type`` 934#. Incorrect range of owning entity numbers for a given ``call_type`` 935 936Once validated, the service ``init()`` callback is invoked. This function carries 937out any essential EL3 initialization before servicing requests. The ``init()`` 938function is only invoked on the primary CPU during cold boot. If the service 939uses per-CPU data this must either be initialized for all CPUs during this call, 940or be done lazily when a CPU first issues an SMC call to that service. If 941``init()`` returns anything other than ``0``, this is treated as an initialization 942error and the service is ignored: this does not cause the firmware to halt. 943 944The OEN and call type fields present in the SMC Function ID cover a total of 945128 distinct services, but in practice a single descriptor can cover a range of 946OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a 947service handler, the framework uses an array of 128 indices that map every 948distinct OEN/call-type combination either to one of the declared services or to 949indicate the service is not handled. This ``rt_svc_descs_indices[]`` array is 950populated for all of the OENs covered by a service after the service ``init()`` 951function has reported success. So a service that fails to initialize will never 952have it's ``handle()`` function invoked. 953 954The following figure shows how the ``rt_svc_descs_indices[]`` index maps the SMC 955Function ID call type and OEN onto a specific service handler in the 956``rt_svc_descs[]`` array. 957 958|Image 1| 959 960Handling an SMC 961~~~~~~~~~~~~~~~ 962 963When the EL3 runtime services framework receives a Secure Monitor Call, the SMC 964Function ID is passed in W0 from the lower exception level (as per the 965`SMCCC`_). If the calling register width is AArch32, it is invalid to invoke an 966SMC Function which indicates the SMC64 calling convention: such calls are 967ignored and return the Unknown SMC Function Identifier result code ``0xFFFFFFFF`` 968in R0/X0. 969 970Bit[31] (fast/yielding call) and bits[29:24] (owning entity number) of the SMC 971Function ID are combined to index into the ``rt_svc_descs_indices[]`` array. The 972resulting value might indicate a service that has no handler, in this case the 973framework will also report an Unknown SMC Function ID. Otherwise, the value is 974used as a further index into the ``rt_svc_descs[]`` array to locate the required 975service and handler. 976 977The service's ``handle()`` callback is provided with five of the SMC parameters 978directly, the others are saved into memory for retrieval (if needed) by the 979handler. The handler is also provided with an opaque ``handle`` for use with the 980supporting library for parameter retrieval, setting return values and context 981manipulation; and with ``flags`` indicating the security state of the caller. The 982framework finally sets up the execution stack for the handler, and invokes the 983services ``handle()`` function. 984 985On return from the handler the result registers are populated in X0-X7 as needed 986before restoring the stack and CPU state and returning from the original SMC. 987 988Exception Handling Framework 989---------------------------- 990 991Please refer to the `Exception Handling Framework`_ document. 992 993Power State Coordination Interface 994---------------------------------- 995 996TODO: Provide design walkthrough of PSCI implementation. 997 998The PSCI v1.1 specification categorizes APIs as optional and mandatory. All the 999mandatory APIs in PSCI v1.1, PSCI v1.0 and in PSCI v0.2 draft specification 1000`Power State Coordination Interface PDD`_ are implemented. The table lists 1001the PSCI v1.1 APIs and their support in generic code. 1002 1003An API implementation might have a dependency on platform code e.g. CPU_SUSPEND 1004requires the platform to export a part of the implementation. Hence the level 1005of support of the mandatory APIs depends upon the support exported by the 1006platform port as well. The Juno and FVP (all variants) platforms export all the 1007required support. 1008 1009+-----------------------------+-------------+-------------------------------+ 1010| PSCI v1.1 API | Supported | Comments | 1011+=============================+=============+===============================+ 1012| ``PSCI_VERSION`` | Yes | The version returned is 1.1 | 1013+-----------------------------+-------------+-------------------------------+ 1014| ``CPU_SUSPEND`` | Yes\* | | 1015+-----------------------------+-------------+-------------------------------+ 1016| ``CPU_OFF`` | Yes\* | | 1017+-----------------------------+-------------+-------------------------------+ 1018| ``CPU_ON`` | Yes\* | | 1019+-----------------------------+-------------+-------------------------------+ 1020| ``AFFINITY_INFO`` | Yes | | 1021+-----------------------------+-------------+-------------------------------+ 1022| ``MIGRATE`` | Yes\*\* | | 1023+-----------------------------+-------------+-------------------------------+ 1024| ``MIGRATE_INFO_TYPE`` | Yes\*\* | | 1025+-----------------------------+-------------+-------------------------------+ 1026| ``MIGRATE_INFO_CPU`` | Yes\*\* | | 1027+-----------------------------+-------------+-------------------------------+ 1028| ``SYSTEM_OFF`` | Yes\* | | 1029+-----------------------------+-------------+-------------------------------+ 1030| ``SYSTEM_RESET`` | Yes\* | | 1031+-----------------------------+-------------+-------------------------------+ 1032| ``PSCI_FEATURES`` | Yes | | 1033+-----------------------------+-------------+-------------------------------+ 1034| ``CPU_FREEZE`` | No | | 1035+-----------------------------+-------------+-------------------------------+ 1036| ``CPU_DEFAULT_SUSPEND`` | No | | 1037+-----------------------------+-------------+-------------------------------+ 1038| ``NODE_HW_STATE`` | Yes\* | | 1039+-----------------------------+-------------+-------------------------------+ 1040| ``SYSTEM_SUSPEND`` | Yes\* | | 1041+-----------------------------+-------------+-------------------------------+ 1042| ``PSCI_SET_SUSPEND_MODE`` | No | | 1043+-----------------------------+-------------+-------------------------------+ 1044| ``PSCI_STAT_RESIDENCY`` | Yes\* | | 1045+-----------------------------+-------------+-------------------------------+ 1046| ``PSCI_STAT_COUNT`` | Yes\* | | 1047+-----------------------------+-------------+-------------------------------+ 1048| ``SYSTEM_RESET2`` | Yes\* | | 1049+-----------------------------+-------------+-------------------------------+ 1050| ``MEM_PROTECT`` | Yes\* | | 1051+-----------------------------+-------------+-------------------------------+ 1052| ``MEM_PROTECT_CHECK_RANGE`` | Yes\* | | 1053+-----------------------------+-------------+-------------------------------+ 1054 1055\*Note : These PSCI APIs require platform power management hooks to be 1056registered with the generic PSCI code to be supported. 1057 1058\*\*Note : These PSCI APIs require appropriate Secure Payload Dispatcher 1059hooks to be registered with the generic PSCI code to be supported. 1060 1061The PSCI implementation in TF-A is a library which can be integrated with 1062AArch64 or AArch32 EL3 Runtime Software for Armv8-A systems. A guide to 1063integrating PSCI library with AArch32 EL3 Runtime Software can be found 1064at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`. 1065 1066.. _firmware_design_sel1_spd: 1067 1068Secure-EL1 Payloads and Dispatchers 1069----------------------------------- 1070 1071On a production system that includes a Trusted OS running in Secure-EL1/EL0, 1072the Trusted OS is coupled with a companion runtime service in the BL31 1073firmware. This service is responsible for the initialisation of the Trusted 1074OS and all communications with it. The Trusted OS is the BL32 stage of the 1075boot flow in TF-A. The firmware will attempt to locate, load and execute a 1076BL32 image. 1077 1078TF-A uses a more general term for the BL32 software that runs at Secure-EL1 - 1079the *Secure-EL1 Payload* - as it is not always a Trusted OS. 1080 1081TF-A provides a Test Secure-EL1 Payload (TSP) and a Test Secure-EL1 Payload 1082Dispatcher (TSPD) service as an example of how a Trusted OS is supported on a 1083production system using the Runtime Services Framework. On such a system, the 1084Test BL32 image and service are replaced by the Trusted OS and its dispatcher 1085service. The TF-A build system expects that the dispatcher will define the 1086build flag ``NEED_BL32`` to enable it to include the BL32 in the build either 1087as a binary or to compile from source depending on whether the ``BL32`` build 1088option is specified or not. 1089 1090The TSP runs in Secure-EL1. It is designed to demonstrate synchronous 1091communication with the normal-world software running in EL1/EL2. Communication 1092is initiated by the normal-world software 1093 1094- either directly through a Fast SMC (as defined in the `SMCCC`_) 1095 1096- or indirectly through a `PSCI`_ SMC. The `PSCI`_ implementation in turn 1097 informs the TSPD about the requested power management operation. This allows 1098 the TSP to prepare for or respond to the power state change 1099 1100The TSPD service is responsible for. 1101 1102- Initializing the TSP 1103 1104- Routing requests and responses between the secure and the non-secure 1105 states during the two types of communications just described 1106 1107Initializing a BL32 Image 1108~~~~~~~~~~~~~~~~~~~~~~~~~ 1109 1110The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing 1111the BL32 image. It needs access to the information passed by BL2 to BL31 to do 1112so. This is provided by: 1113 1114.. code:: c 1115 1116 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t); 1117 1118which returns a reference to the ``entry_point_info`` structure corresponding to 1119the image which will be run in the specified security state. The SPD uses this 1120API to get entry point information for the SECURE image, BL32. 1121 1122In the absence of a BL32 image, BL31 passes control to the normal world 1123bootloader image (BL33). When the BL32 image is present, it is typical 1124that the SPD wants control to be passed to BL32 first and then later to BL33. 1125 1126To do this the SPD has to register a BL32 initialization function during 1127initialization of the SPD service. The BL32 initialization function has this 1128prototype: 1129 1130.. code:: c 1131 1132 int32_t init(void); 1133 1134and is registered using the ``bl31_register_bl32_init()`` function. 1135 1136TF-A supports two approaches for the SPD to pass control to BL32 before 1137returning through EL3 and running the non-trusted firmware (BL33): 1138 1139#. In the BL32 setup function, use ``bl31_set_next_image_type()`` to 1140 request that the exit from ``bl31_main()`` is to the BL32 entrypoint in 1141 Secure-EL1. BL31 will exit to BL32 using the asynchronous method by 1142 calling ``bl31_prepare_next_image_entry()`` and ``el3_exit()``. 1143 1144 When the BL32 has completed initialization at Secure-EL1, it returns to 1145 BL31 by issuing an SMC, using a Function ID allocated to the SPD. On 1146 receipt of this SMC, the SPD service handler should switch the CPU context 1147 from trusted to normal world and use the ``bl31_set_next_image_type()`` and 1148 ``bl31_prepare_next_image_entry()`` functions to set up the initial return to 1149 the normal world firmware BL33. On return from the handler the framework 1150 will exit to EL2 and run BL33. 1151 1152#. The BL32 setup function registers an initialization function using 1153 ``bl31_register_bl32_init()`` which provides a SPD-defined mechanism to 1154 invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32 1155 entrypoint. 1156 1157 .. note:: 1158 The Test SPD service included with TF-A provides one implementation 1159 of such a mechanism. 1160 1161 On completion BL32 returns control to BL31 via a SMC, and on receipt the 1162 SPD service handler invokes the synchronous call return mechanism to return 1163 to the BL32 initialization function. On return from this function, 1164 ``bl31_main()`` will set up the return to the normal world firmware BL33 and 1165 continue the boot process in the normal world. 1166 1167Crash Reporting in BL31 1168----------------------- 1169 1170BL31 implements a scheme for reporting the processor state when an unhandled 1171exception is encountered. The reporting mechanism attempts to preserve all the 1172register contents and report it via a dedicated UART (PL011 console). BL31 1173reports the general purpose, EL3, Secure EL1 and some EL2 state registers. 1174 1175A dedicated per-CPU crash stack is maintained by BL31 and this is retrieved via 1176the per-CPU pointer cache. The implementation attempts to minimise the memory 1177required for this feature. The file ``crash_reporting.S`` contains the 1178implementation for crash reporting. 1179 1180The sample crash output is shown below. 1181 1182:: 1183 1184 x0 = 0x000000002a4a0000 1185 x1 = 0x0000000000000001 1186 x2 = 0x0000000000000002 1187 x3 = 0x0000000000000003 1188 x4 = 0x0000000000000004 1189 x5 = 0x0000000000000005 1190 x6 = 0x0000000000000006 1191 x7 = 0x0000000000000007 1192 x8 = 0x0000000000000008 1193 x9 = 0x0000000000000009 1194 x10 = 0x0000000000000010 1195 x11 = 0x0000000000000011 1196 x12 = 0x0000000000000012 1197 x13 = 0x0000000000000013 1198 x14 = 0x0000000000000014 1199 x15 = 0x0000000000000015 1200 x16 = 0x0000000000000016 1201 x17 = 0x0000000000000017 1202 x18 = 0x0000000000000018 1203 x19 = 0x0000000000000019 1204 x20 = 0x0000000000000020 1205 x21 = 0x0000000000000021 1206 x22 = 0x0000000000000022 1207 x23 = 0x0000000000000023 1208 x24 = 0x0000000000000024 1209 x25 = 0x0000000000000025 1210 x26 = 0x0000000000000026 1211 x27 = 0x0000000000000027 1212 x28 = 0x0000000000000028 1213 x29 = 0x0000000000000029 1214 x30 = 0x0000000088000b78 1215 scr_el3 = 0x000000000003073d 1216 sctlr_el3 = 0x00000000b0cd183f 1217 cptr_el3 = 0x0000000000000000 1218 tcr_el3 = 0x000000008080351c 1219 daif = 0x00000000000002c0 1220 mair_el3 = 0x00000000004404ff 1221 spsr_el3 = 0x0000000060000349 1222 elr_el3 = 0x0000000088000114 1223 ttbr0_el3 = 0x0000000004018201 1224 esr_el3 = 0x00000000be000000 1225 far_el3 = 0x0000000000000000 1226 spsr_el1 = 0x0000000000000000 1227 elr_el1 = 0x0000000000000000 1228 spsr_abt = 0x0000000000000000 1229 spsr_und = 0x0000000000000000 1230 spsr_irq = 0x0000000000000000 1231 spsr_fiq = 0x0000000000000000 1232 sctlr_el1 = 0x0000000030d00800 1233 actlr_el1 = 0x0000000000000000 1234 cpacr_el1 = 0x0000000000000000 1235 csselr_el1 = 0x0000000000000000 1236 sp_el1 = 0x0000000000000000 1237 esr_el1 = 0x0000000000000000 1238 ttbr0_el1 = 0x0000000000000000 1239 ttbr1_el1 = 0x0000000000000000 1240 mair_el1 = 0x0000000000000000 1241 amair_el1 = 0x0000000000000000 1242 tcr_el1 = 0x0000000000000000 1243 tpidr_el1 = 0x0000000000000000 1244 tpidr_el0 = 0x0000000000000000 1245 tpidrro_el0 = 0x0000000000000000 1246 par_el1 = 0x0000000000000000 1247 mpidr_el1 = 0x0000000080000000 1248 afsr0_el1 = 0x0000000000000000 1249 afsr1_el1 = 0x0000000000000000 1250 contextidr_el1 = 0x0000000000000000 1251 vbar_el1 = 0x0000000000000000 1252 cntp_ctl_el0 = 0x0000000000000000 1253 cntp_cval_el0 = 0x0000000000000000 1254 cntv_ctl_el0 = 0x0000000000000000 1255 cntv_cval_el0 = 0x0000000000000000 1256 cntkctl_el1 = 0x0000000000000000 1257 sp_el0 = 0x0000000004014940 1258 isr_el1 = 0x0000000000000000 1259 dacr32_el2 = 0x0000000000000000 1260 ifsr32_el2 = 0x0000000000000000 1261 icc_hppir0_el1 = 0x00000000000003ff 1262 icc_hppir1_el1 = 0x00000000000003ff 1263 icc_ctlr_el3 = 0x0000000000080400 1264 gicd_ispendr regs (Offsets 0x200-0x278) 1265 Offset Value 1266 0x200: 0x0000000000000000 1267 0x208: 0x0000000000000000 1268 0x210: 0x0000000000000000 1269 0x218: 0x0000000000000000 1270 0x220: 0x0000000000000000 1271 0x228: 0x0000000000000000 1272 0x230: 0x0000000000000000 1273 0x238: 0x0000000000000000 1274 0x240: 0x0000000000000000 1275 0x248: 0x0000000000000000 1276 0x250: 0x0000000000000000 1277 0x258: 0x0000000000000000 1278 0x260: 0x0000000000000000 1279 0x268: 0x0000000000000000 1280 0x270: 0x0000000000000000 1281 0x278: 0x0000000000000000 1282 1283Guidelines for Reset Handlers 1284----------------------------- 1285 1286TF-A implements a framework that allows CPU and platform ports to perform 1287actions very early after a CPU is released from reset in both the cold and warm 1288boot paths. This is done by calling the ``reset_handler()`` function in both 1289the BL1 and BL31 images. It in turn calls the platform and CPU specific reset 1290handling functions. 1291 1292Details for implementing a CPU specific reset handler can be found in 1293Section 8. Details for implementing a platform specific reset handler can be 1294found in the :ref:`Porting Guide` (see the ``plat_reset_handler()`` function). 1295 1296When adding functionality to a reset handler, keep in mind that if a different 1297reset handling behavior is required between the first and the subsequent 1298invocations of the reset handling code, this should be detected at runtime. 1299In other words, the reset handler should be able to detect whether an action has 1300already been performed and act as appropriate. Possible courses of actions are, 1301e.g. skip the action the second time, or undo/redo it. 1302 1303Configuring secure interrupts 1304----------------------------- 1305 1306The GIC driver is responsible for performing initial configuration of secure 1307interrupts on the platform. To this end, the platform is expected to provide the 1308GIC driver (either GICv2 or GICv3, as selected by the platform) with the 1309interrupt configuration during the driver initialisation. 1310 1311Secure interrupt configuration are specified in an array of secure interrupt 1312properties. In this scheme, in both GICv2 and GICv3 driver data structures, the 1313``interrupt_props`` member points to an array of interrupt properties. Each 1314element of the array specifies the interrupt number and its attributes 1315(priority, group, configuration). Each element of the array shall be populated 1316by the macro ``INTR_PROP_DESC()``. The macro takes the following arguments: 1317 1318- 10-bit interrupt number, 1319 1320- 8-bit interrupt priority, 1321 1322- Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``, 1323 ``INTR_TYPE_NS``), 1324 1325- Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or 1326 ``GIC_INTR_CFG_EDGE``). 1327 1328.. _firmware_design_cpu_ops_fwk: 1329 1330CPU specific operations framework 1331--------------------------------- 1332 1333Certain aspects of the Armv8-A architecture are implementation defined, 1334that is, certain behaviours are not architecturally defined, but must be 1335defined and documented by individual processor implementations. TF-A 1336implements a framework which categorises the common implementation defined 1337behaviours and allows a processor to export its implementation of that 1338behaviour. The categories are: 1339 1340#. Processor specific reset sequence. 1341 1342#. Processor specific power down sequences. 1343 1344#. Processor specific register dumping as a part of crash reporting. 1345 1346#. Errata status reporting. 1347 1348Each of the above categories fulfils a different requirement. 1349 1350#. allows any processor specific initialization before the caches and MMU 1351 are turned on, like implementation of errata workarounds, entry into 1352 the intra-cluster coherency domain etc. 1353 1354#. allows each processor to implement the power down sequence mandated in 1355 its Technical Reference Manual (TRM). 1356 1357#. allows a processor to provide additional information to the developer 1358 in the event of a crash, for example Cortex-A53 has registers which 1359 can expose the data cache contents. 1360 1361#. allows a processor to define a function that inspects and reports the status 1362 of all errata workarounds on that processor. 1363 1364Please note that only 2. is mandated by the TRM. 1365 1366The CPU specific operations framework scales to accommodate a large number of 1367different CPUs during power down and reset handling. The platform can specify 1368any CPU optimization it wants to enable for each CPU. It can also specify 1369the CPU errata workarounds to be applied for each CPU type during reset 1370handling by defining CPU errata compile time macros. Details on these macros 1371can be found in the :ref:`Arm CPU Specific Build Macros` document. 1372 1373The CPU specific operations framework depends on the ``cpu_ops`` structure which 1374needs to be exported for each type of CPU in the platform. It is defined in 1375``include/lib/cpus/aarch64/cpu_macros.S`` and has the following fields : ``midr``, 1376``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and 1377``cpu_reg_dump()``. 1378 1379The CPU specific files in ``lib/cpus`` export a ``cpu_ops`` data structure with 1380suitable handlers for that CPU. For example, ``lib/cpus/aarch64/cortex_a53.S`` 1381exports the ``cpu_ops`` for Cortex-A53 CPU. According to the platform 1382configuration, these CPU specific files must be included in the build by 1383the platform makefile. The generic CPU specific operations framework code exists 1384in ``lib/cpus/aarch64/cpu_helpers.S``. 1385 1386CPU specific Reset Handling 1387~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1388 1389After a reset, the state of the CPU when it calls generic reset handler is: 1390MMU turned off, both instruction and data caches turned off and not part 1391of any coherency domain. 1392 1393The BL entrypoint code first invokes the ``plat_reset_handler()`` to allow 1394the platform to perform any system initialization required and any system 1395errata workarounds that needs to be applied. The ``get_cpu_ops_ptr()`` reads 1396the current CPU midr, finds the matching ``cpu_ops`` entry in the ``cpu_ops`` 1397array and returns it. Note that only the part number and implementer fields 1398in midr are used to find the matching ``cpu_ops`` entry. The ``reset_func()`` in 1399the returned ``cpu_ops`` is then invoked which executes the required reset 1400handling for that CPU and also any errata workarounds enabled by the platform. 1401This function must preserve the values of general purpose registers x20 to x29. 1402 1403Refer to Section "Guidelines for Reset Handlers" for general guidelines 1404regarding placement of code in a reset handler. 1405 1406CPU specific power down sequence 1407~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1408 1409During the BL31 initialization sequence, the pointer to the matching ``cpu_ops`` 1410entry is stored in per-CPU data by ``init_cpu_ops()`` so that it can be quickly 1411retrieved during power down sequences. 1412 1413Various CPU drivers register handlers to perform power down at certain power 1414levels for that specific CPU. The PSCI service, upon receiving a power down 1415request, determines the highest power level at which to execute power down 1416sequence for a particular CPU. It uses the ``prepare_cpu_pwr_dwn()`` function to 1417pick the right power down handler for the requested level. The function 1418retrieves ``cpu_ops`` pointer member of per-CPU data, and from that, further 1419retrieves ``cpu_pwr_down_ops`` array, and indexes into the required level. If the 1420requested power level is higher than what a CPU driver supports, the handler 1421registered for highest level is invoked. 1422 1423At runtime the platform hooks for power down are invoked by the PSCI service to 1424perform platform specific operations during a power down sequence, for example 1425turning off CCI coherency during a cluster power down. 1426 1427CPU specific register reporting during crash 1428~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1429 1430If the crash reporting is enabled in BL31, when a crash occurs, the crash 1431reporting framework calls ``do_cpu_reg_dump`` which retrieves the matching 1432``cpu_ops`` using ``get_cpu_ops_ptr()`` function. The ``cpu_reg_dump()`` in 1433``cpu_ops`` is invoked, which then returns the CPU specific register values to 1434be reported and a pointer to the ASCII list of register names in a format 1435expected by the crash reporting framework. 1436 1437.. _firmware_design_cpu_errata_reporting: 1438 1439CPU errata status reporting 1440~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1441 1442Errata workarounds for CPUs supported in TF-A are applied during both cold and 1443warm boots, shortly after reset. Individual Errata workarounds are enabled as 1444build options. Some errata workarounds have potential run-time implications; 1445therefore some are enabled by default, others not. Platform ports shall 1446override build options to enable or disable errata as appropriate. The CPU 1447drivers take care of applying errata workarounds that are enabled and applicable 1448to a given CPU. Refer to :ref:`arm_cpu_macros_errata_workarounds` for more 1449information. 1450 1451Functions in CPU drivers that apply errata workaround must follow the 1452conventions listed below. 1453 1454The errata workaround must be authored as two separate functions: 1455 1456- One that checks for errata. This function must determine whether that errata 1457 applies to the current CPU. Typically this involves matching the current 1458 CPUs revision and variant against a value that's known to be affected by the 1459 errata. If the function determines that the errata applies to this CPU, it 1460 must return ``ERRATA_APPLIES``; otherwise, it must return 1461 ``ERRATA_NOT_APPLIES``. The utility functions ``cpu_get_rev_var`` and 1462 ``cpu_rev_var_ls`` functions may come in handy for this purpose. 1463 1464For an errata identified as ``E``, the check function must be named 1465``check_errata_E``. 1466 1467This function will be invoked at different times, both from assembly and from 1468C run time. Therefore it must follow AAPCS, and must not use stack. 1469 1470- Another one that applies the errata workaround. This function would call the 1471 check function described above, and applies errata workaround if required. 1472 1473CPU drivers that apply errata workaround can optionally implement an assembly 1474function that report the status of errata workarounds pertaining to that CPU. 1475For a driver that registers the CPU, for example, ``cpux`` via ``declare_cpu_ops`` 1476macro, the errata reporting function, if it exists, must be named 1477``cpux_errata_report``. This function will always be called with MMU enabled; it 1478must follow AAPCS and may use stack. 1479 1480In a debug build of TF-A, on a CPU that comes out of reset, both BL1 and the 1481runtime firmware (BL31 in AArch64, and BL32 in AArch32) will invoke errata 1482status reporting function, if one exists, for that type of CPU. 1483 1484To report the status of each errata workaround, the function shall use the 1485assembler macro ``report_errata``, passing it: 1486 1487- The build option that enables the errata; 1488 1489- The name of the CPU: this must be the same identifier that CPU driver 1490 registered itself with, using ``declare_cpu_ops``; 1491 1492- And the errata identifier: the identifier must match what's used in the 1493 errata's check function described above. 1494 1495The errata status reporting function will be called once per CPU type/errata 1496combination during the software's active life time. 1497 1498It's expected that whenever an errata workaround is submitted to TF-A, the 1499errata reporting function is appropriately extended to report its status as 1500well. 1501 1502Reporting the status of errata workaround is for informational purpose only; it 1503has no functional significance. 1504 1505Memory layout of BL images 1506-------------------------- 1507 1508Each bootloader image can be divided in 2 parts: 1509 1510- the static contents of the image. These are data actually stored in the 1511 binary on the disk. In the ELF terminology, they are called ``PROGBITS`` 1512 sections; 1513 1514- the run-time contents of the image. These are data that don't occupy any 1515 space in the binary on the disk. The ELF binary just contains some 1516 metadata indicating where these data will be stored at run-time and the 1517 corresponding sections need to be allocated and initialized at run-time. 1518 In the ELF terminology, they are called ``NOBITS`` sections. 1519 1520All PROGBITS sections are grouped together at the beginning of the image, 1521followed by all NOBITS sections. This is true for all TF-A images and it is 1522governed by the linker scripts. This ensures that the raw binary images are 1523as small as possible. If a NOBITS section was inserted in between PROGBITS 1524sections then the resulting binary file would contain zero bytes in place of 1525this NOBITS section, making the image unnecessarily bigger. Smaller images 1526allow faster loading from the FIP to the main memory. 1527 1528For BL31, a platform can specify an alternate location for NOBITS sections 1529(other than immediately following PROGBITS sections) by setting 1530``SEPARATE_NOBITS_REGION`` to 1 and defining ``BL31_NOBITS_BASE`` and 1531``BL31_NOBITS_LIMIT``. 1532 1533Linker scripts and symbols 1534~~~~~~~~~~~~~~~~~~~~~~~~~~ 1535 1536Each bootloader stage image layout is described by its own linker script. The 1537linker scripts export some symbols into the program symbol table. Their values 1538correspond to particular addresses. TF-A code can refer to these symbols to 1539figure out the image memory layout. 1540 1541Linker symbols follow the following naming convention in TF-A. 1542 1543- ``__<SECTION>_START__`` 1544 1545 Start address of a given section named ``<SECTION>``. 1546 1547- ``__<SECTION>_END__`` 1548 1549 End address of a given section named ``<SECTION>``. If there is an alignment 1550 constraint on the section's end address then ``__<SECTION>_END__`` corresponds 1551 to the end address of the section's actual contents, rounded up to the right 1552 boundary. Refer to the value of ``__<SECTION>_UNALIGNED_END__`` to know the 1553 actual end address of the section's contents. 1554 1555- ``__<SECTION>_UNALIGNED_END__`` 1556 1557 End address of a given section named ``<SECTION>`` without any padding or 1558 rounding up due to some alignment constraint. 1559 1560- ``__<SECTION>_SIZE__`` 1561 1562 Size (in bytes) of a given section named ``<SECTION>``. If there is an 1563 alignment constraint on the section's end address then ``__<SECTION>_SIZE__`` 1564 corresponds to the size of the section's actual contents, rounded up to the 1565 right boundary. In other words, ``__<SECTION>_SIZE__ = __<SECTION>_END__ - _<SECTION>_START__``. Refer to the value of ``__<SECTION>_UNALIGNED_SIZE__`` 1566 to know the actual size of the section's contents. 1567 1568- ``__<SECTION>_UNALIGNED_SIZE__`` 1569 1570 Size (in bytes) of a given section named ``<SECTION>`` without any padding or 1571 rounding up due to some alignment constraint. In other words, 1572 ``__<SECTION>_UNALIGNED_SIZE__ = __<SECTION>_UNALIGNED_END__ - __<SECTION>_START__``. 1573 1574Some of the linker symbols are mandatory as TF-A code relies on them to be 1575defined. They are listed in the following subsections. Some of them must be 1576provided for each bootloader stage and some are specific to a given bootloader 1577stage. 1578 1579The linker scripts define some extra, optional symbols. They are not actually 1580used by any code but they help in understanding the bootloader images' memory 1581layout as they are easy to spot in the link map files. 1582 1583Common linker symbols 1584^^^^^^^^^^^^^^^^^^^^^ 1585 1586All BL images share the following requirements: 1587 1588- The BSS section must be zero-initialised before executing any C code. 1589- The coherent memory section (if enabled) must be zero-initialised as well. 1590- The MMU setup code needs to know the extents of the coherent and read-only 1591 memory regions to set the right memory attributes. When 1592 ``SEPARATE_CODE_AND_RODATA=1``, it needs to know more specifically how the 1593 read-only memory region is divided between code and data. 1594 1595The following linker symbols are defined for this purpose: 1596 1597- ``__BSS_START__`` 1598- ``__BSS_SIZE__`` 1599- ``__COHERENT_RAM_START__`` Must be aligned on a page-size boundary. 1600- ``__COHERENT_RAM_END__`` Must be aligned on a page-size boundary. 1601- ``__COHERENT_RAM_UNALIGNED_SIZE__`` 1602- ``__RO_START__`` 1603- ``__RO_END__`` 1604- ``__TEXT_START__`` 1605- ``__TEXT_END__`` 1606- ``__RODATA_START__`` 1607- ``__RODATA_END__`` 1608 1609BL1's linker symbols 1610^^^^^^^^^^^^^^^^^^^^ 1611 1612BL1 being the ROM image, it has additional requirements. BL1 resides in ROM and 1613it is entirely executed in place but it needs some read-write memory for its 1614mutable data. Its ``.data`` section (i.e. its allocated read-write data) must be 1615relocated from ROM to RAM before executing any C code. 1616 1617The following additional linker symbols are defined for BL1: 1618 1619- ``__BL1_ROM_END__`` End address of BL1's ROM contents, covering its code 1620 and ``.data`` section in ROM. 1621- ``__DATA_ROM_START__`` Start address of the ``.data`` section in ROM. Must be 1622 aligned on a 16-byte boundary. 1623- ``__DATA_RAM_START__`` Address in RAM where the ``.data`` section should be 1624 copied over. Must be aligned on a 16-byte boundary. 1625- ``__DATA_SIZE__`` Size of the ``.data`` section (in ROM or RAM). 1626- ``__BL1_RAM_START__`` Start address of BL1 read-write data. 1627- ``__BL1_RAM_END__`` End address of BL1 read-write data. 1628 1629How to choose the right base addresses for each bootloader stage image 1630~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1631 1632There is currently no support for dynamic image loading in TF-A. This means 1633that all bootloader images need to be linked against their ultimate runtime 1634locations and the base addresses of each image must be chosen carefully such 1635that images don't overlap each other in an undesired way. As the code grows, 1636the base addresses might need adjustments to cope with the new memory layout. 1637 1638The memory layout is completely specific to the platform and so there is no 1639general recipe for choosing the right base addresses for each bootloader image. 1640However, there are tools to aid in understanding the memory layout. These are 1641the link map files: ``build/<platform>/<build-type>/bl<x>/bl<x>.map``, with ``<x>`` 1642being the stage bootloader. They provide a detailed view of the memory usage of 1643each image. Among other useful information, they provide the end address of 1644each image. 1645 1646- ``bl1.map`` link map file provides ``__BL1_RAM_END__`` address. 1647- ``bl2.map`` link map file provides ``__BL2_END__`` address. 1648- ``bl31.map`` link map file provides ``__BL31_END__`` address. 1649- ``bl32.map`` link map file provides ``__BL32_END__`` address. 1650 1651For each bootloader image, the platform code must provide its start address 1652as well as a limit address that it must not overstep. The latter is used in the 1653linker scripts to check that the image doesn't grow past that address. If that 1654happens, the linker will issue a message similar to the following: 1655 1656:: 1657 1658 aarch64-none-elf-ld: BLx has exceeded its limit. 1659 1660Additionally, if the platform memory layout implies some image overlaying like 1661on FVP, BL31 and TSP need to know the limit address that their PROGBITS 1662sections must not overstep. The platform code must provide those. 1663 1664TF-A does not provide any mechanism to verify at boot time that the memory 1665to load a new image is free to prevent overwriting a previously loaded image. 1666The platform must specify the memory available in the system for all the 1667relevant BL images to be loaded. 1668 1669For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will 1670return the region defined by the platform where BL1 intends to load BL2. The 1671``load_image()`` function performs bounds check for the image size based on the 1672base and maximum image size provided by the platforms. Platforms must take 1673this behaviour into account when defining the base/size for each of the images. 1674 1675Memory layout on Arm development platforms 1676^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1677 1678The following list describes the memory layout on the Arm development platforms: 1679 1680- A 4KB page of shared memory is used for communication between Trusted 1681 Firmware and the platform's power controller. This is located at the base of 1682 Trusted SRAM. The amount of Trusted SRAM available to load the bootloader 1683 images is reduced by the size of the shared memory. 1684 1685 The shared memory is used to store the CPUs' entrypoint mailbox. On Juno, 1686 this is also used for the MHU payload when passing messages to and from the 1687 SCP. 1688 1689- Another 4 KB page is reserved for passing memory layout between BL1 and BL2 1690 and also the dynamic firmware configurations. 1691 1692- On FVP, BL1 is originally sitting in the Trusted ROM at address ``0x0``. On 1693 Juno, BL1 resides in flash memory at address ``0x0BEC0000``. BL1 read-write 1694 data are relocated to the top of Trusted SRAM at runtime. 1695 1696- BL2 is loaded below BL1 RW 1697 1698- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP_MIN), 1699 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will 1700 overwrite BL1 R/W data and BL2. This implies that BL1 global variables 1701 remain valid only until execution reaches the EL3 Runtime Software entry 1702 point during a cold boot. 1703 1704- On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory 1705 region and transferred to the SCP before being overwritten by EL3 Runtime 1706 Software. 1707 1708- BL32 (for AArch64) can be loaded in one of the following locations: 1709 1710 - Trusted SRAM 1711 - Trusted DRAM (FVP only) 1712 - Secure region of DRAM (top 16MB of DRAM configured by the TrustZone 1713 controller) 1714 1715 When BL32 (for AArch64) is loaded into Trusted SRAM, it is loaded below 1716 BL31. 1717 1718The location of the BL32 image will result in different memory maps. This is 1719illustrated for both FVP and Juno in the following diagrams, using the TSP as 1720an example. 1721 1722.. note:: 1723 Loading the BL32 image in TZC secured DRAM doesn't change the memory 1724 layout of the other images in Trusted SRAM. 1725 1726CONFIG section in memory layouts shown below contains: 1727 1728:: 1729 1730 +--------------------+ 1731 |bl2_mem_params_descs| 1732 |--------------------| 1733 | fw_configs | 1734 +--------------------+ 1735 1736``bl2_mem_params_descs`` contains parameters passed from BL2 to next the 1737BL image during boot. 1738 1739``fw_configs`` includes soc_fw_config, tos_fw_config, tb_fw_config and fw_config. 1740 1741**FVP with TSP in Trusted SRAM with firmware configs :** 1742(These diagrams only cover the AArch64 case) 1743 1744:: 1745 1746 DRAM 1747 0xffffffff +----------+ 1748 : : 1749 |----------| 1750 |HW_CONFIG | 1751 0x83000000 |----------| (non-secure) 1752 | | 1753 0x80000000 +----------+ 1754 1755 Trusted SRAM 1756 0x04040000 +----------+ loaded by BL2 +----------------+ 1757 | BL1 (rw) | <<<<<<<<<<<<< | | 1758 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1759 | BL2 | <<<<<<<<<<<<< | | 1760 |----------| <<<<<<<<<<<<< |----------------| 1761 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1762 | | <<<<<<<<<<<<< |----------------| 1763 | | <<<<<<<<<<<<< | BL32 | 1764 0x04003000 +----------+ +----------------+ 1765 | CONFIG | 1766 0x04001000 +----------+ 1767 | Shared | 1768 0x04000000 +----------+ 1769 1770 Trusted ROM 1771 0x04000000 +----------+ 1772 | BL1 (ro) | 1773 0x00000000 +----------+ 1774 1775**FVP with TSP in Trusted DRAM with firmware configs (default option):** 1776 1777:: 1778 1779 DRAM 1780 0xffffffff +--------------+ 1781 : : 1782 |--------------| 1783 | HW_CONFIG | 1784 0x83000000 |--------------| (non-secure) 1785 | | 1786 0x80000000 +--------------+ 1787 1788 Trusted DRAM 1789 0x08000000 +--------------+ 1790 | BL32 | 1791 0x06000000 +--------------+ 1792 1793 Trusted SRAM 1794 0x04040000 +--------------+ loaded by BL2 +----------------+ 1795 | BL1 (rw) | <<<<<<<<<<<<< | | 1796 |--------------| <<<<<<<<<<<<< | BL31 NOBITS | 1797 | BL2 | <<<<<<<<<<<<< | | 1798 |--------------| <<<<<<<<<<<<< |----------------| 1799 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1800 | | +----------------+ 1801 0x04003000 +--------------+ 1802 | CONFIG | 1803 0x04001000 +--------------+ 1804 | Shared | 1805 0x04000000 +--------------+ 1806 1807 Trusted ROM 1808 0x04000000 +--------------+ 1809 | BL1 (ro) | 1810 0x00000000 +--------------+ 1811 1812**FVP with TSP in TZC-Secured DRAM with firmware configs :** 1813 1814:: 1815 1816 DRAM 1817 0xffffffff +----------+ 1818 | BL32 | (secure) 1819 0xff000000 +----------+ 1820 | | 1821 |----------| 1822 |HW_CONFIG | 1823 0x83000000 |----------| (non-secure) 1824 | | 1825 0x80000000 +----------+ 1826 1827 Trusted SRAM 1828 0x04040000 +----------+ loaded by BL2 +----------------+ 1829 | BL1 (rw) | <<<<<<<<<<<<< | | 1830 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1831 | BL2 | <<<<<<<<<<<<< | | 1832 |----------| <<<<<<<<<<<<< |----------------| 1833 | | <<<<<<<<<<<<< | BL31 PROGBITS | 1834 | | +----------------+ 1835 0x04003000 +----------+ 1836 | CONFIG | 1837 0x04001000 +----------+ 1838 | Shared | 1839 0x04000000 +----------+ 1840 1841 Trusted ROM 1842 0x04000000 +----------+ 1843 | BL1 (ro) | 1844 0x00000000 +----------+ 1845 1846**Juno with BL32 in Trusted SRAM :** 1847 1848:: 1849 1850 Flash0 1851 0x0C000000 +----------+ 1852 : : 1853 0x0BED0000 |----------| 1854 | BL1 (ro) | 1855 0x0BEC0000 |----------| 1856 : : 1857 0x08000000 +----------+ BL31 is loaded 1858 after SCP_BL2 has 1859 Trusted SRAM been sent to SCP 1860 0x04040000 +----------+ loaded by BL2 +----------------+ 1861 | BL1 (rw) | <<<<<<<<<<<<< | | 1862 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1863 | BL2 | <<<<<<<<<<<<< | | 1864 |----------| <<<<<<<<<<<<< |----------------| 1865 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 1866 | | <<<<<<<<<<<<< |----------------| 1867 | | <<<<<<<<<<<<< | BL32 | 1868 | | +----------------+ 1869 | | 1870 0x04001000 +----------+ 1871 | MHU | 1872 0x04000000 +----------+ 1873 1874**Juno with BL32 in TZC-secured DRAM :** 1875 1876:: 1877 1878 DRAM 1879 0xFFE00000 +----------+ 1880 | BL32 | (secure) 1881 0xFF000000 |----------| 1882 | | 1883 : : (non-secure) 1884 | | 1885 0x80000000 +----------+ 1886 1887 Flash0 1888 0x0C000000 +----------+ 1889 : : 1890 0x0BED0000 |----------| 1891 | BL1 (ro) | 1892 0x0BEC0000 |----------| 1893 : : 1894 0x08000000 +----------+ BL31 is loaded 1895 after SCP_BL2 has 1896 Trusted SRAM been sent to SCP 1897 0x04040000 +----------+ loaded by BL2 +----------------+ 1898 | BL1 (rw) | <<<<<<<<<<<<< | | 1899 |----------| <<<<<<<<<<<<< | BL31 NOBITS | 1900 | BL2 | <<<<<<<<<<<<< | | 1901 |----------| <<<<<<<<<<<<< |----------------| 1902 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | 1903 | | +----------------+ 1904 0x04001000 +----------+ 1905 | MHU | 1906 0x04000000 +----------+ 1907 1908.. _firmware_design_fip: 1909 1910Firmware Image Package (FIP) 1911---------------------------- 1912 1913Using a Firmware Image Package (FIP) allows for packing bootloader images (and 1914potentially other payloads) into a single archive that can be loaded by TF-A 1915from non-volatile platform storage. A driver to load images from a FIP has 1916been added to the storage layer and allows a package to be read from supported 1917platform storage. A tool to create Firmware Image Packages is also provided 1918and described below. 1919 1920Firmware Image Package layout 1921~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1922 1923The FIP layout consists of a table of contents (ToC) followed by payload data. 1924The ToC itself has a header followed by one or more table entries. The ToC is 1925terminated by an end marker entry, and since the size of the ToC is 0 bytes, 1926the offset equals the total size of the FIP file. All ToC entries describe some 1927payload data that has been appended to the end of the binary package. With the 1928information provided in the ToC entry the corresponding payload data can be 1929retrieved. 1930 1931:: 1932 1933 ------------------ 1934 | ToC Header | 1935 |----------------| 1936 | ToC Entry 0 | 1937 |----------------| 1938 | ToC Entry 1 | 1939 |----------------| 1940 | ToC End Marker | 1941 |----------------| 1942 | | 1943 | Data 0 | 1944 | | 1945 |----------------| 1946 | | 1947 | Data 1 | 1948 | | 1949 ------------------ 1950 1951The ToC header and entry formats are described in the header file 1952``include/tools_share/firmware_image_package.h``. This file is used by both the 1953tool and TF-A. 1954 1955The ToC header has the following fields: 1956 1957:: 1958 1959 `name`: The name of the ToC. This is currently used to validate the header. 1960 `serial_number`: A non-zero number provided by the creation tool 1961 `flags`: Flags associated with this data. 1962 Bits 0-31: Reserved 1963 Bits 32-47: Platform defined 1964 Bits 48-63: Reserved 1965 1966A ToC entry has the following fields: 1967 1968:: 1969 1970 `uuid`: All files are referred to by a pre-defined Universally Unique 1971 IDentifier [UUID] . The UUIDs are defined in 1972 `include/tools_share/firmware_image_package.h`. The platform translates 1973 the requested image name into the corresponding UUID when accessing the 1974 package. 1975 `offset_address`: The offset address at which the corresponding payload data 1976 can be found. The offset is calculated from the ToC base address. 1977 `size`: The size of the corresponding payload data in bytes. 1978 `flags`: Flags associated with this entry. None are yet defined. 1979 1980Firmware Image Package creation tool 1981~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1982 1983The FIP creation tool can be used to pack specified images into a binary 1984package that can be loaded by TF-A from platform storage. The tool currently 1985only supports packing bootloader images. Additional image definitions can be 1986added to the tool as required. 1987 1988The tool can be found in ``tools/fiptool``. 1989 1990Loading from a Firmware Image Package (FIP) 1991~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1992 1993The Firmware Image Package (FIP) driver can load images from a binary package on 1994non-volatile platform storage. For the Arm development platforms, this is 1995currently NOR FLASH. 1996 1997Bootloader images are loaded according to the platform policy as specified by 1998the function ``plat_get_image_source()``. For the Arm development platforms, this 1999means the platform will attempt to load images from a Firmware Image Package 2000located at the start of NOR FLASH0. 2001 2002The Arm development platforms' policy is to only allow loading of a known set of 2003images. The platform policy can be modified to allow additional images. 2004 2005Use of coherent memory in TF-A 2006------------------------------ 2007 2008There might be loss of coherency when physical memory with mismatched 2009shareability, cacheability and memory attributes is accessed by multiple CPUs 2010(refer to section B2.9 of `Arm ARM`_ for more details). This possibility occurs 2011in TF-A during power up/down sequences when coherency, MMU and caches are 2012turned on/off incrementally. 2013 2014TF-A defines coherent memory as a region of memory with Device nGnRE attributes 2015in the translation tables. The translation granule size in TF-A is 4KB. This 2016is the smallest possible size of the coherent memory region. 2017 2018By default, all data structures which are susceptible to accesses with 2019mismatched attributes from various CPUs are allocated in a coherent memory 2020region (refer to section 2.1 of :ref:`Porting Guide`). The coherent memory 2021region accesses are Outer Shareable, non-cacheable and they can be accessed with 2022the Device nGnRE attributes when the MMU is turned on. Hence, at the expense of 2023at least an extra page of memory, TF-A is able to work around coherency issues 2024due to mismatched memory attributes. 2025 2026The alternative to the above approach is to allocate the susceptible data 2027structures in Normal WriteBack WriteAllocate Inner shareable memory. This 2028approach requires the data structures to be designed so that it is possible to 2029work around the issue of mismatched memory attributes by performing software 2030cache maintenance on them. 2031 2032Disabling the use of coherent memory in TF-A 2033~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2034 2035It might be desirable to avoid the cost of allocating coherent memory on 2036platforms which are memory constrained. TF-A enables inclusion of coherent 2037memory in firmware images through the build flag ``USE_COHERENT_MEM``. 2038This flag is enabled by default. It can be disabled to choose the second 2039approach described above. 2040 2041The below sections analyze the data structures allocated in the coherent memory 2042region and the changes required to allocate them in normal memory. 2043 2044Coherent memory usage in PSCI implementation 2045~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2046 2047The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain 2048tree information for state management of power domains. By default, this data 2049structure is allocated in the coherent memory region in TF-A because it can be 2050accessed by multiple CPUs, either with caches enabled or disabled. 2051 2052.. code:: c 2053 2054 typedef struct non_cpu_pwr_domain_node { 2055 /* 2056 * Index of the first CPU power domain node level 0 which has this node 2057 * as its parent. 2058 */ 2059 unsigned int cpu_start_idx; 2060 2061 /* 2062 * Number of CPU power domains which are siblings of the domain indexed 2063 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx 2064 * -> cpu_start_idx + ncpus' have this node as their parent. 2065 */ 2066 unsigned int ncpus; 2067 2068 /* 2069 * Index of the parent power domain node. 2070 */ 2071 unsigned int parent_node; 2072 2073 plat_local_state_t local_state; 2074 2075 unsigned char level; 2076 2077 /* For indexing the psci_lock array*/ 2078 unsigned char lock_index; 2079 } non_cpu_pd_node_t; 2080 2081In order to move this data structure to normal memory, the use of each of its 2082fields must be analyzed. Fields like ``cpu_start_idx``, ``ncpus``, ``parent_node`` 2083``level`` and ``lock_index`` are only written once during cold boot. Hence removing 2084them from coherent memory involves only doing a clean and invalidate of the 2085cache lines after these fields are written. 2086 2087The field ``local_state`` can be concurrently accessed by multiple CPUs in 2088different cache states. A Lamport's Bakery lock ``psci_locks`` is used to ensure 2089mutual exclusion to this field and a clean and invalidate is needed after it 2090is written. 2091 2092Bakery lock data 2093~~~~~~~~~~~~~~~~ 2094 2095The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory 2096and is accessed by multiple CPUs with mismatched attributes. ``bakery_lock_t`` is 2097defined as follows: 2098 2099.. code:: c 2100 2101 typedef struct bakery_lock { 2102 /* 2103 * The lock_data is a bit-field of 2 members: 2104 * Bit[0] : choosing. This field is set when the CPU is 2105 * choosing its bakery number. 2106 * Bits[1 - 15] : number. This is the bakery number allocated. 2107 */ 2108 volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS]; 2109 } bakery_lock_t; 2110 2111It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU 2112fields can be read by all CPUs but only written to by the owning CPU. 2113 2114Depending upon the data cache line size, the per-CPU fields of the 2115``bakery_lock_t`` structure for multiple CPUs may exist on a single cache line. 2116These per-CPU fields can be read and written during lock contention by multiple 2117CPUs with mismatched memory attributes. Since these fields are a part of the 2118lock implementation, they do not have access to any other locking primitive to 2119safeguard against the resulting coherency issues. As a result, simple software 2120cache maintenance is not enough to allocate them in coherent memory. Consider 2121the following example. 2122 2123CPU0 updates its per-CPU field with data cache enabled. This write updates a 2124local cache line which contains a copy of the fields for other CPUs as well. Now 2125CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache 2126disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of 2127its field in any other cache line in the system. This operation will invalidate 2128the update made by CPU0 as well. 2129 2130To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure 2131has been redesigned. The changes utilise the characteristic of Lamport's Bakery 2132algorithm mentioned earlier. The bakery_lock structure only allocates the memory 2133for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks 2134needed for a CPU into a section ``bakery_lock``. The linker allocates the memory 2135for other cores by using the total size allocated for the bakery_lock section 2136and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to 2137perform software cache maintenance on the lock data structure without running 2138into coherency issues associated with mismatched attributes. 2139 2140The bakery lock data structure ``bakery_info_t`` is defined for use when 2141``USE_COHERENT_MEM`` is disabled as follows: 2142 2143.. code:: c 2144 2145 typedef struct bakery_info { 2146 /* 2147 * The lock_data is a bit-field of 2 members: 2148 * Bit[0] : choosing. This field is set when the CPU is 2149 * choosing its bakery number. 2150 * Bits[1 - 15] : number. This is the bakery number allocated. 2151 */ 2152 volatile uint16_t lock_data; 2153 } bakery_info_t; 2154 2155The ``bakery_info_t`` represents a single per-CPU field of one lock and 2156the combination of corresponding ``bakery_info_t`` structures for all CPUs in the 2157system represents the complete bakery lock. The view in memory for a system 2158with n bakery locks are: 2159 2160:: 2161 2162 bakery_lock section start 2163 |----------------| 2164 | `bakery_info_t`| <-- Lock_0 per-CPU field 2165 | Lock_0 | for CPU0 2166 |----------------| 2167 | `bakery_info_t`| <-- Lock_1 per-CPU field 2168 | Lock_1 | for CPU0 2169 |----------------| 2170 | .... | 2171 |----------------| 2172 | `bakery_info_t`| <-- Lock_N per-CPU field 2173 | Lock_N | for CPU0 2174 ------------------ 2175 | XXXXX | 2176 | Padding to | 2177 | next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate 2178 | Granule | continuous memory for remaining CPUs. 2179 ------------------ 2180 | `bakery_info_t`| <-- Lock_0 per-CPU field 2181 | Lock_0 | for CPU1 2182 |----------------| 2183 | `bakery_info_t`| <-- Lock_1 per-CPU field 2184 | Lock_1 | for CPU1 2185 |----------------| 2186 | .... | 2187 |----------------| 2188 | `bakery_info_t`| <-- Lock_N per-CPU field 2189 | Lock_N | for CPU1 2190 ------------------ 2191 | XXXXX | 2192 | Padding to | 2193 | next Cache WB | 2194 | Granule | 2195 ------------------ 2196 2197Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an 2198operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1 2199``bakery_lock`` section need to be fetched and appropriate cache operations need 2200to be performed for each access. 2201 2202On Arm Platforms, bakery locks are used in psci (``psci_locks``) and power controller 2203driver (``arm_lock``). 2204 2205Non Functional Impact of removing coherent memory 2206~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2207 2208Removal of the coherent memory region leads to the additional software overhead 2209of performing cache maintenance for the affected data structures. However, since 2210the memory where the data structures are allocated is cacheable, the overhead is 2211mostly mitigated by an increase in performance. 2212 2213There is however a performance impact for bakery locks, due to: 2214 2215- Additional cache maintenance operations, and 2216- Multiple cache line reads for each lock operation, since the bakery locks 2217 for each CPU are distributed across different cache lines. 2218 2219The implementation has been optimized to minimize this additional overhead. 2220Measurements indicate that when bakery locks are allocated in Normal memory, the 2221minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas 2222in Device memory the same is 2 micro seconds. The measurements were done on the 2223Juno Arm development platform. 2224 2225As mentioned earlier, almost a page of memory can be saved by disabling 2226``USE_COHERENT_MEM``. Each platform needs to consider these trade-offs to decide 2227whether coherent memory should be used. If a platform disables 2228``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can 2229optionally define macro ``PLAT_PERCPU_BAKERY_LOCK_SIZE`` (see the 2230:ref:`Porting Guide`). Refer to the reference platform code for examples. 2231 2232Isolating code and read-only data on separate memory pages 2233---------------------------------------------------------- 2234 2235In the Armv8-A VMSA, translation table entries include fields that define the 2236properties of the target memory region, such as its access permissions. The 2237smallest unit of memory that can be addressed by a translation table entry is 2238a memory page. Therefore, if software needs to set different permissions on two 2239memory regions then it needs to map them using different memory pages. 2240 2241The default memory layout for each BL image is as follows: 2242 2243:: 2244 2245 | ... | 2246 +-------------------+ 2247 | Read-write data | 2248 +-------------------+ Page boundary 2249 | <Padding> | 2250 +-------------------+ 2251 | Exception vectors | 2252 +-------------------+ 2 KB boundary 2253 | <Padding> | 2254 +-------------------+ 2255 | Read-only data | 2256 +-------------------+ 2257 | Code | 2258 +-------------------+ BLx_BASE 2259 2260.. note:: 2261 The 2KB alignment for the exception vectors is an architectural 2262 requirement. 2263 2264The read-write data start on a new memory page so that they can be mapped with 2265read-write permissions, whereas the code and read-only data below are configured 2266as read-only. 2267 2268However, the read-only data are not aligned on a page boundary. They are 2269contiguous to the code. Therefore, the end of the code section and the beginning 2270of the read-only data one might share a memory page. This forces both to be 2271mapped with the same memory attributes. As the code needs to be executable, this 2272means that the read-only data stored on the same memory page as the code are 2273executable as well. This could potentially be exploited as part of a security 2274attack. 2275 2276TF provides the build flag ``SEPARATE_CODE_AND_RODATA`` to isolate the code and 2277read-only data on separate memory pages. This in turn allows independent control 2278of the access permissions for the code and read-only data. In this case, 2279platform code gets a finer-grained view of the image layout and can 2280appropriately map the code region as executable and the read-only data as 2281execute-never. 2282 2283This has an impact on memory footprint, as padding bytes need to be introduced 2284between the code and read-only data to ensure the segregation of the two. To 2285limit the memory cost, this flag also changes the memory layout such that the 2286code and exception vectors are now contiguous, like so: 2287 2288:: 2289 2290 | ... | 2291 +-------------------+ 2292 | Read-write data | 2293 +-------------------+ Page boundary 2294 | <Padding> | 2295 +-------------------+ 2296 | Read-only data | 2297 +-------------------+ Page boundary 2298 | <Padding> | 2299 +-------------------+ 2300 | Exception vectors | 2301 +-------------------+ 2 KB boundary 2302 | <Padding> | 2303 +-------------------+ 2304 | Code | 2305 +-------------------+ BLx_BASE 2306 2307With this more condensed memory layout, the separation of read-only data will 2308add zero or one page to the memory footprint of each BL image. Each platform 2309should consider the trade-off between memory footprint and security. 2310 2311This build flag is disabled by default, minimising memory footprint. On Arm 2312platforms, it is enabled. 2313 2314Publish and Subscribe Framework 2315------------------------------- 2316 2317The Publish and Subscribe Framework allows EL3 components to define and publish 2318events, to which other EL3 components can subscribe. 2319 2320The following macros are provided by the framework: 2321 2322- ``REGISTER_PUBSUB_EVENT(event)``: Defines an event, and takes one argument, 2323 the event name, which must be a valid C identifier. All calls to 2324 ``REGISTER_PUBSUB_EVENT`` macro must be placed in the file 2325 ``pubsub_events.h``. 2326 2327- ``PUBLISH_EVENT_ARG(event, arg)``: Publishes a defined event, by iterating 2328 subscribed handlers and calling them in turn. The handlers will be passed the 2329 parameter ``arg``. The expected use-case is to broadcast an event. 2330 2331- ``PUBLISH_EVENT(event)``: Like ``PUBLISH_EVENT_ARG``, except that the value 2332 ``NULL`` is passed to subscribed handlers. 2333 2334- ``SUBSCRIBE_TO_EVENT(event, handler)``: Registers the ``handler`` to 2335 subscribe to ``event``. The handler will be executed whenever the ``event`` 2336 is published. 2337 2338- ``for_each_subscriber(event, subscriber)``: Iterates through all handlers 2339 subscribed for ``event``. ``subscriber`` must be a local variable of type 2340 ``pubsub_cb_t *``, and will point to each subscribed handler in turn during 2341 iteration. This macro can be used for those patterns that none of the 2342 ``PUBLISH_EVENT_*()`` macros cover. 2343 2344Publishing an event that wasn't defined using ``REGISTER_PUBSUB_EVENT`` will 2345result in build error. Subscribing to an undefined event however won't. 2346 2347Subscribed handlers must be of type ``pubsub_cb_t``, with following function 2348signature: 2349 2350.. code:: c 2351 2352 typedef void* (*pubsub_cb_t)(const void *arg); 2353 2354There may be arbitrary number of handlers registered to the same event. The 2355order in which subscribed handlers are notified when that event is published is 2356not defined. Subscribed handlers may be executed in any order; handlers should 2357not assume any relative ordering amongst them. 2358 2359Publishing an event on a PE will result in subscribed handlers executing on that 2360PE only; it won't cause handlers to execute on a different PE. 2361 2362Note that publishing an event on a PE blocks until all the subscribed handlers 2363finish executing on the PE. 2364 2365TF-A generic code publishes and subscribes to some events within. Platform 2366ports are discouraged from subscribing to them. These events may be withdrawn, 2367renamed, or have their semantics altered in the future. Platforms may however 2368register, publish, and subscribe to platform-specific events. 2369 2370Publish and Subscribe Example 2371~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2372 2373A publisher that wants to publish event ``foo`` would: 2374 2375- Define the event ``foo`` in the ``pubsub_events.h``. 2376 2377 .. code:: c 2378 2379 REGISTER_PUBSUB_EVENT(foo); 2380 2381- Depending on the nature of event, use one of ``PUBLISH_EVENT_*()`` macros to 2382 publish the event at the appropriate path and time of execution. 2383 2384A subscriber that wants to subscribe to event ``foo`` published above would 2385implement: 2386 2387.. code:: c 2388 2389 void *foo_handler(const void *arg) 2390 { 2391 void *result; 2392 2393 /* Do handling ... */ 2394 2395 return result; 2396 } 2397 2398 SUBSCRIBE_TO_EVENT(foo, foo_handler); 2399 2400 2401Reclaiming the BL31 initialization code 2402~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2403 2404A significant amount of the code used for the initialization of BL31 is never 2405needed again after boot time. In order to reduce the runtime memory 2406footprint, the memory used for this code can be reclaimed after initialization 2407has finished and be used for runtime data. 2408 2409The build option ``RECLAIM_INIT_CODE`` can be set to mark this boot time code 2410with a ``.text.init.*`` attribute which can be filtered and placed suitably 2411within the BL image for later reclamation by the platform. The platform can 2412specify the filter and the memory region for this init section in BL31 via the 2413plat.ld.S linker script. For example, on the FVP, this section is placed 2414overlapping the secondary CPU stacks so that after the cold boot is done, this 2415memory can be reclaimed for the stacks. The init memory section is initially 2416mapped with ``RO``, ``EXECUTE`` attributes. After BL31 initialization has 2417completed, the FVP changes the attributes of this section to ``RW``, 2418``EXECUTE_NEVER`` allowing it to be used for runtime data. The memory attributes 2419are changed within the ``bl31_plat_runtime_setup`` platform hook. The init 2420section section can be reclaimed for any data which is accessed after cold 2421boot initialization and it is upto the platform to make the decision. 2422 2423.. _firmware_design_pmf: 2424 2425Performance Measurement Framework 2426--------------------------------- 2427 2428The Performance Measurement Framework (PMF) facilitates collection of 2429timestamps by registered services and provides interfaces to retrieve them 2430from within TF-A. A platform can choose to expose appropriate SMCs to 2431retrieve these collected timestamps. 2432 2433By default, the global physical counter is used for the timestamp 2434value and is read via ``CNTPCT_EL0``. The framework allows to retrieve 2435timestamps captured by other CPUs. 2436 2437Timestamp identifier format 2438~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2439 2440A PMF timestamp is uniquely identified across the system via the 2441timestamp ID or ``tid``. The ``tid`` is composed as follows: 2442 2443:: 2444 2445 Bits 0-7: The local timestamp identifier. 2446 Bits 8-9: Reserved. 2447 Bits 10-15: The service identifier. 2448 Bits 16-31: Reserved. 2449 2450#. The service identifier. Each PMF service is identified by a 2451 service name and a service identifier. Both the service name and 2452 identifier are unique within the system as a whole. 2453 2454#. The local timestamp identifier. This identifier is unique within a given 2455 service. 2456 2457Registering a PMF service 2458~~~~~~~~~~~~~~~~~~~~~~~~~ 2459 2460To register a PMF service, the ``PMF_REGISTER_SERVICE()`` macro from ``pmf.h`` 2461is used. The arguments required are the service name, the service ID, 2462the total number of local timestamps to be captured and a set of flags. 2463 2464The ``flags`` field can be specified as a bitwise-OR of the following values: 2465 2466:: 2467 2468 PMF_STORE_ENABLE: The timestamp is stored in memory for later retrieval. 2469 PMF_DUMP_ENABLE: The timestamp is dumped on the serial console. 2470 2471The ``PMF_REGISTER_SERVICE()`` reserves memory to store captured 2472timestamps in a PMF specific linker section at build time. 2473Additionally, it defines necessary functions to capture and 2474retrieve a particular timestamp for the given service at runtime. 2475 2476The macro ``PMF_REGISTER_SERVICE()`` only enables capturing PMF timestamps 2477from within TF-A. In order to retrieve timestamps from outside of TF-A, the 2478``PMF_REGISTER_SERVICE_SMC()`` macro must be used instead. This macro 2479accepts the same set of arguments as the ``PMF_REGISTER_SERVICE()`` 2480macro but additionally supports retrieving timestamps using SMCs. 2481 2482Capturing a timestamp 2483~~~~~~~~~~~~~~~~~~~~~ 2484 2485PMF timestamps are stored in a per-service timestamp region. On a 2486system with multiple CPUs, each timestamp is captured and stored 2487in a per-CPU cache line aligned memory region. 2488 2489Having registered the service, the ``PMF_CAPTURE_TIMESTAMP()`` macro can be 2490used to capture a timestamp at the location where it is used. The macro 2491takes the service name, a local timestamp identifier and a flag as arguments. 2492 2493The ``flags`` field argument can be zero, or ``PMF_CACHE_MAINT`` which 2494instructs PMF to do cache maintenance following the capture. Cache 2495maintenance is required if any of the service's timestamps are captured 2496with data cache disabled. 2497 2498To capture a timestamp in assembly code, the caller should use 2499``pmf_calc_timestamp_addr`` macro (defined in ``pmf_asm_macros.S``) to 2500calculate the address of where the timestamp would be stored. The 2501caller should then read ``CNTPCT_EL0`` register to obtain the timestamp 2502and store it at the determined address for later retrieval. 2503 2504Retrieving a timestamp 2505~~~~~~~~~~~~~~~~~~~~~~ 2506 2507From within TF-A, timestamps for individual CPUs can be retrieved using either 2508``PMF_GET_TIMESTAMP_BY_MPIDR()`` or ``PMF_GET_TIMESTAMP_BY_INDEX()`` macros. 2509These macros accept the CPU's MPIDR value, or its ordinal position 2510respectively. 2511 2512From outside TF-A, timestamps for individual CPUs can be retrieved by calling 2513into ``pmf_smc_handler()``. 2514 2515:: 2516 2517 Interface : pmf_smc_handler() 2518 Argument : unsigned int smc_fid, u_register_t x1, 2519 u_register_t x2, u_register_t x3, 2520 u_register_t x4, void *cookie, 2521 void *handle, u_register_t flags 2522 Return : uintptr_t 2523 2524 smc_fid: Holds the SMC identifier which is either `PMF_SMC_GET_TIMESTAMP_32` 2525 when the caller of the SMC is running in AArch32 mode 2526 or `PMF_SMC_GET_TIMESTAMP_64` when the caller is running in AArch64 mode. 2527 x1: Timestamp identifier. 2528 x2: The `mpidr` of the CPU for which the timestamp has to be retrieved. 2529 This can be the `mpidr` of a different core to the one initiating 2530 the SMC. In that case, service specific cache maintenance may be 2531 required to ensure the updated copy of the timestamp is returned. 2532 x3: A flags value that is either 0 or `PMF_CACHE_MAINT`. If 2533 `PMF_CACHE_MAINT` is passed, then the PMF code will perform a 2534 cache invalidate before reading the timestamp. This ensures 2535 an updated copy is returned. 2536 2537The remaining arguments, ``x4``, ``cookie``, ``handle`` and ``flags`` are unused 2538in this implementation. 2539 2540PMF code structure 2541~~~~~~~~~~~~~~~~~~ 2542 2543#. ``pmf_main.c`` consists of core functions that implement service registration, 2544 initialization, storing, dumping and retrieving timestamps. 2545 2546#. ``pmf_smc.c`` contains the SMC handling for registered PMF services. 2547 2548#. ``pmf.h`` contains the public interface to Performance Measurement Framework. 2549 2550#. ``pmf_asm_macros.S`` consists of macros to facilitate capturing timestamps in 2551 assembly code. 2552 2553#. ``pmf_helpers.h`` is an internal header used by ``pmf.h``. 2554 2555Armv8-A Architecture Extensions 2556------------------------------- 2557 2558TF-A makes use of Armv8-A Architecture Extensions where applicable. This 2559section lists the usage of Architecture Extensions, and build flags 2560controlling them. 2561 2562In general, and unless individually mentioned, the build options 2563``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` select the Architecture Extension to 2564target when building TF-A. Subsequent Arm Architecture Extensions are backward 2565compatible with previous versions. 2566 2567The build system only requires that ``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` have a 2568valid numeric value. These build options only control whether or not 2569Architecture Extension-specific code is included in the build. Otherwise, TF-A 2570targets the base Armv8.0-A architecture; i.e. as if ``ARM_ARCH_MAJOR`` == 8 2571and ``ARM_ARCH_MINOR`` == 0, which are also their respective default values. 2572 2573.. seealso:: :ref:`Build Options` 2574 2575For details on the Architecture Extension and available features, please refer 2576to the respective Architecture Extension Supplement. 2577 2578Armv8.1-A 2579~~~~~~~~~ 2580 2581This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when 2582``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` >= 1. 2583 2584- By default, a load-/store-exclusive instruction pair is used to implement 2585 spinlocks. The ``USE_SPINLOCK_CAS`` build option when set to 1 selects the 2586 spinlock implementation using the ARMv8.1-LSE Compare and Swap instruction. 2587 Notice this instruction is only available in AArch64 execution state, so 2588 the option is only available to AArch64 builds. 2589 2590Armv8.2-A 2591~~~~~~~~~ 2592 2593- The presence of ARMv8.2-TTCNP is detected at runtime. When it is present, the 2594 Common not Private (TTBRn_ELx.CnP) bit is enabled to indicate that multiple 2595 Processing Elements in the same Inner Shareable domain use the same 2596 translation table entries for a given stage of translation for a particular 2597 translation regime. 2598 2599Armv8.3-A 2600~~~~~~~~~ 2601 2602- Pointer authentication features of Armv8.3-A are unconditionally enabled in 2603 the Non-secure world so that lower ELs are allowed to use them without 2604 causing a trap to EL3. 2605 2606 In order to enable the Secure world to use it, ``CTX_INCLUDE_PAUTH_REGS`` 2607 must be set to 1. This will add all pointer authentication system registers 2608 to the context that is saved when doing a world switch. 2609 2610 The TF-A itself has support for pointer authentication at runtime 2611 that can be enabled by setting ``BRANCH_PROTECTION`` option to non-zero and 2612 ``CTX_INCLUDE_PAUTH_REGS`` to 1. This enables pointer authentication in BL1, 2613 BL2, BL31, and the TSP if it is used. 2614 2615 These options are experimental features. 2616 2617 Note that Pointer Authentication is enabled for Non-secure world irrespective 2618 of the value of these build flags if the CPU supports it. 2619 2620 If ``ARM_ARCH_MAJOR == 8`` and ``ARM_ARCH_MINOR >= 3`` the code footprint of 2621 enabling PAuth is lower because the compiler will use the optimized 2622 PAuth instructions rather than the backwards-compatible ones. 2623 2624Armv8.5-A 2625~~~~~~~~~ 2626 2627- Branch Target Identification feature is selected by ``BRANCH_PROTECTION`` 2628 option set to 1. This option defaults to 0 and this is an experimental 2629 feature. 2630 2631- Memory Tagging Extension feature is unconditionally enabled for both worlds 2632 (at EL0 and S-EL0) if it is only supported at EL0. If instead it is 2633 implemented at all ELs, it is unconditionally enabled for only the normal 2634 world. To enable it for the secure world as well, the build option 2635 ``CTX_INCLUDE_MTE_REGS`` is required. If the hardware does not implement 2636 MTE support at all, it is always disabled, no matter what build options 2637 are used. 2638 2639Armv7-A 2640~~~~~~~ 2641 2642This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 7. 2643 2644There are several Armv7-A extensions available. Obviously the TrustZone 2645extension is mandatory to support the TF-A bootloader and runtime services. 2646 2647Platform implementing an Armv7-A system can to define from its target 2648Cortex-A architecture through ``ARM_CORTEX_A<X> = yes`` in their 2649``platform.mk`` script. For example ``ARM_CORTEX_A15=yes`` for a 2650Cortex-A15 target. 2651 2652Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support. 2653Note that using neon at runtime has constraints on non secure world context. 2654TF-A does not yet provide VFP context management. 2655 2656Directive ``ARM_CORTEX_A<x>`` and ``ARM_WITH_NEON`` are used to set 2657the toolchain target architecture directive. 2658 2659Platform may choose to not define straight the toolchain target architecture 2660directive by defining ``MARCH32_DIRECTIVE``. 2661I.e: 2662 2663.. code:: make 2664 2665 MARCH32_DIRECTIVE := -mach=armv7-a 2666 2667Code Structure 2668-------------- 2669 2670TF-A code is logically divided between the three boot loader stages mentioned 2671in the previous sections. The code is also divided into the following 2672categories (present as directories in the source code): 2673 2674- **Platform specific.** Choice of architecture specific code depends upon 2675 the platform. 2676- **Common code.** This is platform and architecture agnostic code. 2677- **Library code.** This code comprises of functionality commonly used by all 2678 other code. The PSCI implementation and other EL3 runtime frameworks reside 2679 as Library components. 2680- **Stage specific.** Code specific to a boot stage. 2681- **Drivers.** 2682- **Services.** EL3 runtime services (eg: SPD). Specific SPD services 2683 reside in the ``services/spd`` directory (e.g. ``services/spd/tspd``). 2684 2685Each boot loader stage uses code from one or more of the above mentioned 2686categories. Based upon the above, the code layout looks like this: 2687 2688:: 2689 2690 Directory Used by BL1? Used by BL2? Used by BL31? 2691 bl1 Yes No No 2692 bl2 No Yes No 2693 bl31 No No Yes 2694 plat Yes Yes Yes 2695 drivers Yes No Yes 2696 common Yes Yes Yes 2697 lib Yes Yes Yes 2698 services No No Yes 2699 2700The build system provides a non configurable build option IMAGE_BLx for each 2701boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE_BL1 will be 2702defined by the build system. This enables TF-A to compile certain code only 2703for specific boot loader stages 2704 2705All assembler files have the ``.S`` extension. The linker source files for each 2706boot stage have the extension ``.ld.S``. These are processed by GCC to create the 2707linker scripts which have the extension ``.ld``. 2708 2709FDTs provide a description of the hardware platform and are used by the Linux 2710kernel at boot time. These can be found in the ``fdts`` directory. 2711 2712.. rubric:: References 2713 2714- `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D)`_ 2715 2716- `Power State Coordination Interface PDD`_ 2717 2718- `SMC Calling Convention`_ 2719 2720- :ref:`Interrupt Management Framework` 2721 2722-------------- 2723 2724*Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.* 2725 2726.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2727.. _SMCCC: https://developer.arm.com/docs/den0028/latest 2728.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2729.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf 2730.. _Arm ARM: https://developer.arm.com/docs/ddi0487/latest 2731.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest 2732.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a 2733 2734.. |Image 1| image:: ../resources/diagrams/rt-svc-descs-layout.png 2735
