1Arm CPU Specific Build Macros 2============================= 3 4 5 6 7.. contents:: 8 9This document describes the various build options present in the CPU specific 10operations framework to enable errata workarounds and to enable optimizations 11for a specific CPU on a platform. 12 13Security Vulnerability Workarounds 14---------------------------------- 15 16TF-A exports a series of build flags which control which security 17vulnerability workarounds should be applied at runtime. 18 19- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for 20 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none 21 of the PEs in the system need the workaround. Setting this flag to 0 provides 22 no performance benefit for non-affected platforms, it just helps to comply 23 with the recommendation in the spec regarding workaround discovery. 24 Defaults to 1. 25 26- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for 27 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep 28 the default value of 1 even on platforms that are unaffected by 29 CVE-2018-3639, in order to comply with the recommendation in the spec 30 regarding workaround discovery. 31 32- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for 33 `CVE-2018-3639`_. This build option should be set to 1 if the target 34 platform contains at least 1 CPU that requires dynamic mitigation. 35 Defaults to 0. 36 37CPU Errata Workarounds 38---------------------- 39 40TF-A exports a series of build flags which control the errata workarounds that 41are applied to each CPU by the reset handler. The errata details can be found 42in the CPU specific errata documents published by Arm: 43 44- `Cortex-A53 MPCore Software Developers Errata Notice`_ 45- `Cortex-A57 MPCore Software Developers Errata Notice`_ 46- `Cortex-A72 MPCore Software Developers Errata Notice`_ 47 48The errata workarounds are implemented for a particular revision or a set of 49processor revisions. This is checked by the reset handler at runtime. Each 50errata workaround is identified by its ``ID`` as specified in the processor's 51errata notice document. The format of the define used to enable/disable the 52errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` 53is for example ``A57`` for the ``Cortex_A57`` CPU. 54 55Refer to the section *CPU errata status reporting* in 56`Firmware Design guide`_ for information on how to write errata workaround 57functions. 58 59All workarounds are disabled by default. The platform is responsible for 60enabling these workarounds according to its requirement by defining the 61errata workaround build flags in the platform specific makefile. In case 62these workarounds are enabled for the wrong CPU revision then the errata 63workaround is not applied. In the DEBUG build, this is indicated by 64printing a warning to the crash console. 65 66In the current implementation, a platform which has more than 1 variant 67with different revisions of a processor has no runtime mechanism available 68for it to specify which errata workarounds should be enabled or not. 69 70The value of the build flags is 0 by default, that is, disabled. A value of 1 71will enable it. 72 73For Cortex-A9, the following errata build flags are defined : 74 75- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9 76 CPU. This needs to be enabled for all revisions of the CPU. 77 78For Cortex-A15, the following errata build flags are defined : 79 80- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 81 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 82 83- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 84 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 85 86For Cortex-A17, the following errata build flags are defined : 87 88- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17 89 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 90 91- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17 92 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 93 94For Cortex-A35, the following errata build flags are defined : 95 96- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35 97 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35. 98 99For Cortex-A53, the following errata build flags are defined : 100 101- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all 102 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53. 103 104- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all 105 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 106 107- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 108 CPU. This needs to be enabled only for revision <= r0p2 of the CPU. 109 110- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all 111 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 112 113- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and 114 link time to Cortex-A53 CPU. This needs to be enabled for some variants of 115 revision <= r0p4. This workaround can lead the linker to create ``*.stub`` 116 sections. 117 118- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 119 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From 120 r0p4 and onwards, this errata is enabled by default in hardware. 121 122- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time 123 to Cortex-A53 CPU. This needs to be enabled for some variants of revision 124 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections 125 which are 4kB aligned. 126 127- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 128 CPUs. Though the erratum is present in every revision of the CPU, 129 this workaround is only applied to CPUs from r0p3 onwards, which feature 130 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. 131 Earlier revisions of the CPU have other errata which require the same 132 workaround in software, so they should be covered anyway. 133 134For Cortex-A55, the following errata build flags are defined : 135 136- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55 137 CPU. This needs to be enabled only for revision r0p0 of the CPU. 138 139- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55 140 CPU. This needs to be enabled only for revision r0p0 of the CPU. 141 142- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55 143 CPU. This needs to be enabled only for revision r0p0 of the CPU. 144 145- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55 146 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 147 148- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55 149 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 150 151For Cortex-A57, the following errata build flags are defined : 152 153- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 154 CPU. This needs to be enabled only for revision r0p0 of the CPU. 155 156- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 157 CPU. This needs to be enabled only for revision r0p0 of the CPU. 158 159- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 160 CPU. This needs to be enabled only for revision r0p0 of the CPU. 161 162- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57 163 CPU. This needs to be enabled only for revision r0p0 of the CPU. 164 165- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57 166 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 167 168- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 169 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 170 171- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 172 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 173 174- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 175 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 176 177- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 178 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 179 180- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 181 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 182 183- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 184 CPU. This needs to be enabled only for revision <= r1p3 of the CPU. 185 186 187For Cortex-A72, the following errata build flags are defined : 188 189- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 190 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. 191 192For Cortex-A73, the following errata build flags are defined : 193 194- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73 195 CPU. This needs to be enabled only for revision r0p0 of the CPU. 196 197- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 198 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 199 200For Cortex-A75, the following errata build flags are defined : 201 202- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 203 CPU. This needs to be enabled only for revision r0p0 of the CPU. 204 205- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 206 CPU. This needs to be enabled only for revision r0p0 of the CPU. 207 208For Cortex-A76, the following errata build flags are defined : 209 210- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 211 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 212 213- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 214 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 215 216- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 217 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 218 219- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76 220 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 221 222- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76 223 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 224 225- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76 226 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 227 228- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 229 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 230 231DSU Errata Workarounds 232---------------------- 233 234Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ 235Shared Unit) errata. The DSU errata details can be found in the respective Arm 236documentation: 237 238- `Arm DSU Software Developers Errata Notice`_. 239 240Each erratum is identified by an ``ID``, as defined in the DSU errata notice 241document. Thus, the build flags which enable/disable the errata workarounds 242have the format ``ERRATA_DSU_<ID>``. The implementation and application logic 243of DSU errata workarounds are similar to `CPU errata workarounds`_. 244 245For DSU errata, the following build flags are defined: 246 247- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the 248 affected DSU configurations. This errata applies only for those DSUs that 249 revision is r0p0 (on r0p1 it is fixed). However, please note that this 250 workaround results in increased DSU power consumption on idle. 251 252- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the 253 affected DSU configurations. This errata applies only for those DSUs that 254 contain the ACP interface **and** the DSU revision is older than r2p0 (on 255 r2p0 it is fixed). However, please note that this workaround results in 256 increased DSU power consumption on idle. 257 258CPU Specific optimizations 259-------------------------- 260 261This section describes some of the optimizations allowed by the CPU micro 262architecture that can be enabled by the platform as desired. 263 264- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the 265 Cortex-A57 cluster power down sequence by not flushing the Level 1 data 266 cache. The L1 data cache and the L2 unified cache are inclusive. A flush 267 of the L2 by set/way flushes any dirty lines from the L1 as well. This 268 is a known safe deviation from the Cortex-A57 TRM defined power down 269 sequence. Each Cortex-A57 based platform must make its own decision on 270 whether to use the optimization. 271 272- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal 273 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave 274 in a way most programmers expect, and will most probably result in a 275 significant speed degradation to any code that employs them. The Armv8-A 276 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore 277 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this 278 flag enforces this behaviour. This needs to be enabled only for revisions 279 <= r0p3 of the CPU and is enabled by default. 280 281- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as 282 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be 283 enabled only for revisions <= r1p2 of the CPU and is enabled by default, 284 as recommended in section "4.7 Non-Temporal Loads/Stores" of the 285 `Cortex-A57 Software Optimization Guide`_. 286 287-------------- 288 289*Copyright (c) 2014-2019, Arm Limited and Contributors. All rights reserved.* 290 291.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 292.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 293.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html 294.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html 295.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html 296.. _Firmware Design guide: firmware-design.rst 297.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf 298.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html 299