1Arm CPU Specific Build Macros 2============================= 3 4This document describes the various build options present in the CPU specific 5operations framework to enable errata workarounds and to enable optimizations 6for a specific CPU on a platform. 7 8Security Vulnerability Workarounds 9---------------------------------- 10 11TF-A exports a series of build flags which control which security 12vulnerability workarounds should be applied at runtime. 13 14- ``WORKAROUND_CVE_2017_5715``: Enables the security workaround for 15 `CVE-2017-5715`_. This flag can be set to 0 by the platform if none 16 of the PEs in the system need the workaround. Setting this flag to 0 provides 17 no performance benefit for non-affected platforms, it just helps to comply 18 with the recommendation in the spec regarding workaround discovery. 19 Defaults to 1. 20 21- ``WORKAROUND_CVE_2018_3639``: Enables the security workaround for 22 `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep 23 the default value of 1 even on platforms that are unaffected by 24 CVE-2018-3639, in order to comply with the recommendation in the spec 25 regarding workaround discovery. 26 27- ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for 28 `CVE-2018-3639`_. This build option should be set to 1 if the target 29 platform contains at least 1 CPU that requires dynamic mitigation. 30 Defaults to 0. 31 32- ``WORKAROUND_CVE_2022_23960``: Enables mitigation for `CVE-2022-23960`_. 33 This build option should be set to 1 if the target platform contains at 34 least 1 CPU that requires this mitigation. Defaults to 1. 35 36.. _arm_cpu_macros_errata_workarounds: 37 38CPU Errata Workarounds 39---------------------- 40 41TF-A exports a series of build flags which control the errata workarounds that 42are applied to each CPU by the reset handler. The errata details can be found 43in the CPU specific errata documents published by Arm: 44 45- `Cortex-A53 MPCore Software Developers Errata Notice`_ 46- `Cortex-A57 MPCore Software Developers Errata Notice`_ 47- `Cortex-A72 MPCore Software Developers Errata Notice`_ 48 49The errata workarounds are implemented for a particular revision or a set of 50processor revisions. This is checked by the reset handler at runtime. Each 51errata workaround is identified by its ``ID`` as specified in the processor's 52errata notice document. The format of the define used to enable/disable the 53errata workaround is ``ERRATA_<Processor name>_<ID>``, where the ``Processor name`` 54is for example ``A57`` for the ``Cortex_A57`` CPU. 55 56Refer to :ref:`firmware_design_cpu_errata_reporting` for information on how to 57write errata workaround functions. 58 59All workarounds are disabled by default. The platform is responsible for 60enabling these workarounds according to its requirement by defining the 61errata workaround build flags in the platform specific makefile. In case 62these workarounds are enabled for the wrong CPU revision then the errata 63workaround is not applied. In the DEBUG build, this is indicated by 64printing a warning to the crash console. 65 66In the current implementation, a platform which has more than 1 variant 67with different revisions of a processor has no runtime mechanism available 68for it to specify which errata workarounds should be enabled or not. 69 70The value of the build flags is 0 by default, that is, disabled. A value of 1 71will enable it. 72 73For Cortex-A9, the following errata build flags are defined : 74 75- ``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9 76 CPU. This needs to be enabled for all revisions of the CPU. 77 78For Cortex-A15, the following errata build flags are defined : 79 80- ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 81 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 82 83- ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 84 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. 85 86For Cortex-A17, the following errata build flags are defined : 87 88- ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17 89 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 90 91- ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17 92 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 93 94For Cortex-A35, the following errata build flags are defined : 95 96- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35 97 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35. 98 99For Cortex-A53, the following errata build flags are defined : 100 101- ``ERRATA_A53_819472``: This applies errata 819472 workaround to all 102 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53. 103 104- ``ERRATA_A53_824069``: This applies errata 824069 workaround to all 105 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 106 107- ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 108 CPU. This needs to be enabled only for revision <= r0p2 of the CPU. 109 110- ``ERRATA_A53_827319``: This applies errata 827319 workaround to all 111 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. 112 113- ``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and 114 link time to Cortex-A53 CPU. This needs to be enabled for some variants of 115 revision <= r0p4. This workaround can lead the linker to create ``*.stub`` 116 sections. 117 118- ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 119 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From 120 r0p4 and onwards, this errata is enabled by default in hardware. 121 122- ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time 123 to Cortex-A53 CPU. This needs to be enabled for some variants of revision 124 <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections 125 which are 4kB aligned. 126 127- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 128 CPUs. Though the erratum is present in every revision of the CPU, 129 this workaround is only applied to CPUs from r0p3 onwards, which feature 130 a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. 131 Earlier revisions of the CPU have other errata which require the same 132 workaround in software, so they should be covered anyway. 133 134- ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all 135 revisions of Cortex-A53 CPU. 136 137For Cortex-A55, the following errata build flags are defined : 138 139- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55 140 CPU. This needs to be enabled only for revision r0p0 of the CPU. 141 142- ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55 143 CPU. This needs to be enabled only for revision r0p0 of the CPU. 144 145- ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55 146 CPU. This needs to be enabled only for revision r0p0 of the CPU. 147 148- ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55 149 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 150 151- ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55 152 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 153 154- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55 155 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 156 157- ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all 158 revisions of Cortex-A55 CPU. 159 160For Cortex-A57, the following errata build flags are defined : 161 162- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 163 CPU. This needs to be enabled only for revision r0p0 of the CPU. 164 165- ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 166 CPU. This needs to be enabled only for revision r0p0 of the CPU. 167 168- ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 169 CPU. This needs to be enabled only for revision r0p0 of the CPU. 170 171- ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57 172 CPU. This needs to be enabled only for revision r0p0 of the CPU. 173 174- ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57 175 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 176 177- ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 178 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 179 180- ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 181 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 182 183- ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 184 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 185 186- ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 187 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 188 189- ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 190 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. 191 192- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 193 CPU. This needs to be enabled only for revision <= r1p3 of the CPU. 194 195- ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all 196 revisions of Cortex-A57 CPU. 197 198For Cortex-A72, the following errata build flags are defined : 199 200- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 201 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. 202 203- ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all 204 revisions of Cortex-A72 CPU. 205 206For Cortex-A73, the following errata build flags are defined : 207 208- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73 209 CPU. This needs to be enabled only for revision r0p0 of the CPU. 210 211- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 212 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. 213 214For Cortex-A75, the following errata build flags are defined : 215 216- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 217 CPU. This needs to be enabled only for revision r0p0 of the CPU. 218 219- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 220 CPU. This needs to be enabled only for revision r0p0 of the CPU. 221 222For Cortex-A76, the following errata build flags are defined : 223 224- ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 225 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 226 227- ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 228 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 229 230- ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 231 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 232 233- ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76 234 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 235 236- ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76 237 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 238 239- ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76 240 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 241 242- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 243 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 244 245- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76 246 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 247 248- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all 249 revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to 250 limitation of errata framework this errata is applied to all revisions 251 of Cortex-A76 CPU. 252 253- ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76 254 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 255 256- ``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76 257 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU. 258 259- ``ERRATA_A76_2743102``: This applies errata 2743102 workaround to Cortex-A76 260 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 261 still open. 262 263For Cortex-A77, the following errata build flags are defined : 264 265- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77 266 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 267 268- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77 269 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 270 271- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77 272 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. 273 274- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77 275 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 276 277- ``ERRATA_A77_2356587``: This applies errata 2356587 workaround to Cortex-A77 278 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 279 280 - ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77 281 CPU. This needs to be enabled for revisions <= r1p1 of the CPU. 282 283 - ``ERRATA_A77_2743100``: This applies errata 2743100 workaround to Cortex-A77 284 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 285 286For Cortex-A78, the following errata build flags are defined : 287 288- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 289 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU. 290 291- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78 292 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 293 294- ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78 295 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same 296 issue but there is no workaround for that revision. 297 298- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78 299 CPU. This needs to be enabled for revisions r0p0 and r1p0. 300 301- ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78 302 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0. 303 304- ``ERRATA_A78_2132060``: This applies errata 2132060 workaround to Cortex-A78 305 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It 306 is still open. 307 308- ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78 309 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue 310 is present in r0p0 but there is no workaround. It is still open. 311 312- ``ERRATA_A78_2376745``: This applies errata 2376745 workaround to Cortex-A78 313 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 314 it is still open. 315 316- ``ERRATA_A78_2395406``: This applies errata 2395406 workaround to Cortex-A78 317 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and 318 it is still open. 319 320For Cortex-A78 AE, the following errata build flags are defined : 321 322- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to 323 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. 324 This erratum is still open. 325 326- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to 327 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 328 erratum is still open. 329 330- ``ERRATA_A78_AE_2376748`` : This applies errata 2376748 workaround to 331 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 332 erratum is still open. 333 334- ``ERRATA_A78_AE_2395408`` : This applies errata 2395408 workaround to 335 Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This 336 erratum is still open. 337 338For Cortex-A78C, the following errata build flags are defined : 339 340- ``ERRATA_A78C_2132064`` : This applies errata 2132064 workaround to 341 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and 342 it is still open. 343 344- ``ERRATA_A78C_2242638`` : This applies errata 2242638 workaround to 345 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and 346 it is still open. 347 348- ``ERRATA_A78C_2376749`` : This applies errata 2376749 workaround to 349 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 350 erratum is still open. 351 352- ``ERRATA_A78C_2395411`` : This applies errata 2395411 workaround to 353 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This 354 erratum is still open. 355 356For Cortex-X1 CPU, the following errata build flags are defined: 357 358- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1 359 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 360 361- ``ERRATA_X1_1688305`` : This applies errata 1688305 workaround to Cortex-X1 362 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 363 364- ``ERRATA_X1_1827429`` : This applies errata 1827429 workaround to Cortex-X1 365 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. 366 367For Neoverse N1, the following errata build flags are defined : 368 369- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 370 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU. 371 372- ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1 373 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 374 375- ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1 376 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 377 378- ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1 379 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 380 381- ``ERRATA_N1_1220197``: This applies errata 1220197 workaround to Neoverse-N1 382 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. 383 384- ``ERRATA_N1_1257314``: This applies errata 1257314 workaround to Neoverse-N1 385 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 386 387- ``ERRATA_N1_1262606``: This applies errata 1262606 workaround to Neoverse-N1 388 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 389 390- ``ERRATA_N1_1262888``: This applies errata 1262888 workaround to Neoverse-N1 391 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 392 393- ``ERRATA_N1_1275112``: This applies errata 1275112 workaround to Neoverse-N1 394 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 395 396- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1 397 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. 398 399- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1 400 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU. 401 402- ``ERRATA_N1_1868343``: This applies errata 1868343 workaround to Neoverse-N1 403 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. 404 405- ``ERRATA_N1_1946160``: This applies errata 1946160 workaround to Neoverse-N1 406 CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for 407 revisions r0p0, r1p0, and r2p0 there is no workaround. 408 409- ``ERRATA_N1_2743102``: This applies errata 2743102 workaround to Neoverse-N1 410 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is 411 still open. 412 413For Neoverse V1, the following errata build flags are defined : 414 415- ``ERRATA_V1_1618635``: This applies errata 1618635 workaround to Neoverse-V1 416 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 417 r1p0. 418 419- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1 420 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 421 in r1p1. 422 423- ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1 424 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 425 in r1p1. 426 427- ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1 428 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed 429 in r1p1. 430 431- ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1 432 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. 433 434- ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1 435 CPU. This needs to be enabled only for revision r1p0 and r1p1 of the 436 CPU. 437 438- ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1 439 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 440 issue is present in r0p0 as well but there is no workaround for that 441 revision. It is still open. 442 443- ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1 444 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the 445 CPU. It is still open. 446 447- ``ERRATA_V1_2108267``: This applies errata 2108267 workaround to Neoverse-V1 448 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 449 It is still open. 450 451- ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1 452 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the 453 issue is present in r0p0 as well but there is no workaround for that 454 revision. It is still open. 455 456- ``ERRATA_V1_2294912``: This applies errata 2294912 workaround to Neoverse-V1 457 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. 458 459- ``ERRATA_V1_2372203``: This applies errata 2372203 workaround to Neoverse-V1 460 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU. 461 It is still open. 462 463For Cortex-A710, the following errata build flags are defined : 464 465- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to 466 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 467 r2p0 of the CPU. It is still open. 468 469- ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to 470 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 471 r2p0 of the CPU. It is still open. 472 473- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to 474 Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU 475 and is still open. 476 477- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to 478 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 479 of the CPU and is still open. 480 481- ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to 482 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and 483 is still open. 484 485- ``ERRATA_A710_2058056``: This applies errata 2058056 workaround to 486 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 487 of the CPU and is still open. 488 489- ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to 490 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 491 of the CPU and is fixed in r2p1. 492 493- ``ERRATA_A710_2136059``: This applies errata 2136059 workaround to 494 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 495 of the CPU and is fixed in r2p1. 496 497- ``ERRATA_A710_2147715``: This applies errata 2147715 workaround to 498 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU 499 and is fixed in r2p1. 500 501- ``ERRATA_A710_2216384``: This applies errata 2216384 workaround to 502 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 503 of the CPU and is fixed in r2p1. 504 505- ``ERRATA_A710_2282622``: This applies errata 2282622 workaround to 506 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 507 of the CPU and is fixed in r2p1. 508 509- ``ERRATA_A710_2291219``: This applies errata 2291219 workaround to 510 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 511 of the CPU and is fixed in r2p1. 512 513- ``ERRATA_A710_2008768``: This applies errata 2008768 workaround to 514 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 515 of the CPU and is fixed in r2p1. 516 517- ``ERRATA_A710_2371105``: This applies errata 2371105 workaround to 518 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 519 of the CPU and is fixed in r2p1. 520 521- ``ERRATA_A710_2768515``: This applies errata 2768515 workaround to 522 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and 523 r2p1 of the CPU and is still open. 524 525For Neoverse N2, the following errata build flags are defined : 526 527- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 528 CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open. 529 530- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 531 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. 532 533- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2 534 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. 535 536- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2 537 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. 538 539- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2 540 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. 541 542- ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2 543 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. 544 545- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2 546 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. 547 548- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2 549 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. 550 551- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2 552 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. 553 554- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2 555 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. 556 557- ``ERRATA_N2_2326639``: This applies errata 2326639 workaround to Neoverse-N2 558 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 559 r0p1. 560 561- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2 562 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 563 r0p1. 564 565- ``ERRATA_N2_2388450``: This applies errata 2388450 workaround to Neoverse-N2 566 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in 567 r0p1. 568 569For Cortex-X2, the following errata build flags are defined : 570 571- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2 572 CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU, 573 it is still open. 574 575- ``ERRATA_X2_2058056``: This applies errata 2058056 workaround to Cortex-X2 576 CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU, 577 it is still open. 578 579- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2 580 CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open. 581 582- ``ERRATA_X2_2017096``: This applies errata 2017096 workaround to 583 Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 584 r2p0 of the CPU, it is fixed in r2p1. 585 586- ``ERRATA_X2_2081180``: This applies errata 2081180 workaround to 587 Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 588 r2p0 of the CPU, it is fixed in r2p1. 589 590- ``ERRATA_X2_2216384``: This applies errata 2216384 workaround to 591 Cortex-X2 CPU. This needs to be enabled only for revisions r0p0, r1p0 and 592 r2p0 of the CPU, it is fixed in r2p1. 593 594- ``ERRATA_X2_2147715``: This applies errata 2147715 workaround to 595 Cortex-X2 CPU. This needs to be enabled only for revision r2p0 of the CPU, 596 it is fixed in r2p1. 597 598- ``ERRATA_X2_2371105``: This applies errata 2371105 workaround to 599 Cortex-X2 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 600 of the CPU and is fixed in r2p1. 601 602- ``ERRATA_X2_2768515``: This applies errata 2768515 workaround to 603 Cortex-X2 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 604 and r2p1 of the CPU and is still open. 605 606For Cortex-X3, the following errata build flags are defined : 607 608- ``ERRATA_X3_2313909``: This applies errata 2313909 workaround to 609 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0 610 of the CPU, it is fixed in r1p1. 611 612- ``ERRATA_X3_2615812``: This applies errata 2615812 workaround to Cortex-X3 613 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the 614 CPU, it is still open. 615 616For Cortex-A510, the following errata build flags are defined : 617 618- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to 619 Cortex-A510 CPU. This needs to be enabled only for revision r0p0, it is 620 fixed in r0p1. 621 622- ``ERRATA_A510_2288014``: This applies errata 2288014 workaround to 623 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1, 624 r0p2, r0p3 and r1p0, it is fixed in r1p1. 625 626- ``ERRATA_A510_2042739``: This applies errata 2042739 workaround to 627 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and 628 r0p2, it is fixed in r0p3. 629 630- ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to 631 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed 632 in r0p3. The issue is also present in r0p0 and r0p1 but there is no 633 workaround for those revisions. 634 635- ``ERRATA_A510_2250311``: This applies errata 2250311 workaround to 636 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 637 r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if 638 ENABLE_MPMM=1. 639 640- ``ERRATA_A510_2218950``: This applies errata 2218950 workaround to 641 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 642 r0p3 and r1p0, it is fixed in r1p1. 643 644- ``ERRATA_A510_2172148``: This applies errata 2172148 workaround to 645 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 646 r0p3 and r1p0, it is fixed in r1p1. 647 648- ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to 649 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, 650 r0p3, r1p0 and r1p1. It is fixed in r1p2. 651 652- ``ERRATA_A510_2371937``: This applies errata 2371937 workaround to 653 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 654 r0p3, r1p0, r1p1, and is fixed in r1p2. 655 656- ``ERRATA_A510_2666669``: This applies errata 2666669 workaround to 657 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, 658 r0p3, r1p0, r1p1. It is fixed in r1p2. 659 660DSU Errata Workarounds 661---------------------- 662 663Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ 664Shared Unit) errata. The DSU errata details can be found in the respective Arm 665documentation: 666 667- `Arm DSU Software Developers Errata Notice`_. 668 669Each erratum is identified by an ``ID``, as defined in the DSU errata notice 670document. Thus, the build flags which enable/disable the errata workarounds 671have the format ``ERRATA_DSU_<ID>``. The implementation and application logic 672of DSU errata workarounds are similar to `CPU errata workarounds`_. 673 674For DSU errata, the following build flags are defined: 675 676- ``ERRATA_DSU_798953``: This applies errata 798953 workaround for the 677 affected DSU configurations. This errata applies only for those DSUs that 678 revision is r0p0 (on r0p1 it is fixed). However, please note that this 679 workaround results in increased DSU power consumption on idle. 680 681- ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the 682 affected DSU configurations. This errata applies only for those DSUs that 683 contain the ACP interface **and** the DSU revision is older than r2p0 (on 684 r2p0 it is fixed). However, please note that this workaround results in 685 increased DSU power consumption on idle. 686 687- ``ERRATA_DSU_2313941``: This applies errata 2313941 workaround for the 688 affected DSU configurations. This errata applies for those DSUs with 689 revisions r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. However, 690 please note that this workaround results in increased DSU power consumption 691 on idle. 692 693CPU Specific optimizations 694-------------------------- 695 696This section describes some of the optimizations allowed by the CPU micro 697architecture that can be enabled by the platform as desired. 698 699- ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the 700 Cortex-A57 cluster power down sequence by not flushing the Level 1 data 701 cache. The L1 data cache and the L2 unified cache are inclusive. A flush 702 of the L2 by set/way flushes any dirty lines from the L1 as well. This 703 is a known safe deviation from the Cortex-A57 TRM defined power down 704 sequence. Each Cortex-A57 based platform must make its own decision on 705 whether to use the optimization. 706 707- ``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal 708 hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave 709 in a way most programmers expect, and will most probably result in a 710 significant speed degradation to any code that employs them. The Armv8-A 711 architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore 712 the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this 713 flag enforces this behaviour. This needs to be enabled only for revisions 714 <= r0p3 of the CPU and is enabled by default. 715 716- ``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as 717 ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be 718 enabled only for revisions <= r1p2 of the CPU and is enabled by default, 719 as recommended in section "4.7 Non-Temporal Loads/Stores" of the 720 `Cortex-A57 Software Optimization Guide`_. 721 722- ''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable 723 streaming enhancement feature for Cortex-A57 CPUs. Platforms can set 724 this bit only if their memory system meets the requirement that cache 725 line fill requests from the Cortex-A57 processor are atomic. Each 726 Cortex-A57 based platform must make its own decision on whether to use 727 the optimization. This flag is disabled by default. 728 729- ``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last 730 level cache(LLC) is present in the system, and that the DataSource field 731 on the master CHI interface indicates when data is returned from the LLC. 732 This is used to control how the LL_CACHE* PMU events count. 733 Default value is 0 (Disabled). 734 735GIC Errata Workarounds 736---------------------- 737- ``GIC600_ERRATA_WA_2384374``: This flag applies part 2 of errata 2384374 738 workaround for the affected GIC600 and GIC600-AE implementations. It applies 739 to implementations of GIC600 and GIC600-AE with revisions less than or equal 740 to r1p6 and r0p2 respectively. If the platform sets GICV3_SUPPORT_GIC600, 741 then this flag is enabled; otherwise, it is 0 (Disabled). 742 743-------------- 744 745*Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved.* 746 747.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715 748.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639 749.. _CVE-2022-23960: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2022-23960 750.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html 751.. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html 752.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html 753.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf 754.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html 755