1Secure Partition Manager 2************************ 3 4.. contents:: 5 6.. toctree:: 7 ffa-manifest-binding 8 9Acronyms 10======== 11 12+--------+--------------------------------------+ 13| CoT | Chain of Trust | 14+--------+--------------------------------------+ 15| DMA | Direct Memory Access | 16+--------+--------------------------------------+ 17| DTB | Device Tree Blob | 18+--------+--------------------------------------+ 19| DTS | Device Tree Source | 20+--------+--------------------------------------+ 21| EC | Execution Context | 22+--------+--------------------------------------+ 23| FIP | Firmware Image Package | 24+--------+--------------------------------------+ 25| FF-A | Firmware Framework for Arm A-profile | 26+--------+--------------------------------------+ 27| IPA | Intermediate Physical Address | 28+--------+--------------------------------------+ 29| JOP | Jump-Oriented Programming | 30+--------+--------------------------------------+ 31| NWd | Normal World | 32+--------+--------------------------------------+ 33| ODM | Original Design Manufacturer | 34+--------+--------------------------------------+ 35| OEM | Original Equipment Manufacturer | 36+--------+--------------------------------------+ 37| PA | Physical Address | 38+--------+--------------------------------------+ 39| PE | Processing Element | 40+--------+--------------------------------------+ 41| PM | Power Management | 42+--------+--------------------------------------+ 43| PVM | Primary VM | 44+--------+--------------------------------------+ 45| ROP | Return-Oriented Programming | 46+--------+--------------------------------------+ 47| SMMU | System Memory Management Unit | 48+--------+--------------------------------------+ 49| SP | Secure Partition | 50+--------+--------------------------------------+ 51| SPD | Secure Payload Dispatcher | 52+--------+--------------------------------------+ 53| SPM | Secure Partition Manager | 54+--------+--------------------------------------+ 55| SPMC | SPM Core | 56+--------+--------------------------------------+ 57| SPMD | SPM Dispatcher | 58+--------+--------------------------------------+ 59| SiP | Silicon Provider | 60+--------+--------------------------------------+ 61| SWd | Secure World | 62+--------+--------------------------------------+ 63| TLV | Tag-Length-Value | 64+--------+--------------------------------------+ 65| TOS | Trusted Operating System | 66+--------+--------------------------------------+ 67| VM | Virtual Machine | 68+--------+--------------------------------------+ 69 70Foreword 71======== 72 73Three implementations of a Secure Partition Manager co-exist in the TF-A 74codebase: 75 76#. S-EL2 SPMC based on the FF-A specification `[1]`_, enabling virtualization in 77 the secure world, managing multiple S-EL1 or S-EL0 partitions. 78#. EL3 SPMC based on the FF-A specification, managing a single S-EL1 partition 79 without virtualization in the secure world. 80#. EL3 SPM based on the MM specification, legacy implementation managing a 81 single S-EL0 partition `[2]`_. 82 83These implementations differ in their respective SW architecture and only one 84can be selected at build time. This document: 85 86- describes the implementation from bullet 1. when the SPMC resides at S-EL2. 87- is not an architecture specification and it might provide assumptions 88 on sections mandated as implementation-defined in the specification. 89- covers the implications to TF-A used as a bootloader, and Hafnium used as a 90 reference code base for an S-EL2/SPMC secure firmware on platforms 91 implementing the FEAT_SEL2 architecture extension. 92 93Terminology 94----------- 95 96- The term Hypervisor refers to the NS-EL2 component managing Virtual Machines 97 (or partitions) in the normal world. 98- The term SPMC refers to the S-EL2 component managing secure partitions in 99 the secure world when the FEAT_SEL2 architecture extension is implemented. 100- Alternatively, SPMC can refer to an S-EL1 component, itself being a secure 101 partition and implementing the FF-A ABI on platforms not implementing the 102 FEAT_SEL2 architecture extension. 103- The term VM refers to a normal world Virtual Machine managed by an Hypervisor. 104- The term SP refers to a secure world "Virtual Machine" managed by an SPMC. 105 106Support for legacy platforms 107---------------------------- 108 109The SPM is split into a dispatcher and a core component (respectively SPMD and 110SPMC) residing at different exception levels. To permit the FF-A specification 111adoption and a smooth migration, the SPMD supports an SPMC residing either at 112S-EL1 or S-EL2: 113 114- The SPMD is located at EL3 and mainly relays the FF-A protocol from NWd 115 (Hypervisor or OS kernel) to the SPMC. 116- The same SPMD component is used for both S-EL1 and S-EL2 SPMC configurations. 117- The SPMC exception level is a build time choice. 118 119TF-A supports both cases: 120 121- S-EL1 SPMC for platforms not supporting the FEAT_SEL2 architecture 122 extension. The SPMD relays the FF-A protocol from EL3 to S-EL1. 123- S-EL2 SPMC for platforms implementing the FEAT_SEL2 architecture 124 extension. The SPMD relays the FF-A protocol from EL3 to S-EL2. 125 126Sample reference stack 127====================== 128 129The following diagram illustrates a possible configuration when the 130FEAT_SEL2 architecture extension is implemented, showing the SPMD 131and SPMC, one or multiple secure partitions, with an optional 132Hypervisor: 133 134.. image:: ../resources/diagrams/ff-a-spm-sel2.png 135 136TF-A build options 137================== 138 139This section explains the TF-A build options involved in building with 140support for an FF-A based SPM where the SPMD is located at EL3 and the 141SPMC located at S-EL1, S-EL2 or EL3: 142 143- **SPD=spmd**: this option selects the SPMD component to relay the FF-A 144 protocol from NWd to SWd back and forth. It is not possible to 145 enable another Secure Payload Dispatcher when this option is chosen. 146- **SPMD_SPM_AT_SEL2**: this option adjusts the SPMC exception 147 level to being at S-EL2. It defaults to enabled (value 1) when 148 SPD=spmd is chosen. 149- **SPMC_AT_EL3**: this option adjusts the SPMC exception level to being 150 at EL3. 151- If neither ``SPMD_SPM_AT_SEL2`` or ``SPMC_AT_EL3`` are enabled the SPMC 152 exception level is set to S-EL1. 153 ``SPMD_SPM_AT_SEL2`` is enabled. The context save/restore routine 154 and exhaustive list of registers is visible at `[4]`_. 155- **SP_LAYOUT_FILE**: this option specifies a text description file 156 providing paths to SP binary images and manifests in DTS format 157 (see `Describing secure partitions`_). It 158 is required when ``SPMD_SPM_AT_SEL2`` is enabled hence when multiple 159 secure partitions are to be loaded by BL2 on behalf of the SPMC. 160 161+---------------+------------------+-------------+-------------------------+ 162| | SPMD_SPM_AT_SEL2 | SPMC_AT_EL3 | CTX_INCLUDE_EL2_REGS(*) | 163+---------------+------------------+-------------+-------------------------+ 164| SPMC at S-EL1 | 0 | 0 | 0 | 165+---------------+------------------+-------------+-------------------------+ 166| SPMC at S-EL2 | 1 (default when | 0 | 1 | 167| | SPD=spmd) | | | 168+---------------+------------------+-------------+-------------------------+ 169| SPMC at EL3 | 0 | 1 | 0 | 170+---------------+------------------+-------------+-------------------------+ 171 172Other combinations of such build options either break the build or are not 173supported. 174 175Notes: 176 177- Only Arm's FVP platform is supported to use with the TF-A reference software 178 stack. 179- When ``SPMD_SPM_AT_SEL2=1``, the reference software stack assumes enablement 180 of FEAT_PAuth, FEAT_BTI and FEAT_MTE architecture extensions. 181- ``(*) CTX_INCLUDE_EL2_REGS``, this flag is |TF-A| internal and informational 182 in this table. When set, it provides the generic support for saving/restoring 183 EL2 registers required when S-EL2 firmware is present. 184- BL32 option is re-purposed to specify the SPMC image. It can specify either 185 the Hafnium binary path (built for the secure world) or the path to a TEE 186 binary implementing FF-A interfaces. 187- BL33 option can specify the TFTF binary or a normal world loader 188 such as U-Boot or the UEFI framework payload. 189 190Sample TF-A build command line when the SPMC is located at S-EL1 191(e.g. when the FEAT_SEL2 architecture extension is not implemented): 192 193.. code:: shell 194 195 make \ 196 CROSS_COMPILE=aarch64-none-elf- \ 197 SPD=spmd \ 198 SPMD_SPM_AT_SEL2=0 \ 199 BL32=<path-to-tee-binary> \ 200 BL33=<path-to-bl33-binary> \ 201 PLAT=fvp \ 202 all fip 203 204Sample TF-A build command line when FEAT_SEL2 architecture extension is 205implemented and the SPMC is located at S-EL2: 206 207.. code:: shell 208 209 make \ 210 CROSS_COMPILE=aarch64-none-elf- \ 211 PLAT=fvp \ 212 SPD=spmd \ 213 ARM_ARCH_MINOR=5 \ 214 BRANCH_PROTECTION=1 \ 215 CTX_INCLUDE_PAUTH_REGS=1 \ 216 CTX_INCLUDE_MTE_REGS=1 \ 217 BL32=<path-to-hafnium-binary> \ 218 BL33=<path-to-bl33-binary> \ 219 SP_LAYOUT_FILE=sp_layout.json \ 220 all fip 221 222Sample TF-A build command line when FEAT_SEL2 architecture extension is 223implemented, the SPMC is located at S-EL2, and enabling secure boot: 224 225.. code:: shell 226 227 make \ 228 CROSS_COMPILE=aarch64-none-elf- \ 229 PLAT=fvp \ 230 SPD=spmd \ 231 ARM_ARCH_MINOR=5 \ 232 BRANCH_PROTECTION=1 \ 233 CTX_INCLUDE_PAUTH_REGS=1 \ 234 CTX_INCLUDE_MTE_REGS=1 \ 235 BL32=<path-to-hafnium-binary> \ 236 BL33=<path-to-bl33-binary> \ 237 SP_LAYOUT_FILE=sp_layout.json \ 238 MBEDTLS_DIR=<path-to-mbedtls-lib> \ 239 TRUSTED_BOARD_BOOT=1 \ 240 COT=dualroot \ 241 ARM_ROTPK_LOCATION=devel_rsa \ 242 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \ 243 GENERATE_COT=1 \ 244 all fip 245 246Sample TF-A build command line when the SPMC is located at EL3: 247 248.. code:: shell 249 250 make \ 251 CROSS_COMPILE=aarch64-none-elf- \ 252 SPD=spmd \ 253 SPMD_SPM_AT_SEL2=0 \ 254 SPMC_AT_EL3=1 \ 255 BL32=<path-to-tee-binary> \ 256 BL33=<path-to-bl33-binary> \ 257 PLAT=fvp \ 258 all fip 259 260FVP model invocation 261==================== 262 263The FVP command line needs the following options to exercise the S-EL2 SPMC: 264 265+---------------------------------------------------+------------------------------------+ 266| - cluster0.has_arm_v8-5=1 | Implements FEAT_SEL2, FEAT_PAuth, | 267| - cluster1.has_arm_v8-5=1 | and FEAT_BTI. | 268+---------------------------------------------------+------------------------------------+ 269| - pci.pci_smmuv3.mmu.SMMU_AIDR=2 | Parameters required for the | 270| - pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B | SMMUv3.2 modeling. | 271| - pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002 | | 272| - pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714 | | 273| - pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0472 | | 274| - pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002 | | 275| - pci.pci_smmuv3.mmu.SMMU_S_IDR2=0 | | 276| - pci.pci_smmuv3.mmu.SMMU_S_IDR3=0 | | 277+---------------------------------------------------+------------------------------------+ 278| - cluster0.has_branch_target_exception=1 | Implements FEAT_BTI. | 279| - cluster1.has_branch_target_exception=1 | | 280+---------------------------------------------------+------------------------------------+ 281| - cluster0.has_pointer_authentication=2 | Implements FEAT_PAuth | 282| - cluster1.has_pointer_authentication=2 | | 283+---------------------------------------------------+------------------------------------+ 284| - cluster0.memory_tagging_support_level=2 | Implements FEAT_MTE2 | 285| - cluster1.memory_tagging_support_level=2 | | 286| - bp.dram_metadata.is_enabled=1 | | 287+---------------------------------------------------+------------------------------------+ 288 289Sample FVP command line invocation: 290 291.. code:: shell 292 293 <path-to-fvp-model>/FVP_Base_RevC-2xAEMvA -C pctl.startup=0.0.0.0 \ 294 -C cluster0.NUM_CORES=4 -C cluster1.NUM_CORES=4 -C bp.secure_memory=1 \ 295 -C bp.secureflashloader.fname=trusted-firmware-a/build/fvp/debug/bl1.bin \ 296 -C bp.flashloader0.fname=trusted-firmware-a/build/fvp/debug/fip.bin \ 297 -C bp.pl011_uart0.out_file=fvp-uart0.log -C bp.pl011_uart1.out_file=fvp-uart1.log \ 298 -C bp.pl011_uart2.out_file=fvp-uart2.log \ 299 -C cluster0.has_arm_v8-5=1 -C cluster1.has_arm_v8-5=1 \ 300 -C cluster0.has_pointer_authentication=2 -C cluster1.has_pointer_authentication=2 \ 301 -C cluster0.has_branch_target_exception=1 -C cluster1.has_branch_target_exception=1 \ 302 -C cluster0.memory_tagging_support_level=2 -C cluster1.memory_tagging_support_level=2 \ 303 -C bp.dram_metadata.is_enabled=1 \ 304 -C pci.pci_smmuv3.mmu.SMMU_AIDR=2 -C pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B \ 305 -C pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002 -C pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714 \ 306 -C pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0472 -C pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002 \ 307 -C pci.pci_smmuv3.mmu.SMMU_S_IDR2=0 -C pci.pci_smmuv3.mmu.SMMU_S_IDR3=0 308 309Boot process 310============ 311 312Loading Hafnium and secure partitions in the secure world 313--------------------------------------------------------- 314 315TF-A BL2 is the bootlader for the SPMC and SPs in the secure world. 316 317SPs may be signed by different parties (SiP, OEM/ODM, TOS vendor, etc.). 318Thus they are supplied as distinct signed entities within the FIP flash 319image. The FIP image itself is not signed hence this provides the ability 320to upgrade SPs in the field. 321 322Booting through TF-A 323-------------------- 324 325SP manifests 326~~~~~~~~~~~~ 327 328An SP manifest describes SP attributes as defined in `[1]`_ 329(partition manifest at virtual FF-A instance) in DTS format. It is 330represented as a single file associated with the SP. A sample is 331provided by `[5]`_. A binding document is provided by `[6]`_. 332 333Secure Partition packages 334~~~~~~~~~~~~~~~~~~~~~~~~~ 335 336Secure partitions are bundled as independent package files consisting 337of: 338 339- a header 340- a DTB 341- an image payload 342 343The header starts with a magic value and offset values to SP DTB and 344image payload. Each SP package is loaded independently by BL2 loader 345and verified for authenticity and integrity. 346 347The SP package identified by its UUID (matching FF-A uuid property) is 348inserted as a single entry into the FIP at end of the TF-A build flow 349as shown: 350 351.. code:: shell 352 353 Trusted Boot Firmware BL2: offset=0x1F0, size=0x8AE1, cmdline="--tb-fw" 354 EL3 Runtime Firmware BL31: offset=0x8CD1, size=0x13000, cmdline="--soc-fw" 355 Secure Payload BL32 (Trusted OS): offset=0x1BCD1, size=0x15270, cmdline="--tos-fw" 356 Non-Trusted Firmware BL33: offset=0x30F41, size=0x92E0, cmdline="--nt-fw" 357 HW_CONFIG: offset=0x3A221, size=0x2348, cmdline="--hw-config" 358 TB_FW_CONFIG: offset=0x3C569, size=0x37A, cmdline="--tb-fw-config" 359 SOC_FW_CONFIG: offset=0x3C8E3, size=0x48, cmdline="--soc-fw-config" 360 TOS_FW_CONFIG: offset=0x3C92B, size=0x427, cmdline="--tos-fw-config" 361 NT_FW_CONFIG: offset=0x3CD52, size=0x48, cmdline="--nt-fw-config" 362 B4B5671E-4A90-4FE1-B81F-FB13DAE1DACB: offset=0x3CD9A, size=0xC168, cmdline="--blob" 363 D1582309-F023-47B9-827C-4464F5578FC8: offset=0x48F02, size=0xC168, cmdline="--blob" 364 365.. uml:: ../resources/diagrams/plantuml/fip-secure-partitions.puml 366 367Describing secure partitions 368~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 369 370A json-formatted description file is passed to the build flow specifying paths 371to the SP binary image and associated DTS partition manifest file. The latter 372is processed by the dtc compiler to generate a DTB fed into the SP package. 373Optionally, the partition's json description can contain offsets for both 374the image and partition manifest within the SP package. Both offsets need to be 3754KB aligned, because it is the translation granule supported by Hafnium SPMC. 376These fields can be leveraged to support SPs with S1 translation granules that 377differ from 4KB, and to configure the regions allocated within the SP package, 378as well as to comply with the requirements for the implementation of the boot 379information protocol (see `Passing boot data to the SP`_ for more details). In 380case the offsets are absent in their json node, they default to 0x1000 and 3810x4000 for the manifest offset and image offset respectively. 382This file also specifies the SP owner (as an optional field) identifying the 383signing domain in case of dual root CoT. 384The SP owner can either be the silicon or the platform provider. The 385corresponding "owner" field value can either take the value of "SiP" or "Plat". 386In absence of "owner" field, it defaults to "SiP" owner. 387The UUID of the partition can be specified as a field in the description file or 388if it does not exist there the UUID is extracted from the DTS partition 389manifest. 390 391.. code:: shell 392 393 { 394 "tee1" : { 395 "image": "tee1.bin", 396 "pm": "tee1.dts", 397 "owner": "SiP", 398 "uuid": "1b1820fe-48f7-4175-8999-d51da00b7c9f" 399 }, 400 401 "tee2" : { 402 "image": "tee2.bin", 403 "pm": "tee2.dts", 404 "owner": "Plat" 405 }, 406 407 "tee3" : { 408 "image": { 409 "file": "tee3.bin", 410 "offset":"0x2000" 411 }, 412 "pm": { 413 "file": "tee3.dts", 414 "offset":"0x6000" 415 }, 416 "owner": "Plat" 417 }, 418 } 419 420SPMC manifest 421~~~~~~~~~~~~~ 422 423This manifest contains the SPMC *attribute* node consumed by the SPMD at boot 424time. It implements `[1]`_ (SP manifest at physical FF-A instance) and serves 425two different cases: 426 427- The SPMC resides at S-EL1: the SPMC manifest is used by the SPMD to setup a 428 SP that co-resides with the SPMC and executes at S-EL1 or Secure Supervisor 429 mode. 430- The SPMC resides at S-EL2: the SPMC manifest is used by the SPMD to setup 431 the environment required by the SPMC to run at S-EL2. SPs run at S-EL1 or 432 S-EL0. 433 434.. code:: shell 435 436 attribute { 437 spmc_id = <0x8000>; 438 maj_ver = <0x1>; 439 min_ver = <0x1>; 440 exec_state = <0x0>; 441 load_address = <0x0 0x6000000>; 442 entrypoint = <0x0 0x6000000>; 443 binary_size = <0x60000>; 444 }; 445 446- *spmc_id* defines the endpoint ID value that SPMC can query through 447 ``FFA_ID_GET``. 448- *maj_ver/min_ver*. SPMD checks provided version versus its internal 449 version and aborts if not matching. 450- *exec_state* defines the SPMC execution state (AArch64 or AArch32). 451 Notice Hafnium used as a SPMC only supports AArch64. 452- *load_address* and *binary_size* are mostly used to verify secondary 453 entry points fit into the loaded binary image. 454- *entrypoint* defines the cold boot primary core entry point used by 455 SPMD (currently matches ``BL32_BASE``) to enter the SPMC. 456 457Other nodes in the manifest are consumed by Hafnium in the secure world. 458A sample can be found at `[7]`_: 459 460- The *hypervisor* node describes SPs. *is_ffa_partition* boolean attribute 461 indicates a FF-A compliant SP. The *load_address* field specifies the load 462 address at which BL2 loaded the SP package. 463- *cpus* node provide the platform topology and allows MPIDR to VMPIDR mapping. 464 Note the primary core is declared first, then secondary cores are declared 465 in reverse order. 466- The *memory* nodes provide platform information on the ranges of memory 467 available for use by SPs at runtime. These ranges relate to either 468 secure or non-secure memory, depending on the *device_type* field. 469 If the field specifies "memory" the range is secure, else if it specifies 470 "ns-memory" the memory is non-secure. The system integrator must exclude 471 the memory used by other components that are not SPs, such as the monitor, 472 or the SPMC itself, the OS Kernel/Hypervisor, or other NWd VMs. The SPMC 473 limits the SP's address space such that they do not access memory outside 474 of those ranges. 475 476SPMC boot 477~~~~~~~~~ 478 479The SPMC is loaded by BL2 as the BL32 image. 480 481The SPMC manifest is loaded by BL2 as the ``TOS_FW_CONFIG`` image `[9]`_. 482 483BL2 passes the SPMC manifest address to BL31 through a register. 484 485At boot time, the SPMD in BL31 runs from the primary core, initializes the core 486contexts and launches the SPMC (BL32) passing the following information through 487registers: 488 489- X0 holds the ``TOS_FW_CONFIG`` physical address (or SPMC manifest blob). 490- X1 holds the ``HW_CONFIG`` physical address. 491- X4 holds the currently running core linear id. 492 493Loading of SPs 494~~~~~~~~~~~~~~ 495 496At boot time, BL2 loads SPs sequentially in addition to the SPMC as depicted 497below: 498 499.. uml:: ../resources/diagrams/plantuml/bl2-loading-sp.puml 500 501Note this boot flow is an implementation sample on Arm's FVP platform. 502Platforms not using TF-A's *Firmware CONFiguration* framework would adjust to a 503different boot flow. The flow restricts to a maximum of 8 secure partitions. 504 505Secure boot 506~~~~~~~~~~~ 507 508The SP content certificate is inserted as a separate FIP item so that BL2 loads SPMC, 509SPMC manifest, secure partitions and verifies them for authenticity and integrity. 510Refer to TBBR specification `[3]`_. 511 512The multiple-signing domain feature (in current state dual signing domain `[8]`_) allows 513the use of two root keys namely S-ROTPK and NS-ROTPK: 514 515- SPMC (BL32) and SPMC manifest are signed by the SiP using the S-ROTPK. 516- BL33 may be signed by the OEM using NS-ROTPK. 517- An SP may be signed either by SiP (using S-ROTPK) or by OEM (using NS-ROTPK). 518- A maximum of 4 partitions can be signed with the S-ROTPK key and 4 partitions 519 signed with the NS-ROTPK key. 520 521Also refer to `Describing secure partitions`_ and `TF-A build options`_ sections. 522 523Hafnium in the secure world 524=========================== 525 526General considerations 527---------------------- 528 529Build platform for the secure world 530~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 531 532In the Hafnium reference implementation specific code parts are only relevant to 533the secure world. Such portions are isolated in architecture specific files 534and/or enclosed by a ``SECURE_WORLD`` macro. 535 536Secure partitions scheduling 537~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 538 539The FF-A specification `[1]`_ provides two ways to relinquinsh CPU time to 540secure partitions. For this a VM (Hypervisor or OS kernel), or SP invokes one of: 541 542- the FFA_MSG_SEND_DIRECT_REQ interface. 543- the FFA_RUN interface. 544 545Additionally a secure interrupt can pre-empt the normal world execution and give 546CPU cycles by transitioning to EL3 and S-EL2. 547 548Platform topology 549~~~~~~~~~~~~~~~~~ 550 551The *execution-ctx-count* SP manifest field can take the value of one or the 552total number of PEs. The FF-A specification `[1]`_ recommends the 553following SP types: 554 555- Pinned MP SPs: an execution context matches a physical PE. MP SPs must 556 implement the same number of ECs as the number of PEs in the platform. 557- Migratable UP SPs: a single execution context can run and be migrated on any 558 physical PE. Such SP declares a single EC in its SP manifest. An UP SP can 559 receive a direct message request originating from any physical core targeting 560 the single execution context. 561 562Parsing SP partition manifests 563------------------------------ 564 565Hafnium consumes SP manifests as defined in `[1]`_ and `SP manifests`_. 566Note the current implementation may not implement all optional fields. 567 568The SP manifest may contain memory and device regions nodes. In case of 569an S-EL2 SPMC: 570 571- Memory regions are mapped in the SP EL1&0 Stage-2 translation regime at 572 load time (or EL1&0 Stage-1 for an S-EL1 SPMC). A memory region node can 573 specify RX/TX buffer regions in which case it is not necessary for an SP 574 to explicitly invoke the ``FFA_RXTX_MAP`` interface. The memory referred 575 shall be contained within the memory ranges defined in SPMC manifest. The 576 NS bit in the attributes field should be consistent with the security 577 state of the range that it relates to. I.e. non-secure memory shall be 578 part of a non-secure memory range, and secure memory shall be contained 579 in a secure memory range of a given platform. 580- Device regions are mapped in the SP EL1&0 Stage-2 translation regime (or 581 EL1&0 Stage-1 for an S-EL1 SPMC) as peripherals and possibly allocate 582 additional resources (e.g. interrupts). 583 584For the S-EL2 SPMC, base addresses for memory and device region nodes are IPAs 585provided the SPMC identity maps IPAs to PAs within SP EL1&0 Stage-2 translation 586regime. 587 588Note: in the current implementation both VTTBR_EL2 and VSTTBR_EL2 point to the 589same set of page tables. It is still open whether two sets of page tables shall 590be provided per SP. The memory region node as defined in the specification 591provides a memory security attribute hinting to map either to the secure or 592non-secure EL1&0 Stage-2 table if it exists. 593 594Passing boot data to the SP 595--------------------------- 596 597In `[1]`_ , the section "Boot information protocol" defines a method for passing 598data to the SPs at boot time. It specifies the format for the boot information 599descriptor and boot information header structures, which describe the data to be 600exchanged between SPMC and SP. 601The specification also defines the types of data that can be passed. 602The aggregate of both the boot info structures and the data itself is designated 603the boot information blob, and is passed to a Partition as a contiguous memory 604region. 605 606Currently, the SPM implementation supports the FDT type which is used to pass the 607partition's DTB manifest. 608 609The region for the boot information blob is allocated through the SP package. 610 611.. image:: ../resources/diagrams/partition-package.png 612 613To adjust the space allocated for the boot information blob, the json description 614of the SP (see section `Describing secure partitions`_) shall be updated to contain 615the manifest offset. If no offset is provided the manifest offset defaults to 0x1000, 616which is the page size in the Hafnium SPMC. 617 618The configuration of the boot protocol is done in the SPs manifest. As defined by 619the specification, the manifest field 'gp-register-num' configures the GP register 620which shall be used to pass the address to the partitions boot information blob when 621booting the partition. 622In addition, the Hafnium SPMC implementation requires the boot information arguments 623to be listed in a designated DT node: 624 625.. code:: shell 626 627 boot-info { 628 compatible = "arm,ffa-manifest-boot-info"; 629 ffa_manifest; 630 }; 631 632The whole secure partition package image (see `Secure Partition packages`_) is 633mapped to the SP secure EL1&0 Stage-2 translation regime. As such, the SP can 634retrieve the address for the boot information blob in the designated GP register, 635process the boot information header and descriptors, access its own manifest 636DTB blob and extract its partition manifest properties. 637 638SP Boot order 639------------- 640 641SP manifests provide an optional boot order attribute meant to resolve 642dependencies such as an SP providing a service required to properly boot 643another SP. SPMC boots the SPs in accordance to the boot order attribute, 644lowest to the highest value. If the boot order attribute is absent from the FF-A 645manifest, the SP is treated as if it had the highest boot order value 646(i.e. lowest booting priority). 647 648It is possible for an SP to call into another SP through a direct request 649provided the latter SP has already been booted. 650 651Boot phases 652----------- 653 654Primary core boot-up 655~~~~~~~~~~~~~~~~~~~~ 656 657Upon boot-up, BL31 hands over to the SPMC (BL32) on the primary boot physical 658core. The SPMC performs its platform initializations and registers the SPMC 659secondary physical core entry point physical address by the use of the 660`FFA_SECONDARY_EP_REGISTER`_ interface (SMC invocation from the SPMC to the SPMD 661at secure physical FF-A instance). 662 663The SPMC then creates secure partitions based on SP packages and manifests. Each 664secure partition is launched in sequence (`SP Boot order`_) on their "primary" 665execution context. If the primary boot physical core linear id is N, an MP SP is 666started using EC[N] on PE[N] (see `Platform topology`_). If the partition is a 667UP SP, it is started using its unique EC0 on PE[N]. 668 669The SP primary EC (or the EC used when the partition is booted as described 670above): 671 672- Performs the overall SP boot time initialization, and in case of a MP SP, 673 prepares the SP environment for other execution contexts. 674- In the case of a MP SP, it invokes the FFA_SECONDARY_EP_REGISTER at secure 675 virtual FF-A instance (SMC invocation from SP to SPMC) to provide the IPA 676 entry point for other execution contexts. 677- Exits through ``FFA_MSG_WAIT`` to indicate successful initialization or 678 ``FFA_ERROR`` in case of failure. 679 680Secondary cores boot-up 681~~~~~~~~~~~~~~~~~~~~~~~ 682 683Once the system is started and NWd brought up, a secondary physical core is 684woken up by the ``PSCI_CPU_ON`` service invocation. The TF-A SPD hook mechanism 685calls into the SPMD on the newly woken up physical core. Then the SPMC is 686entered at the secondary physical core entry point. 687 688In the current implementation, the first SP is resumed on the coresponding EC 689(the virtual CPU which matches the physical core). The implication is that the 690first SP must be a MP SP. 691 692In a linux based system, once secure and normal worlds are booted but prior to 693a NWd FF-A driver has been loaded: 694 695- The first SP has initialized all its ECs in response to primary core boot up 696 (at system initialization) and secondary core boot up (as a result of linux 697 invoking PSCI_CPU_ON for all secondary cores). 698- Other SPs have their first execution context initialized as a result of secure 699 world initialization on the primary boot core. Other ECs for those SPs have to 700 be run first through ffa_run to complete their initialization (which results 701 in the EC completing with FFA_MSG_WAIT). 702 703Refer to `Power management`_ for further details. 704 705Notifications 706------------- 707 708The FF-A v1.1 specification `[1]`_ defines notifications as an asynchronous 709communication mechanism with non-blocking semantics. It allows for one FF-A 710endpoint to signal another for service provision, without hindering its current 711progress. 712 713Hafnium currently supports 64 notifications. The IDs of each notification define 714a position in a 64-bit bitmap. 715 716The signaling of notifications can interchangeably happen between NWd and SWd 717FF-A endpoints. 718 719The SPMC is in charge of managing notifications from SPs to SPs, from SPs to 720VMs, and from VMs to SPs. An hypervisor component would only manage 721notifications from VMs to VMs. Given the SPMC has no visibility of the endpoints 722deployed in NWd, the Hypervisor or OS kernel must invoke the interface 723FFA_NOTIFICATION_BITMAP_CREATE to allocate the notifications bitmap per FF-A 724endpoint in the NWd that supports it. 725 726A sender can signal notifications once the receiver has provided it with 727permissions. Permissions are provided by invoking the interface 728FFA_NOTIFICATION_BIND. 729 730Notifications are signaled by invoking FFA_NOTIFICATION_SET. Henceforth 731they are considered to be in a pending sate. The receiver can retrieve its 732pending notifications invoking FFA_NOTIFICATION_GET, which, from that moment, 733are considered to be handled. 734 735Per the FF-A v1.1 spec, each FF-A endpoint must be associated with a scheduler 736that is in charge of donating CPU cycles for notifications handling. The 737FF-A driver calls FFA_NOTIFICATION_INFO_GET to retrieve the information about 738which FF-A endpoints have pending notifications. The receiver scheduler is 739called and informed by the FF-A driver, and it should allocate CPU cycles to the 740receiver. 741 742There are two types of notifications supported: 743 744- Global, which are targeted to a FF-A endpoint and can be handled within any of 745 its execution contexts, as determined by the scheduler of the system. 746- Per-vCPU, which are targeted to a FF-A endpoint and to be handled within a 747 a specific execution context, as determined by the sender. 748 749The type of a notification is set when invoking FFA_NOTIFICATION_BIND to give 750permissions to the sender. 751 752Notification signaling resorts to two interrupts: 753 754- Schedule Receiver Interrupt: non-secure physical interrupt to be handled by 755 the FF-A driver within the receiver scheduler. At initialization the SPMC 756 donates a SGI ID chosen from the secure SGI IDs range and configures it as 757 non-secure. The SPMC triggers this SGI on the currently running core when 758 there are pending notifications, and the respective receivers need CPU cycles 759 to handle them. 760- Notifications Pending Interrupt: virtual interrupt to be handled by the 761 receiver of the notification. Set when there are pending notifications for the 762 given secure partition. The NPI is pended when the NWd relinquishes CPU cycles 763 to an SP. 764 765The notifications receipt support is enabled in the partition FF-A manifest. 766 767Mandatory interfaces 768-------------------- 769 770The following interfaces are exposed to SPs: 771 772- ``FFA_VERSION`` 773- ``FFA_FEATURES`` 774- ``FFA_RX_RELEASE`` 775- ``FFA_RXTX_MAP`` 776- ``FFA_RXTX_UNMAP`` 777- ``FFA_PARTITION_INFO_GET`` 778- ``FFA_ID_GET`` 779- ``FFA_MSG_WAIT`` 780- ``FFA_MSG_SEND_DIRECT_REQ`` 781- ``FFA_MSG_SEND_DIRECT_RESP`` 782- ``FFA_MEM_DONATE`` 783- ``FFA_MEM_LEND`` 784- ``FFA_MEM_SHARE`` 785- ``FFA_MEM_RETRIEVE_REQ`` 786- ``FFA_MEM_RETRIEVE_RESP`` 787- ``FFA_MEM_RELINQUISH`` 788- ``FFA_MEM_FRAG_RX`` 789- ``FFA_MEM_FRAG_TX`` 790- ``FFA_MEM_RECLAIM`` 791- ``FFA_RUN`` 792 793As part of the FF-A v1.1 support, the following interfaces were added: 794 795 - ``FFA_NOTIFICATION_BITMAP_CREATE`` 796 - ``FFA_NOTIFICATION_BITMAP_DESTROY`` 797 - ``FFA_NOTIFICATION_BIND`` 798 - ``FFA_NOTIFICATION_UNBIND`` 799 - ``FFA_NOTIFICATION_SET`` 800 - ``FFA_NOTIFICATION_GET`` 801 - ``FFA_NOTIFICATION_INFO_GET`` 802 - ``FFA_SPM_ID_GET`` 803 - ``FFA_SECONDARY_EP_REGISTER`` 804 - ``FFA_MEM_PERM_GET`` 805 - ``FFA_MEM_PERM_SET`` 806 - ``FFA_MSG_SEND2`` 807 - ``FFA_RX_ACQUIRE`` 808 809FFA_VERSION 810~~~~~~~~~~~ 811 812``FFA_VERSION`` requires a *requested_version* parameter from the caller. 813The returned value depends on the caller: 814 815- Hypervisor or OS kernel in NS-EL1/EL2: the SPMD returns the SPMC version 816 specified in the SPMC manifest. 817- SP: the SPMC returns its own implemented version. 818- SPMC at S-EL1/S-EL2: the SPMD returns its own implemented version. 819 820FFA_FEATURES 821~~~~~~~~~~~~ 822 823FF-A features supported by the SPMC may be discovered by secure partitions at 824boot (that is prior to NWd is booted) or run-time. 825 826The SPMC calling FFA_FEATURES at secure physical FF-A instance always get 827FFA_SUCCESS from the SPMD. 828 829The request made by an Hypervisor or OS kernel is forwarded to the SPMC and 830the response relayed back to the NWd. 831 832FFA_RXTX_MAP/FFA_RXTX_UNMAP 833~~~~~~~~~~~~~~~~~~~~~~~~~~~ 834 835When invoked from a secure partition FFA_RXTX_MAP maps the provided send and 836receive buffers described by their IPAs to the SP EL1&0 Stage-2 translation 837regime as secure buffers in the MMU descriptors. 838 839When invoked from the Hypervisor or OS kernel, the buffers are mapped into the 840SPMC EL2 Stage-1 translation regime and marked as NS buffers in the MMU 841descriptors. The provided addresses may be owned by a VM in the normal world, 842which is expected to receive messages from the secure world. The SPMC will in 843this case allocate internal state structures to facilitate RX buffer access 844synchronization (through FFA_RX_ACQUIRE interface), and to permit SPs to send 845messages. 846 847The FFA_RXTX_UNMAP unmaps the RX/TX pair from the translation regime of the 848caller, either it being the Hypervisor or OS kernel, as well as a secure 849partition. 850 851FFA_PARTITION_INFO_GET 852~~~~~~~~~~~~~~~~~~~~~~ 853 854Partition info get call can originate: 855 856- from SP to SPMC 857- from Hypervisor or OS kernel to SPMC. The request is relayed by the SPMD. 858 859FFA_ID_GET 860~~~~~~~~~~ 861 862The FF-A id space is split into a non-secure space and secure space: 863 864- FF-A ID with bit 15 clear relates to VMs. 865- FF-A ID with bit 15 set related to SPs. 866- FF-A IDs 0, 0xffff, 0x8000 are assigned respectively to the Hypervisor, SPMD 867 and SPMC. 868 869The SPMD returns: 870 871- The default zero value on invocation from the Hypervisor. 872- The ``spmc_id`` value specified in the SPMC manifest on invocation from 873 the SPMC (see `SPMC manifest`_) 874 875This convention helps the SPMC to determine the origin and destination worlds in 876an FF-A ABI invocation. In particular the SPMC shall filter unauthorized 877transactions in its world switch routine. It must not be permitted for a VM to 878use a secure FF-A ID as origin world by spoofing: 879 880- A VM-to-SP direct request/response shall set the origin world to be non-secure 881 (FF-A ID bit 15 clear) and destination world to be secure (FF-A ID bit 15 882 set). 883- Similarly, an SP-to-SP direct request/response shall set the FF-A ID bit 15 884 for both origin and destination IDs. 885 886An incoming direct message request arriving at SPMD from NWd is forwarded to 887SPMC without a specific check. The SPMC is resumed through eret and "knows" the 888message is coming from normal world in this specific code path. Thus the origin 889endpoint ID must be checked by SPMC for being a normal world ID. 890 891An SP sending a direct message request must have bit 15 set in its origin 892endpoint ID and this can be checked by the SPMC when the SP invokes the ABI. 893 894The SPMC shall reject the direct message if the claimed world in origin endpoint 895ID is not consistent: 896 897- It is either forwarded by SPMD and thus origin endpoint ID must be a "normal 898 world ID", 899- or initiated by an SP and thus origin endpoint ID must be a "secure world ID". 900 901 902FFA_MSG_SEND_DIRECT_REQ/FFA_MSG_SEND_DIRECT_RESP 903~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 904 905This is a mandatory interface for secure partitions consisting in direct request 906and responses with the following rules: 907 908- An SP can send a direct request to another SP. 909- An SP can receive a direct request from another SP. 910- An SP can send a direct response to another SP. 911- An SP cannot send a direct request to an Hypervisor or OS kernel. 912- An Hypervisor or OS kernel can send a direct request to an SP. 913- An SP can send a direct response to an Hypervisor or OS kernel. 914 915FFA_NOTIFICATION_BITMAP_CREATE/FFA_NOTIFICATION_BITMAP_DESTROY 916~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 917 918The secure partitions notifications bitmap are statically allocated by the SPMC. 919Hence, this interface is not to be issued by secure partitions. 920 921At initialization, the SPMC is not aware of VMs/partitions deployed in the 922normal world. Hence, the Hypervisor or OS kernel must use both ABIs for SPMC 923to be prepared to handle notifications for the provided VM ID. 924 925FFA_NOTIFICATION_BIND/FFA_NOTIFICATION_UNBIND 926~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 927 928Pair of interfaces to manage permissions to signal notifications. Prior to 929handling notifications, an FF-A endpoint must allow a given sender to signal a 930bitmap of notifications. 931 932If the receiver doesn't have notification support enabled in its FF-A manifest, 933it won't be able to bind notifications, hence forbidding it to receive any 934notifications. 935 936FFA_NOTIFICATION_SET/FFA_NOTIFICATION_GET 937~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 938 939FFA_NOTIFICATION_GET retrieves all pending global notifications and 940per-vCPU notifications targeted to the current vCPU. 941 942Hafnium maintains a global count of pending notifications which gets incremented 943and decremented when handling FFA_NOTIFICATION_SET and FFA_NOTIFICATION_GET 944respectively. A delayed SRI is triggered if the counter is non-zero when the 945SPMC returns to normal world. 946 947FFA_NOTIFICATION_INFO_GET 948~~~~~~~~~~~~~~~~~~~~~~~~~ 949 950Hafnium maintains a global count of pending notifications whose information 951has been retrieved by this interface. The count is incremented and decremented 952when handling FFA_NOTIFICATION_INFO_GET and FFA_NOTIFICATION_GET respectively. 953It also tracks notifications whose information has been retrieved individually, 954such that it avoids duplicating returned information for subsequent calls to 955FFA_NOTIFICATION_INFO_GET. For each notification, this state information is 956reset when receiver called FFA_NOTIFICATION_GET to retrieve them. 957 958FFA_SPM_ID_GET 959~~~~~~~~~~~~~~ 960 961Returns the FF-A ID allocated to an SPM component which can be one of SPMD 962or SPMC. 963 964At initialization, the SPMC queries the SPMD for the SPMC ID, using the 965FFA_ID_GET interface, and records it. The SPMC can also query the SPMD ID using 966the FFA_SPM_ID_GET interface at the secure physical FF-A instance. 967 968Secure partitions call this interface at the virtual FF-A instance, to which 969the SPMC returns the priorly retrieved SPMC ID. 970 971The Hypervisor or OS kernel can issue the FFA_SPM_ID_GET call handled by the 972SPMD, which returns the SPMC ID. 973 974FFA_SECONDARY_EP_REGISTER 975~~~~~~~~~~~~~~~~~~~~~~~~~ 976 977When the SPMC boots, all secure partitions are initialized on their primary 978Execution Context. 979 980The FFA_SECONDARY_EP_REGISTER interface is to be used by a secure partition 981from its first execution context, to provide the entry point address for 982secondary execution contexts. 983 984A secondary EC is first resumed either upon invocation of PSCI_CPU_ON from 985the NWd or by invocation of FFA_RUN. 986 987FFA_RX_ACQUIRE/FFA_RX_RELEASE 988~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 989 990The RX buffers can be used to pass information to an FF-A endpoint in the 991following scenarios: 992 993 - When it was targetted by a FFA_MSG_SEND2 invokation from another endpoint. 994 - Return the result of calling ``FFA_PARTITION_INFO_GET``. 995 - In a memory share operation, as part of the ``FFA_MEM_RETRIEVE_RESP``, 996 with the memory descriptor of the shared memory. 997 998If a normal world VM is expected to exchange messages with secure world, 999its RX/TX buffer addresses are forwarded to the SPMC via FFA_RXTX_MAP ABI, 1000and are from this moment owned by the SPMC. 1001The hypervisor must call the FFA_RX_ACQUIRE interface before attempting 1002to use the RX buffer, in any of the aforementioned scenarios. A successful 1003call to FFA_RX_ACQUIRE transfers ownership of RX buffer to hypervisor, such 1004that it can be safely used. 1005 1006The FFA_RX_RELEASE interface is used after the FF-A endpoint is done with 1007processing the data received in its RX buffer. If the RX buffer has been 1008acquired by the hypervisor, the FFA_RX_RELEASE call must be forwarded to 1009the SPMC to reestablish SPMC's RX ownership. 1010 1011An attempt from an SP to send a message to a normal world VM whose RX buffer 1012was acquired by the hypervisor fails with error code FFA_BUSY, to preserve 1013the RX buffer integrity. 1014The operation could then be conducted after FFA_RX_RELEASE. 1015 1016FFA_MSG_SEND2 1017~~~~~~~~~~~~~ 1018 1019Hafnium copies a message from the sender TX buffer into receiver's RX buffer. 1020For messages from SPs to VMs, operation is only possible if the SPMC owns 1021the receiver's RX buffer. 1022 1023Both receiver and sender need to enable support for indirect messaging, 1024in their respective partition manifest. The discovery of support 1025of such feature can be done via FFA_PARTITION_INFO_GET. 1026 1027On a successful message send, Hafnium pends an RX buffer full framework 1028notification for the receiver, to inform it about a message in the RX buffer. 1029 1030The handling of framework notifications is similar to that of 1031global notifications. Binding of these is not necessary, as these are 1032reserved to be used by the hypervisor or SPMC. 1033 1034SPMC-SPMD direct requests/responses 1035----------------------------------- 1036 1037Implementation-defined FF-A IDs are allocated to the SPMC and SPMD. 1038Using those IDs in source/destination fields of a direct request/response 1039permits SPMD to SPMC communication and either way. 1040 1041- SPMC to SPMD direct request/response uses SMC conduit. 1042- SPMD to SPMC direct request/response uses ERET conduit. 1043 1044This is used in particular to convey power management messages. 1045 1046Memory Sharing 1047-------------- 1048 1049Hafnium implements the following memory sharing interfaces: 1050 1051 - ``FFA_MEM_SHARE`` - for shared access between lender and borrower. 1052 - ``FFA_MEM_LEND`` - borrower to obtain exclusive access, though lender 1053 retains ownership of the memory. 1054 - ``FFA_MEM_DONATE`` - lender permanently relinquishes ownership of memory 1055 to the borrower. 1056 1057The ``FFA_MEM_RETRIEVE_REQ`` interface is for the borrower to request the 1058memory to be mapped into its address space: for S-EL1 partitions the SPM updates 1059their stage 2 translation regime; for S-EL0 partitions the SPM updates their 1060stage 1 translation regime. On a successful call, the SPMC responds back with 1061``FFA_MEM_RETRIEVE_RESP``. 1062 1063The ``FFA_MEM_RELINQUISH`` interface is for when the borrower is done with using 1064a memory region. 1065 1066The ``FFA_MEM_RECLAIM`` interface is for the owner of the memory to reestablish 1067its ownership and exclusive access to the memory shared. 1068 1069The memory transaction descriptors are transmitted via RX/TX buffers. In 1070situations where the size of the memory transaction descriptor exceeds the 1071size of the RX/TX buffers, Hafnium provides support for fragmented transmission 1072of the full transaction descriptor. The ``FFA_MEM_FRAG_RX`` and ``FFA_MEM_FRAG_TX`` 1073interfaces are for receiving and transmitting the next fragment, respectively. 1074 1075If lender and borrower(s) are SPs, all memory sharing operations are supported. 1076 1077Hafnium also supports memory sharing operations between the normal world and the 1078secure world. If there is an SP involved, the SPMC allocates data to track the 1079state of the operation. 1080 1081The SPMC is also the designated allocator for the memory handle. The hypervisor 1082or OS kernel has the possibility to rely on the SPMC to maintain the state 1083of the operation, thus saving memory. 1084A lender SP can only donate NS memory to a borrower from the normal world. 1085 1086The SPMC supports the hypervisor retrieve request, as defined by the FF-A 1087v1.1 EAC0 specification, in section 16.4.3. The intent is to aid with operations 1088that the hypervisor must do for a VM retriever. For example, when handling 1089an FFA_MEM_RECLAIM, if the hypervisor relies on SPMC to keep the state 1090of the operation, the hypervisor retrieve request can be used to obtain 1091that state information, do the necessary validations, and update stage 2 1092memory translation. 1093 1094Hafnium also supports memory lend and share targetting multiple borrowers. 1095This is the case for a lender SP to multiple SPs, and for a lender VM to 1096multiple endpoints (from both secure world and normal world). If there is 1097at least one borrower VM, the hypervisor is in charge of managing its 1098stage 2 translation on a successful memory retrieve. 1099The semantics of ``FFA_MEM_DONATE`` implies ownership transmission, 1100which should target only one partition. 1101 1102The memory share interfaces are backwards compatible with memory transaction 1103descriptors from FF-A v1.0. These get translated to FF-A v1.1 descriptors for 1104Hafnium's internal processing of the operation. If the FF-A version of a 1105borrower is v1.0, Hafnium provides FF-A v1.0 compliant memory transaction 1106descriptors on memory retrieve response. 1107 1108PE MMU configuration 1109-------------------- 1110 1111With secure virtualization enabled (``HCR_EL2.VM = 1``) and for S-EL1 1112partitions, two IPA spaces (secure and non-secure) are output from the 1113secure EL1&0 Stage-1 translation. 1114The EL1&0 Stage-2 translation hardware is fed by: 1115 1116- A secure IPA when the SP EL1&0 Stage-1 MMU is disabled. 1117- One of secure or non-secure IPA when the secure EL1&0 Stage-1 MMU is enabled. 1118 1119``VTCR_EL2`` and ``VSTCR_EL2`` provide configuration bits for controlling the 1120NS/S IPA translations. The following controls are set up: 1121``VSTCR_EL2.SW = 0`` , ``VSTCR_EL2.SA = 0``, ``VTCR_EL2.NSW = 0``, 1122``VTCR_EL2.NSA = 1``: 1123 1124- Stage-2 translations for the NS IPA space access the NS PA space. 1125- Stage-2 translation table walks for the NS IPA space are to the secure PA space. 1126 1127Secure and non-secure IPA regions (rooted to by ``VTTBR_EL2`` and ``VSTTBR_EL2``) 1128use the same set of Stage-2 page tables within a SP. 1129 1130The ``VTCR_EL2/VSTCR_EL2/VTTBR_EL2/VSTTBR_EL2`` virtual address space 1131configuration is made part of a vCPU context. 1132 1133For S-EL0 partitions with VHE enabled, a single secure EL2&0 Stage-1 translation 1134regime is used for both Hafnium and the partition. 1135 1136Schedule modes and SP Call chains 1137--------------------------------- 1138 1139An SP execution context is said to be in SPMC scheduled mode if CPU cycles are 1140allocated to it by SPMC. Correspondingly, an SP execution context is said to be 1141in Normal world scheduled mode if CPU cycles are allocated by the normal world. 1142 1143A call chain represents all SPs in a sequence of invocations of a direct message 1144request. When execution on a PE is in the secure state, only a single call chain 1145that runs in the Normal World scheduled mode can exist. FF-A v1.1 spec allows 1146any number of call chains to run in the SPMC scheduled mode but the Hafnium 1147SPMC restricts the number of call chains in SPMC scheduled mode to only one for 1148keeping the implementation simple. 1149 1150Partition runtime models 1151------------------------ 1152 1153The runtime model of an endpoint describes the transitions permitted for an 1154execution context between various states. These are the four partition runtime 1155models supported (refer to `[1]`_ section 7): 1156 1157 - RTM_FFA_RUN: runtime model presented to an execution context that is 1158 allocated CPU cycles through FFA_RUN interface. 1159 - RTM_FFA_DIR_REQ: runtime model presented to an execution context that is 1160 allocated CPU cycles through FFA_MSG_SEND_DIRECT_REQ interface. 1161 - RTM_SEC_INTERRUPT: runtime model presented to an execution context that is 1162 allocated CPU cycles by SPMC to handle a secure interrupt. 1163 - RTM_SP_INIT: runtime model presented to an execution context that is 1164 allocated CPU cycles by SPMC to initialize its state. 1165 1166If an endpoint execution context attempts to make an invalid transition or a 1167valid transition that could lead to a loop in the call chain, SPMC denies the 1168transition with the help of above runtime models. 1169 1170Interrupt management 1171-------------------- 1172 1173GIC ownership 1174~~~~~~~~~~~~~ 1175 1176The SPMC owns the GIC configuration. Secure and non-secure interrupts are 1177trapped at S-EL2. The SPMC manages interrupt resources and allocates interrupt 1178IDs based on SP manifests. The SPMC acknowledges physical interrupts and injects 1179virtual interrupts by setting the use of vIRQ/vFIQ bits before resuming a SP. 1180 1181Abbreviations: 1182 1183 - NS-Int: A non-secure physical interrupt. It requires a switch to the normal 1184 world to be handled if it triggers while execution is in secure world. 1185 - Other S-Int: A secure physical interrupt targeted to an SP different from 1186 the one that is currently running. 1187 - Self S-Int: A secure physical interrupt targeted to the SP that is currently 1188 running. 1189 1190Non-secure interrupt handling 1191~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1192 1193This section documents the actions supported in SPMC in response to a non-secure 1194interrupt as per the guidance provided by FF-A v1.1 EAC0 specification. 1195An SP specifies one of the following actions in its partition manifest: 1196 1197 - Non-secure interrupt is signaled. 1198 - Non-secure interrupt is signaled after a managed exit. 1199 - Non-secure interrupt is queued. 1200 1201An SP execution context in a call chain could specify a less permissive action 1202than subsequent SP execution contexts in the same call chain. The less 1203permissive action takes precedence over the more permissive actions specified 1204by the subsequent execution contexts. Please refer to FF-A v1.1 EAC0 section 12058.3.1 for further explanation. 1206 1207Secure interrupt handling 1208~~~~~~~~~~~~~~~~~~~~~~~~~ 1209 1210This section documents the support implemented for secure interrupt handling in 1211SPMC as per the guidance provided by FF-A v1.1 EAC0 specification. 1212The following assumptions are made about the system configuration: 1213 1214 - In the current implementation, S-EL1 SPs are expected to use the para 1215 virtualized ABIs for interrupt management rather than accessing the virtual 1216 GIC interface. 1217 - Unless explicitly stated otherwise, this support is applicable only for 1218 S-EL1 SPs managed by SPMC. 1219 - Secure interrupts are configured as G1S or G0 interrupts. 1220 - All physical interrupts are routed to SPMC when running a secure partition 1221 execution context. 1222 - All endpoints with multiple execution contexts have their contexts pinned 1223 to corresponding CPUs. Hence, a secure virtual interrupt cannot be signaled 1224 to a target vCPU that is currently running or blocked on a different 1225 physical CPU. 1226 1227A physical secure interrupt could trigger while CPU is executing in normal world 1228or secure world. 1229The action of SPMC for a secure interrupt depends on: the state of the target 1230execution context of the SP that is responsible for handling the interrupt; 1231whether the interrupt triggered while execution was in normal world or secure 1232world. 1233 1234Secure interrupt signaling mechanisms 1235~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1236 1237Signaling refers to the mechanisms used by SPMC to indicate to the SP execution 1238context that it has a pending virtual interrupt and to further run the SP 1239execution context, such that it can handle the virtual interrupt. SPMC uses 1240either the FFA_INTERRUPT interface with ERET conduit or vIRQ signal for signaling 1241to S-EL1 SPs. When normal world execution is preempted by a secure interrupt, 1242the SPMD uses the FFA_INTERRUPT ABI with ERET conduit to signal interrupt to SPMC 1243running in S-EL2. 1244 1245+-----------+---------+---------------+---------------------------------------+ 1246| SP State | Conduit | Interface and | Description | 1247| | | parameters | | 1248+-----------+---------+---------------+---------------------------------------+ 1249| WAITING | ERET, | FFA_INTERRUPT,| SPMC signals to SP the ID of pending | 1250| | vIRQ | Interrupt ID | interrupt. It pends vIRQ signal and | 1251| | | | resumes execution context of SP | 1252| | | | through ERET. | 1253+-----------+---------+---------------+---------------------------------------+ 1254| BLOCKED | ERET, | FFA_INTERRUPT | SPMC signals to SP that an interrupt | 1255| | vIRQ | | is pending. It pends vIRQ signal and | 1256| | | | resumes execution context of SP | 1257| | | | through ERET. | 1258+-----------+---------+---------------+---------------------------------------+ 1259| PREEMPTED | vIRQ | NA | SPMC pends the vIRQ signal but does | 1260| | | | not resume execution context of SP. | 1261+-----------+---------+---------------+---------------------------------------+ 1262| RUNNING | ERET, | NA | SPMC pends the vIRQ signal and resumes| 1263| | vIRQ | | execution context of SP through ERET. | 1264+-----------+---------+---------------+---------------------------------------+ 1265 1266Secure interrupt completion mechanisms 1267~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1268 1269A SP signals secure interrupt handling completion to the SPMC through the 1270following mechanisms: 1271 1272 - ``FFA_MSG_WAIT`` ABI if it was in WAITING state. 1273 - ``FFA_RUN`` ABI if its was in BLOCKED state. 1274 1275This is a remnant of SPMC implementation based on the FF-A v1.0 specification. 1276In the current implementation, S-EL1 SPs use the para-virtualized HVC interface 1277implemented by SPMC to perform priority drop and interrupt deactivation (SPMC 1278configures EOImode = 0, i.e. priority drop and deactivation are done together). 1279The SPMC performs checks to deny the state transition upon invocation of 1280either FFA_MSG_WAIT or FFA_RUN interface if the SP didn't perform the 1281deactivation of the secure virtual interrupt. 1282 1283If the current SP execution context was preempted by a secure interrupt to be 1284handled by execution context of target SP, SPMC resumes current SP after signal 1285completion by target SP execution context. 1286 1287Actions for a secure interrupt triggered while execution is in normal world 1288~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1289 1290+-------------------+----------+-----------------------------------------------+ 1291| State of target | Action | Description | 1292| execution context | | | 1293+-------------------+----------+-----------------------------------------------+ 1294| WAITING | Signaled | This starts a new call chain in SPMC scheduled| 1295| | | mode. | 1296+-------------------+----------+-----------------------------------------------+ 1297| PREEMPTED | Queued | The target execution must have been preempted | 1298| | | by a non-secure interrupt. SPMC queues the | 1299| | | secure virtual interrupt now. It is signaled | 1300| | | when the target execution context next enters | 1301| | | the RUNNING state. | 1302+-------------------+----------+-----------------------------------------------+ 1303| BLOCKED, RUNNING | NA | The target execution context is blocked or | 1304| | | running on a different CPU. This is not | 1305| | | supported by current SPMC implementation and | 1306| | | execution hits panic. | 1307+-------------------+----------+-----------------------------------------------+ 1308 1309If normal world execution was preempted by a secure interrupt, SPMC uses 1310FFA_NORMAL_WORLD_RESUME ABI to indicate completion of secure interrupt handling 1311and further returns execution to normal world. 1312 1313The following figure describes interrupt handling flow when a secure interrupt 1314triggers while execution is in normal world: 1315 1316.. image:: ../resources/diagrams/ffa-secure-interrupt-handling-nwd.png 1317 1318A brief description of the events: 1319 1320 - 1) Secure interrupt triggers while normal world is running. 1321 - 2) FIQ gets trapped to EL3. 1322 - 3) SPMD signals secure interrupt to SPMC at S-EL2 using FFA_INTERRUPT ABI. 1323 - 4) SPMC identifies target vCPU of SP and injects virtual interrupt (pends 1324 vIRQ). 1325 - 5) Assuming SP1 vCPU is in WAITING state, SPMC signals virtual interrupt 1326 using FFA_INTERRUPT with interrupt id as an argument and resumes the SP1 1327 vCPU using ERET in SPMC scheduled mode. 1328 - 6) Execution traps to vIRQ handler in SP1 provided that the virtual 1329 interrupt is not masked i.e., PSTATE.I = 0 1330 - 7) SP1 queries for the pending virtual interrupt id using a paravirtualized 1331 HVC call. SPMC clears the pending virtual interrupt state management 1332 and returns the pending virtual interrupt id. 1333 - 8) SP1 services the virtual interrupt and invokes the paravirtualized 1334 de-activation HVC call. SPMC de-activates the physical interrupt, 1335 clears the fields tracking the secure interrupt and resumes SP1 vCPU. 1336 - 9) SP1 performs secure interrupt completion through FFA_MSG_WAIT ABI. 1337 - 10) SPMC returns control to EL3 using FFA_NORMAL_WORLD_RESUME. 1338 - 11) EL3 resumes normal world execution. 1339 1340Actions for a secure interrupt triggered while execution is in secure world 1341~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1342 1343+-------------------+----------+------------------------------------------------+ 1344| State of target | Action | Description | 1345| execution context | | | 1346+-------------------+----------+------------------------------------------------+ 1347| WAITING | Signaled | This starts a new call chain in SPMC scheduled | 1348| | | mode. | 1349+-------------------+----------+------------------------------------------------+ 1350| PREEMPTED by Self | Signaled | The target execution context reenters the | 1351| S-Int | | RUNNING state to handle the secure virtual | 1352| | | interrupt. | 1353+-------------------+----------+------------------------------------------------+ 1354| PREEMPTED by | Queued | SPMC queues the secure virtual interrupt now. | 1355| NS-Int | | It is signaled when the target execution | 1356| | | context next enters the RUNNING state. | 1357+-------------------+----------+------------------------------------------------+ 1358| BLOCKED | Signaled | Both preempted and target execution contexts | 1359| | | must have been part of the Normal world | 1360| | | scheduled call chain. Refer scenario 1 of | 1361| | | Table 8.4 in the FF-A v1.1 EAC0 spec. | 1362+-------------------+----------+------------------------------------------------+ 1363| RUNNING | NA | The target execution context is running on a | 1364| | | different CPU. This scenario is not supported | 1365| | | by current SPMC implementation and execution | 1366| | | hits panic. | 1367+-------------------+----------+------------------------------------------------+ 1368 1369The following figure describes interrupt handling flow when a secure interrupt 1370triggers while execution is in secure world. We assume OS kernel sends a direct 1371request message to SP1. Further, SP1 sends a direct request message to SP2. SP1 1372enters BLOCKED state and SPMC resumes SP2. 1373 1374.. image:: ../resources/diagrams/ffa-secure-interrupt-handling-swd.png 1375 1376A brief description of the events: 1377 1378 - 1) Secure interrupt triggers while SP2 is running. 1379 - 2) SP2 gets preempted and execution traps to SPMC as IRQ. 1380 - 3) SPMC finds the target vCPU of secure partition responsible for handling 1381 this secure interrupt. In this scenario, it is SP1. 1382 - 4) SPMC pends vIRQ for SP1 and signals through FFA_INTERRUPT interface. 1383 SPMC further resumes SP1 through ERET conduit. Note that SP1 remains in 1384 Normal world schedule mode. 1385 - 6) Execution traps to vIRQ handler in SP1 provided that the virtual 1386 interrupt is not masked i.e., PSTATE.I = 0 1387 - 7) SP1 queries for the pending virtual interrupt id using a paravirtualized 1388 HVC call. SPMC clears the pending virtual interrupt state management 1389 and returns the pending virtual interrupt id. 1390 - 8) SP1 services the virtual interrupt and invokes the paravirtualized 1391 de-activation HVC call. SPMC de-activates the physical interrupt and 1392 clears the fields tracking the secure interrupt and resumes SP1 vCPU. 1393 - 9) Since SP1 direct request completed with FFA_INTERRUPT, it resumes the 1394 direct request to SP2 by invoking FFA_RUN. 1395 - 9) SPMC resumes the pre-empted vCPU of SP2. 1396 1397EL3 interrupt handling 1398~~~~~~~~~~~~~~~~~~~~~~ 1399 1400In GICv3 based systems, EL3 interrupts are configured as Group0 secure 1401interrupts. Execution traps to SPMC when a Group0 interrupt triggers while an 1402SP is running. Further, SPMC running at S-EL2 uses FFA_EL3_INTR_HANDLE ABI to 1403request EL3 platform firmware to handle a pending Group0 interrupt. 1404Similarly, SPMD registers a handler with interrupt management framework to 1405delegate handling of Group0 interrupt to the platform if the interrupt triggers 1406in normal world. 1407 1408 - Platform hook 1409 1410 - plat_spmd_handle_group0_interrupt 1411 1412 SPMD provides platform hook to handle Group0 secure interrupts. In the 1413 current design, SPMD expects the platform not to delegate handling to the 1414 NWd (such as through SDEI) while processing Group0 interrupts. 1415 1416Power management 1417---------------- 1418 1419In platforms with or without secure virtualization: 1420 1421- The NWd owns the platform PM policy. 1422- The Hypervisor or OS kernel is the component initiating PSCI service calls. 1423- The EL3 PSCI library is in charge of the PM coordination and control 1424 (eventually writing to platform registers). 1425- While coordinating PM events, the PSCI library calls backs into the Secure 1426 Payload Dispatcher for events the latter has statically registered to. 1427 1428When using the SPMD as a Secure Payload Dispatcher: 1429 1430- A power management event is relayed through the SPD hook to the SPMC. 1431- In the current implementation only cpu on (svc_on_finish) and cpu off 1432 (svc_off) hooks are registered. 1433- The behavior for the cpu on event is described in `Secondary cores boot-up`_. 1434 The SPMC is entered through its secondary physical core entry point. 1435- The cpu off event occurs when the NWd calls PSCI_CPU_OFF. The PM event is 1436 signaled to the SPMC through a power management framework message. 1437 It consists in a SPMD-to-SPMC direct request/response (`SPMC-SPMD direct 1438 requests/responses`_) conveying the event details and SPMC response. 1439 The SPMD performs a synchronous entry into the SPMC. The SPMC is entered and 1440 updates its internal state to reflect the physical core is being turned off. 1441 In the current implementation no SP is resumed as a consequence. This behavior 1442 ensures a minimal support for CPU hotplug e.g. when initiated by the NWd linux 1443 userspace. 1444 1445Arm architecture extensions for security hardening 1446================================================== 1447 1448Hafnium supports the following architecture extensions for security hardening: 1449 1450- Pointer authentication (FEAT_PAuth): the extension permits detection of forged 1451 pointers used by ROP type of attacks through the signing of the pointer 1452 value. Hafnium is built with the compiler branch protection option to permit 1453 generation of a pointer authentication code for return addresses (pointer 1454 authentication for instructions). The APIA key is used while Hafnium runs. 1455 A random key is generated at boot time and restored upon entry into Hafnium 1456 at run-time. APIA and other keys (APIB, APDA, APDB, APGA) are saved/restored 1457 in vCPU contexts permitting to enable pointer authentication in VMs/SPs. 1458- Branch Target Identification (FEAT_BTI): the extension permits detection of 1459 unexpected indirect branches used by JOP type of attacks. Hafnium is built 1460 with the compiler branch protection option, inserting land pads at function 1461 prologues that are reached by indirect branch instructions (BR/BLR). 1462 Hafnium code pages are marked as guarded in the EL2 Stage-1 MMU descriptors 1463 such that an indirect branch must always target a landpad. A fault is 1464 triggered otherwise. VMs/SPs can (independently) mark their code pages as 1465 guarded in the EL1&0 Stage-1 translation regime. 1466- Memory Tagging Extension (FEAT_MTE): the option permits detection of out of 1467 bound memory array accesses or re-use of an already freed memory region. 1468 Hafnium enables the compiler option permitting to leverage MTE stack tagging 1469 applied to core stacks. Core stacks are marked as normal tagged memory in the 1470 EL2 Stage-1 translation regime. A synchronous data abort is generated upon tag 1471 check failure on load/stores. A random seed is generated at boot time and 1472 restored upon entry into Hafnium. MTE system registers are saved/restored in 1473 vCPU contexts permitting MTE usage from VMs/SPs. 1474 1475SMMUv3 support in Hafnium 1476========================= 1477 1478An SMMU is analogous to an MMU in a CPU. It performs address translations for 1479Direct Memory Access (DMA) requests from system I/O devices. 1480The responsibilities of an SMMU include: 1481 1482- Translation: Incoming DMA requests are translated from bus address space to 1483 system physical address space using translation tables compliant to 1484 Armv8/Armv7 VMSA descriptor format. 1485- Protection: An I/O device can be prohibited from read, write access to a 1486 memory region or allowed. 1487- Isolation: Traffic from each individial device can be independently managed. 1488 The devices are differentiated from each other using unique translation 1489 tables. 1490 1491The following diagram illustrates a typical SMMU IP integrated in a SoC with 1492several I/O devices along with Interconnect and Memory system. 1493 1494.. image:: ../resources/diagrams/MMU-600.png 1495 1496SMMU has several versions including SMMUv1, SMMUv2 and SMMUv3. Hafnium provides 1497support for SMMUv3 driver in both normal and secure world. A brief introduction 1498of SMMUv3 functionality and the corresponding software support in Hafnium is 1499provided here. 1500 1501SMMUv3 features 1502--------------- 1503 1504- SMMUv3 provides Stage1, Stage2 translation as well as nested (Stage1 + Stage2) 1505 translation support. It can either bypass or abort incoming translations as 1506 well. 1507- Traffic (memory transactions) from each upstream I/O peripheral device, 1508 referred to as Stream, can be independently managed using a combination of 1509 several memory based configuration structures. This allows the SMMUv3 to 1510 support a large number of streams with each stream assigned to a unique 1511 translation context. 1512- Support for Armv8.1 VMSA where the SMMU shares the translation tables with 1513 a Processing Element. AArch32(LPAE) and AArch64 translation table format 1514 are supported by SMMUv3. 1515- SMMUv3 offers non-secure stream support with secure stream support being 1516 optional. Logically, SMMUv3 behaves as if there is an indepdendent SMMU 1517 instance for secure and non-secure stream support. 1518- It also supports sub-streams to differentiate traffic from a virtualized 1519 peripheral associated with a VM/SP. 1520- Additionally, SMMUv3.2 provides support for PEs implementing Armv8.4-A 1521 extensions. Consequently, SPM depends on Secure EL2 support in SMMUv3.2 1522 for providing Secure Stage2 translation support to upstream peripheral 1523 devices. 1524 1525SMMUv3 Programming Interfaces 1526----------------------------- 1527 1528SMMUv3 has three software interfaces that are used by the Hafnium driver to 1529configure the behaviour of SMMUv3 and manage the streams. 1530 1531- Memory based data strutures that provide unique translation context for 1532 each stream. 1533- Memory based circular buffers for command queue and event queue. 1534- A large number of SMMU configuration registers that are memory mapped during 1535 boot time by Hafnium driver. Except a few registers, all configuration 1536 registers have independent secure and non-secure versions to configure the 1537 behaviour of SMMUv3 for translation of secure and non-secure streams 1538 respectively. 1539 1540Peripheral device manifest 1541-------------------------- 1542 1543Currently, SMMUv3 driver in Hafnium only supports dependent peripheral devices. 1544These devices are dependent on PE endpoint to initiate and receive memory 1545management transactions on their behalf. The acccess to the MMIO regions of 1546any such device is assigned to the endpoint during boot. Moreover, SMMUv3 driver 1547uses the same stage 2 translations for the device as those used by partition 1548manager on behalf of the PE endpoint. This ensures that the peripheral device 1549has the same visibility of the physical address space as the endpoint. The 1550device node of the corresponding partition manifest (refer to `[1]`_ section 3.2 1551) must specify these additional properties for each peripheral device in the 1552system : 1553 1554- smmu-id: This field helps to identify the SMMU instance that this device is 1555 upstream of. 1556- stream-ids: List of stream IDs assigned to this device. 1557 1558.. code:: shell 1559 1560 smmuv3-testengine { 1561 base-address = <0x00000000 0x2bfe0000>; 1562 pages-count = <32>; 1563 attributes = <0x3>; 1564 smmu-id = <0>; 1565 stream-ids = <0x0 0x1>; 1566 interrupts = <0x2 0x3>, <0x4 0x5>; 1567 exclusive-access; 1568 }; 1569 1570SMMUv3 driver limitations 1571------------------------- 1572 1573The primary design goal for the Hafnium SMMU driver is to support secure 1574streams. 1575 1576- Currently, the driver only supports Stage2 translations. No support for 1577 Stage1 or nested translations. 1578- Supports only AArch64 translation format. 1579- No support for features such as PCI Express (PASIDs, ATS, PRI), MSI, RAS, 1580 Fault handling, Performance Monitor Extensions, Event Handling, MPAM. 1581- No support for independent peripheral devices. 1582 1583S-EL0 Partition support 1584======================= 1585The SPMC (Hafnium) has limited capability to run S-EL0 FF-A partitions using 1586FEAT_VHE (mandatory with ARMv8.1 in non-secure state, and in secure world 1587with ARMv8.4 and FEAT_SEL2). 1588 1589S-EL0 partitions are useful for simple partitions that don't require full 1590Trusted OS functionality. It is also useful to reduce jitter and cycle 1591stealing from normal world since they are more lightweight than VMs. 1592 1593S-EL0 partitions are presented, loaded and initialized the same as S-EL1 VMs by 1594the SPMC. They are differentiated primarily by the 'exception-level' property 1595and the 'execution-ctx-count' property in the SP manifest. They are host apps 1596under the single EL2&0 Stage-1 translation regime controlled by the SPMC and 1597call into the SPMC through SVCs as opposed to HVCs and SMCs. These partitions 1598can use FF-A defined services (FFA_MEM_PERM_*) to update or change permissions 1599for memory regions. 1600 1601S-EL0 partitions are required by the FF-A specification to be UP endpoints, 1602capable of migrating, and the SPMC enforces this requirement. The SPMC allows 1603a S-EL0 partition to accept a direct message from secure world and normal world, 1604and generate direct responses to them. 1605All S-EL0 partitions must use AArch64. AArch32 S-EL0 partitions are not supported. 1606 1607Memory sharing, indirect messaging, and notifications functionality with S-EL0 1608partitions is supported. 1609 1610Interrupt handling is not supported with S-EL0 partitions and is work in 1611progress. 1612 1613References 1614========== 1615 1616.. _[1]: 1617 1618[1] `Arm Firmware Framework for Arm A-profile <https://developer.arm.com/docs/den0077/latest>`__ 1619 1620.. _[2]: 1621 1622[2] :ref:`Secure Partition Manager using MM interface<Secure Partition Manager (MM)>` 1623 1624.. _[3]: 1625 1626[3] `Trusted Boot Board Requirements 1627Client <https://developer.arm.com/documentation/den0006/d/>`__ 1628 1629.. _[4]: 1630 1631[4] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/lib/el3_runtime/aarch64/context.S#n45 1632 1633.. _[5]: 1634 1635[5] https://git.trustedfirmware.org/TF-A/tf-a-tests.git/tree/spm/cactus/plat/arm/fvp/fdts/cactus.dts 1636 1637.. _[6]: 1638 1639[6] https://trustedfirmware-a.readthedocs.io/en/latest/components/ffa-manifest-binding.html 1640 1641.. _[7]: 1642 1643[7] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts 1644 1645.. _[8]: 1646 1647[8] https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.org/thread/CFQFGU6H2D5GZYMUYGTGUSXIU3OYZP6U/ 1648 1649.. _[9]: 1650 1651[9] https://trustedfirmware-a.readthedocs.io/en/latest/design/firmware-design.html#dynamic-configuration-during-cold-boot 1652 1653-------------- 1654 1655*Copyright (c) 2020-2023, Arm Limited and Contributors. All rights reserved.* 1656
