1*68120783SChris KayMaximum Power Mitigation Mechanism (MPMM) 2*68120783SChris Kay^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 3*68120783SChris Kay 4*68120783SChris Kay|MPMM| is an optional microarchitectural power management mechanism supported by 5*68120783SChris Kaysome Arm Armv9-A cores, beginning with the Cortex-X2, Cortex-A710 and 6*68120783SChris KayCortex-A510 cores. This mechanism detects and limits high-activity events to 7*68120783SChris Kayassist in |SoC| processor power domain dynamic power budgeting and limit the 8*68120783SChris Kaytriggering of whole-rail (i.e. clock chopping) responses to overcurrent 9*68120783SChris Kayconditions. 10*68120783SChris Kay 11*68120783SChris Kay|MPMM| is enabled on a per-core basis by the EL3 runtime firmware. The presence 12*68120783SChris Kayof |MPMM| cannot be determined at runtime by the firmware, and therefore the 13*68120783SChris Kayplatform must expose this information through one of two possible mechanisms: 14*68120783SChris Kay 15*68120783SChris Kay- |FCONF|, controlled by the ``ENABLE_MPMM_FCONF`` build option. 16*68120783SChris Kay- A platform implementation of the ``plat_mpmm_topology`` function (the 17*68120783SChris Kay default). 18*68120783SChris Kay 19*68120783SChris KaySee :ref:`Maximum Power Mitigation Mechanism (MPMM) Bindings` for documentation 20*68120783SChris Kayon the |FCONF| device tree bindings. 21*68120783SChris Kay 22*68120783SChris Kay.. warning:: 23*68120783SChris Kay 24*68120783SChris Kay |MPMM| exposes gear metrics through the auxiliary |AMU| counters. An 25*68120783SChris Kay external power controller can use these metrics to budget SoC power by 26*68120783SChris Kay limiting the number of cores that can execute higher-activity workloads or 27*68120783SChris Kay switching to a different DVFS operating point. When this is the case, the 28*68120783SChris Kay |AMU| counters that make up the |MPMM| gears must be enabled by the EL3 29*68120783SChris Kay runtime firmware - please see :ref:`Activity Monitor Auxiliary Counters` for 30*68120783SChris Kay documentation on enabling auxiliary |AMU| counters. 31