16c595b3dSSandrine Bailleux/* 2*e0ae9fabSSandrine Bailleux * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 36c595b3dSSandrine Bailleux * 46c595b3dSSandrine Bailleux * Redistribution and use in source and binary forms, with or without 56c595b3dSSandrine Bailleux * modification, are permitted provided that the following conditions are met: 66c595b3dSSandrine Bailleux * 76c595b3dSSandrine Bailleux * Redistributions of source code must retain the above copyright notice, this 86c595b3dSSandrine Bailleux * list of conditions and the following disclaimer. 96c595b3dSSandrine Bailleux * 106c595b3dSSandrine Bailleux * Redistributions in binary form must reproduce the above copyright notice, 116c595b3dSSandrine Bailleux * this list of conditions and the following disclaimer in the documentation 126c595b3dSSandrine Bailleux * and/or other materials provided with the distribution. 136c595b3dSSandrine Bailleux * 146c595b3dSSandrine Bailleux * Neither the name of ARM nor the names of its contributors may be used 156c595b3dSSandrine Bailleux * to endorse or promote products derived from this software without specific 166c595b3dSSandrine Bailleux * prior written permission. 176c595b3dSSandrine Bailleux * 186c595b3dSSandrine Bailleux * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 196c595b3dSSandrine Bailleux * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 206c595b3dSSandrine Bailleux * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 216c595b3dSSandrine Bailleux * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 226c595b3dSSandrine Bailleux * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 236c595b3dSSandrine Bailleux * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 246c595b3dSSandrine Bailleux * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 256c595b3dSSandrine Bailleux * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 266c595b3dSSandrine Bailleux * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 276c595b3dSSandrine Bailleux * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 286c595b3dSSandrine Bailleux * POSSIBILITY OF SUCH DAMAGE. 296c595b3dSSandrine Bailleux */ 306c595b3dSSandrine Bailleux 316c595b3dSSandrine Bailleux#include <asm_macros.S> 32bbf8f6f9SYatharth Kochar#include <bl_common.h> 336c595b3dSSandrine Bailleux 34*e0ae9fabSSandrine Bailleux/* ----------------------------------------------------------------------------- 35*e0ae9fabSSandrine Bailleux * Very simple stackless exception handlers used by BL2 and BL31 stages. 36*e0ae9fabSSandrine Bailleux * BL31 uses them before stacks are setup. BL2 uses them throughout. 37*e0ae9fabSSandrine Bailleux * ----------------------------------------------------------------------------- 38*e0ae9fabSSandrine Bailleux */ 396c595b3dSSandrine Bailleux .globl early_exceptions 406c595b3dSSandrine Bailleux 41*e0ae9fabSSandrine Bailleuxvector_base early_exceptions 426c595b3dSSandrine Bailleux 436c595b3dSSandrine Bailleux /* ----------------------------------------------------- 44*e0ae9fabSSandrine Bailleux * Current EL with SP0 : 0x0 - 0x200 456c595b3dSSandrine Bailleux * ----------------------------------------------------- 466c595b3dSSandrine Bailleux */ 47*e0ae9fabSSandrine Bailleuxvector_entry SynchronousExceptionSP0 486c595b3dSSandrine Bailleux mov x0, #SYNC_EXCEPTION_SP_EL0 496c595b3dSSandrine Bailleux bl plat_report_exception 506c595b3dSSandrine Bailleux b SynchronousExceptionSP0 516c595b3dSSandrine Bailleux check_vector_size SynchronousExceptionSP0 526c595b3dSSandrine Bailleux 53*e0ae9fabSSandrine Bailleuxvector_entry IrqSP0 546c595b3dSSandrine Bailleux mov x0, #IRQ_SP_EL0 556c595b3dSSandrine Bailleux bl plat_report_exception 566c595b3dSSandrine Bailleux b IrqSP0 576c595b3dSSandrine Bailleux check_vector_size IrqSP0 586c595b3dSSandrine Bailleux 59*e0ae9fabSSandrine Bailleuxvector_entry FiqSP0 606c595b3dSSandrine Bailleux mov x0, #FIQ_SP_EL0 616c595b3dSSandrine Bailleux bl plat_report_exception 626c595b3dSSandrine Bailleux b FiqSP0 636c595b3dSSandrine Bailleux check_vector_size FiqSP0 646c595b3dSSandrine Bailleux 65*e0ae9fabSSandrine Bailleuxvector_entry SErrorSP0 666c595b3dSSandrine Bailleux mov x0, #SERROR_SP_EL0 676c595b3dSSandrine Bailleux bl plat_report_exception 686c595b3dSSandrine Bailleux b SErrorSP0 696c595b3dSSandrine Bailleux check_vector_size SErrorSP0 706c595b3dSSandrine Bailleux 716c595b3dSSandrine Bailleux /* ----------------------------------------------------- 72*e0ae9fabSSandrine Bailleux * Current EL with SPx: 0x200 - 0x400 736c595b3dSSandrine Bailleux * ----------------------------------------------------- 746c595b3dSSandrine Bailleux */ 75*e0ae9fabSSandrine Bailleuxvector_entry SynchronousExceptionSPx 766c595b3dSSandrine Bailleux mov x0, #SYNC_EXCEPTION_SP_ELX 776c595b3dSSandrine Bailleux bl plat_report_exception 786c595b3dSSandrine Bailleux b SynchronousExceptionSPx 796c595b3dSSandrine Bailleux check_vector_size SynchronousExceptionSPx 806c595b3dSSandrine Bailleux 81*e0ae9fabSSandrine Bailleuxvector_entry IrqSPx 826c595b3dSSandrine Bailleux mov x0, #IRQ_SP_ELX 836c595b3dSSandrine Bailleux bl plat_report_exception 846c595b3dSSandrine Bailleux b IrqSPx 856c595b3dSSandrine Bailleux check_vector_size IrqSPx 866c595b3dSSandrine Bailleux 87*e0ae9fabSSandrine Bailleuxvector_entry FiqSPx 886c595b3dSSandrine Bailleux mov x0, #FIQ_SP_ELX 896c595b3dSSandrine Bailleux bl plat_report_exception 906c595b3dSSandrine Bailleux b FiqSPx 916c595b3dSSandrine Bailleux check_vector_size FiqSPx 926c595b3dSSandrine Bailleux 93*e0ae9fabSSandrine Bailleuxvector_entry SErrorSPx 946c595b3dSSandrine Bailleux mov x0, #SERROR_SP_ELX 956c595b3dSSandrine Bailleux bl plat_report_exception 966c595b3dSSandrine Bailleux b SErrorSPx 976c595b3dSSandrine Bailleux check_vector_size SErrorSPx 986c595b3dSSandrine Bailleux 996c595b3dSSandrine Bailleux /* ----------------------------------------------------- 100*e0ae9fabSSandrine Bailleux * Lower EL using AArch64 : 0x400 - 0x600 1016c595b3dSSandrine Bailleux * ----------------------------------------------------- 1026c595b3dSSandrine Bailleux */ 103*e0ae9fabSSandrine Bailleuxvector_entry SynchronousExceptionA64 1046c595b3dSSandrine Bailleux mov x0, #SYNC_EXCEPTION_AARCH64 1056c595b3dSSandrine Bailleux bl plat_report_exception 1066c595b3dSSandrine Bailleux b SynchronousExceptionA64 1076c595b3dSSandrine Bailleux check_vector_size SynchronousExceptionA64 1086c595b3dSSandrine Bailleux 109*e0ae9fabSSandrine Bailleuxvector_entry IrqA64 1106c595b3dSSandrine Bailleux mov x0, #IRQ_AARCH64 1116c595b3dSSandrine Bailleux bl plat_report_exception 1126c595b3dSSandrine Bailleux b IrqA64 1136c595b3dSSandrine Bailleux check_vector_size IrqA64 1146c595b3dSSandrine Bailleux 115*e0ae9fabSSandrine Bailleuxvector_entry FiqA64 1166c595b3dSSandrine Bailleux mov x0, #FIQ_AARCH64 1176c595b3dSSandrine Bailleux bl plat_report_exception 1186c595b3dSSandrine Bailleux b FiqA64 1196c595b3dSSandrine Bailleux check_vector_size FiqA64 1206c595b3dSSandrine Bailleux 121*e0ae9fabSSandrine Bailleuxvector_entry SErrorA64 1226c595b3dSSandrine Bailleux mov x0, #SERROR_AARCH64 1236c595b3dSSandrine Bailleux bl plat_report_exception 1246c595b3dSSandrine Bailleux b SErrorA64 1256c595b3dSSandrine Bailleux check_vector_size SErrorA64 1266c595b3dSSandrine Bailleux 1276c595b3dSSandrine Bailleux /* ----------------------------------------------------- 128*e0ae9fabSSandrine Bailleux * Lower EL using AArch32 : 0x600 - 0x800 1296c595b3dSSandrine Bailleux * ----------------------------------------------------- 1306c595b3dSSandrine Bailleux */ 131*e0ae9fabSSandrine Bailleuxvector_entry SynchronousExceptionA32 1326c595b3dSSandrine Bailleux mov x0, #SYNC_EXCEPTION_AARCH32 1336c595b3dSSandrine Bailleux bl plat_report_exception 1346c595b3dSSandrine Bailleux b SynchronousExceptionA32 1356c595b3dSSandrine Bailleux check_vector_size SynchronousExceptionA32 1366c595b3dSSandrine Bailleux 137*e0ae9fabSSandrine Bailleuxvector_entry IrqA32 1386c595b3dSSandrine Bailleux mov x0, #IRQ_AARCH32 1396c595b3dSSandrine Bailleux bl plat_report_exception 1406c595b3dSSandrine Bailleux b IrqA32 1416c595b3dSSandrine Bailleux check_vector_size IrqA32 1426c595b3dSSandrine Bailleux 143*e0ae9fabSSandrine Bailleuxvector_entry FiqA32 1446c595b3dSSandrine Bailleux mov x0, #FIQ_AARCH32 1456c595b3dSSandrine Bailleux bl plat_report_exception 1466c595b3dSSandrine Bailleux b FiqA32 1476c595b3dSSandrine Bailleux check_vector_size FiqA32 1486c595b3dSSandrine Bailleux 149*e0ae9fabSSandrine Bailleuxvector_entry SErrorA32 1506c595b3dSSandrine Bailleux mov x0, #SERROR_AARCH32 1516c595b3dSSandrine Bailleux bl plat_report_exception 1526c595b3dSSandrine Bailleux b SErrorA32 1536c595b3dSSandrine Bailleux check_vector_size SErrorA32 154