16c595b3dSSandrine Bailleux/* 2e0ae9fabSSandrine Bailleux * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 36c595b3dSSandrine Bailleux * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 56c595b3dSSandrine Bailleux */ 66c595b3dSSandrine Bailleux 76c595b3dSSandrine Bailleux#include <asm_macros.S> 8bbf8f6f9SYatharth Kochar#include <bl_common.h> 96c595b3dSSandrine Bailleux 10e0ae9fabSSandrine Bailleux/* ----------------------------------------------------------------------------- 11e0ae9fabSSandrine Bailleux * Very simple stackless exception handlers used by BL2 and BL31 stages. 12e0ae9fabSSandrine Bailleux * BL31 uses them before stacks are setup. BL2 uses them throughout. 13e0ae9fabSSandrine Bailleux * ----------------------------------------------------------------------------- 14e0ae9fabSSandrine Bailleux */ 156c595b3dSSandrine Bailleux .globl early_exceptions 166c595b3dSSandrine Bailleux 17e0ae9fabSSandrine Bailleuxvector_base early_exceptions 186c595b3dSSandrine Bailleux 196c595b3dSSandrine Bailleux /* ----------------------------------------------------- 20e0ae9fabSSandrine Bailleux * Current EL with SP0 : 0x0 - 0x200 216c595b3dSSandrine Bailleux * ----------------------------------------------------- 226c595b3dSSandrine Bailleux */ 23e0ae9fabSSandrine Bailleuxvector_entry SynchronousExceptionSP0 246c595b3dSSandrine Bailleux mov x0, #SYNC_EXCEPTION_SP_EL0 256c595b3dSSandrine Bailleux bl plat_report_exception 26a806dad5SJeenu Viswambharan no_ret plat_panic_handler 276c595b3dSSandrine Bailleux check_vector_size SynchronousExceptionSP0 286c595b3dSSandrine Bailleux 29e0ae9fabSSandrine Bailleuxvector_entry IrqSP0 306c595b3dSSandrine Bailleux mov x0, #IRQ_SP_EL0 316c595b3dSSandrine Bailleux bl plat_report_exception 32a806dad5SJeenu Viswambharan no_ret plat_panic_handler 336c595b3dSSandrine Bailleux check_vector_size IrqSP0 346c595b3dSSandrine Bailleux 35e0ae9fabSSandrine Bailleuxvector_entry FiqSP0 366c595b3dSSandrine Bailleux mov x0, #FIQ_SP_EL0 376c595b3dSSandrine Bailleux bl plat_report_exception 38a806dad5SJeenu Viswambharan no_ret plat_panic_handler 396c595b3dSSandrine Bailleux check_vector_size FiqSP0 406c595b3dSSandrine Bailleux 41e0ae9fabSSandrine Bailleuxvector_entry SErrorSP0 426c595b3dSSandrine Bailleux mov x0, #SERROR_SP_EL0 436c595b3dSSandrine Bailleux bl plat_report_exception 44a806dad5SJeenu Viswambharan no_ret plat_panic_handler 456c595b3dSSandrine Bailleux check_vector_size SErrorSP0 466c595b3dSSandrine Bailleux 476c595b3dSSandrine Bailleux /* ----------------------------------------------------- 48e0ae9fabSSandrine Bailleux * Current EL with SPx: 0x200 - 0x400 496c595b3dSSandrine Bailleux * ----------------------------------------------------- 506c595b3dSSandrine Bailleux */ 51e0ae9fabSSandrine Bailleuxvector_entry SynchronousExceptionSPx 526c595b3dSSandrine Bailleux mov x0, #SYNC_EXCEPTION_SP_ELX 536c595b3dSSandrine Bailleux bl plat_report_exception 54a806dad5SJeenu Viswambharan no_ret plat_panic_handler 556c595b3dSSandrine Bailleux check_vector_size SynchronousExceptionSPx 566c595b3dSSandrine Bailleux 57e0ae9fabSSandrine Bailleuxvector_entry IrqSPx 586c595b3dSSandrine Bailleux mov x0, #IRQ_SP_ELX 596c595b3dSSandrine Bailleux bl plat_report_exception 60a806dad5SJeenu Viswambharan no_ret plat_panic_handler 616c595b3dSSandrine Bailleux check_vector_size IrqSPx 626c595b3dSSandrine Bailleux 63e0ae9fabSSandrine Bailleuxvector_entry FiqSPx 646c595b3dSSandrine Bailleux mov x0, #FIQ_SP_ELX 656c595b3dSSandrine Bailleux bl plat_report_exception 66a806dad5SJeenu Viswambharan no_ret plat_panic_handler 676c595b3dSSandrine Bailleux check_vector_size FiqSPx 686c595b3dSSandrine Bailleux 69e0ae9fabSSandrine Bailleuxvector_entry SErrorSPx 706c595b3dSSandrine Bailleux mov x0, #SERROR_SP_ELX 716c595b3dSSandrine Bailleux bl plat_report_exception 72a806dad5SJeenu Viswambharan no_ret plat_panic_handler 736c595b3dSSandrine Bailleux check_vector_size SErrorSPx 746c595b3dSSandrine Bailleux 756c595b3dSSandrine Bailleux /* ----------------------------------------------------- 76e0ae9fabSSandrine Bailleux * Lower EL using AArch64 : 0x400 - 0x600 776c595b3dSSandrine Bailleux * ----------------------------------------------------- 786c595b3dSSandrine Bailleux */ 79e0ae9fabSSandrine Bailleuxvector_entry SynchronousExceptionA64 806c595b3dSSandrine Bailleux mov x0, #SYNC_EXCEPTION_AARCH64 816c595b3dSSandrine Bailleux bl plat_report_exception 82a806dad5SJeenu Viswambharan no_ret plat_panic_handler 836c595b3dSSandrine Bailleux check_vector_size SynchronousExceptionA64 846c595b3dSSandrine Bailleux 85e0ae9fabSSandrine Bailleuxvector_entry IrqA64 866c595b3dSSandrine Bailleux mov x0, #IRQ_AARCH64 876c595b3dSSandrine Bailleux bl plat_report_exception 88a806dad5SJeenu Viswambharan no_ret plat_panic_handler 896c595b3dSSandrine Bailleux check_vector_size IrqA64 906c595b3dSSandrine Bailleux 91e0ae9fabSSandrine Bailleuxvector_entry FiqA64 926c595b3dSSandrine Bailleux mov x0, #FIQ_AARCH64 936c595b3dSSandrine Bailleux bl plat_report_exception 94a806dad5SJeenu Viswambharan no_ret plat_panic_handler 956c595b3dSSandrine Bailleux check_vector_size FiqA64 966c595b3dSSandrine Bailleux 97e0ae9fabSSandrine Bailleuxvector_entry SErrorA64 986c595b3dSSandrine Bailleux mov x0, #SERROR_AARCH64 996c595b3dSSandrine Bailleux bl plat_report_exception 100a806dad5SJeenu Viswambharan no_ret plat_panic_handler 1016c595b3dSSandrine Bailleux check_vector_size SErrorA64 1026c595b3dSSandrine Bailleux 1036c595b3dSSandrine Bailleux /* ----------------------------------------------------- 104e0ae9fabSSandrine Bailleux * Lower EL using AArch32 : 0x600 - 0x800 1056c595b3dSSandrine Bailleux * ----------------------------------------------------- 1066c595b3dSSandrine Bailleux */ 107e0ae9fabSSandrine Bailleuxvector_entry SynchronousExceptionA32 1086c595b3dSSandrine Bailleux mov x0, #SYNC_EXCEPTION_AARCH32 1096c595b3dSSandrine Bailleux bl plat_report_exception 110a806dad5SJeenu Viswambharan no_ret plat_panic_handler 1116c595b3dSSandrine Bailleux check_vector_size SynchronousExceptionA32 1126c595b3dSSandrine Bailleux 113e0ae9fabSSandrine Bailleuxvector_entry IrqA32 1146c595b3dSSandrine Bailleux mov x0, #IRQ_AARCH32 1156c595b3dSSandrine Bailleux bl plat_report_exception 116a806dad5SJeenu Viswambharan no_ret plat_panic_handler 1176c595b3dSSandrine Bailleux check_vector_size IrqA32 1186c595b3dSSandrine Bailleux 119e0ae9fabSSandrine Bailleuxvector_entry FiqA32 1206c595b3dSSandrine Bailleux mov x0, #FIQ_AARCH32 1216c595b3dSSandrine Bailleux bl plat_report_exception 122a806dad5SJeenu Viswambharan no_ret plat_panic_handler 1236c595b3dSSandrine Bailleux check_vector_size FiqA32 1246c595b3dSSandrine Bailleux 125e0ae9fabSSandrine Bailleuxvector_entry SErrorA32 1266c595b3dSSandrine Bailleux mov x0, #SERROR_AARCH32 1276c595b3dSSandrine Bailleux bl plat_report_exception 128a806dad5SJeenu Viswambharan no_ret plat_panic_handler 1296c595b3dSSandrine Bailleux check_vector_size SErrorA32 130