xref: /rk3399_ARM-atf/bl32/tsp/tsp.ld.S (revision f43e09a12e4f4f32185d3e2accceb65895d1f16b) 
1/*
2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/bl_common.ld.h>
8#include <lib/xlat_tables/xlat_tables_defs.h>
9
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(tsp_entrypoint)
13
14MEMORY {
15    RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE
16}
17
18SECTIONS {
19    RAM_REGION_START = ORIGIN(RAM);
20    RAM_REGION_LENGTH = LENGTH(RAM);
21    . = BL32_BASE;
22
23    ASSERT(. == ALIGN(PAGE_SIZE),
24        "BL32_BASE address is not aligned on a page boundary.")
25
26#if SEPARATE_CODE_AND_RODATA
27    .text . : {
28        __TEXT_START__ = .;
29
30        *tsp_entrypoint.o(.text*)
31        *(.text*)
32        *(.vectors)
33
34        . = ALIGN(PAGE_SIZE);
35
36        __TEXT_END__ = .;
37    } >RAM
38
39    .rodata . : {
40        __RODATA_START__ = .;
41
42        *(.rodata*)
43
44        RODATA_COMMON
45
46        . = ALIGN(PAGE_SIZE);
47
48        __RODATA_END__ = .;
49    } >RAM
50#else /* SEPARATE_CODE_AND_RODATA */
51    .ro . : {
52        __RO_START__ = .;
53
54        *tsp_entrypoint.o(.text*)
55        *(.text*)
56        *(.rodata*)
57
58        RODATA_COMMON
59
60        *(.vectors)
61
62        __RO_END_UNALIGNED__ = .;
63
64        /*
65         * Memory page(s) mapped to this section will be marked as read-only,
66         * executable. No RW data from the next section must creep in. Ensure
67         * that the rest of the current memory page is unused.
68         */
69        . = ALIGN(PAGE_SIZE);
70
71        __RO_END__ = .;
72    } >RAM
73#endif /* SEPARATE_CODE_AND_RODATA */
74
75    __RW_START__ = .;
76
77    DATA_SECTION >RAM
78    RELA_SECTION >RAM
79
80#ifdef TSP_PROGBITS_LIMIT
81    ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.")
82#endif /* TSP_PROGBITS_LIMIT */
83
84    STACK_SECTION >RAM
85    BSS_SECTION >RAM
86    XLAT_TABLE_SECTION >RAM
87
88#if USE_COHERENT_MEM
89    /*
90     * The base address of the coherent memory section must be page-aligned to
91     * guarantee that the coherent data are stored on their own pages and are
92     * not mixed with normal data. This is required to set up the correct memory
93     * attributes for the coherent data page tables.
94     */
95    .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
96        __COHERENT_RAM_START__ = .;
97        *(.tzfw_coherent_mem)
98        __COHERENT_RAM_END_UNALIGNED__ = .;
99
100        /*
101         * Memory page(s) mapped to this section will be marked as device
102         * memory. No other unexpected data must creep in. Ensure that the rest
103         * of the current memory page is unused.
104         */
105        . = ALIGN(PAGE_SIZE);
106
107        __COHERENT_RAM_END__ = .;
108    } >RAM
109#endif /* USE_COHERENT_MEM */
110
111    __RW_END__ = .;
112    __BL32_END__ = .;
113
114    /DISCARD/ : {
115        *(.dynsym .dynstr .hash .gnu.hash)
116    }
117
118    __BSS_SIZE__ = SIZEOF(.bss);
119
120#if USE_COHERENT_MEM
121    __COHERENT_RAM_UNALIGNED_SIZE__ =
122        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
123#endif /* USE_COHERENT_MEM */
124
125    ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.")
126    RAM_REGION_END = .;
127}
128