xref: /rk3399_ARM-atf/bl32/tsp/tsp.ld.S (revision f29d1e0c72e6665ba4c8ab11bad83f59669ea0d9) 
1/*
2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/bl_common.ld.h>
8#include <lib/xlat_tables/xlat_tables_defs.h>
9#include <platform_def.h>
10
11OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
12OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
13ENTRY(tsp_entrypoint)
14
15
16MEMORY {
17    RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE
18}
19
20
21SECTIONS
22{
23    . = BL32_BASE;
24    ASSERT(. == ALIGN(PAGE_SIZE),
25           "BL32_BASE address is not aligned on a page boundary.")
26
27#if SEPARATE_CODE_AND_RODATA
28    .text . : {
29        __TEXT_START__ = .;
30        *tsp_entrypoint.o(.text*)
31        *(.text*)
32        *(.vectors)
33        . = ALIGN(PAGE_SIZE);
34        __TEXT_END__ = .;
35    } >RAM
36
37    .rodata . : {
38        __RODATA_START__ = .;
39        *(.rodata*)
40
41        /*
42         * Keep the .got section in the RO section as it is patched
43         * prior to enabling the MMU and having the .got in RO is better for
44         * security. GOT is a table of addresses so ensure 8-byte alignment.
45         */
46        . = ALIGN(8);
47        __GOT_START__ = .;
48        *(.got)
49        __GOT_END__ = .;
50
51        . = ALIGN(PAGE_SIZE);
52        __RODATA_END__ = .;
53    } >RAM
54#else
55    ro . : {
56        __RO_START__ = .;
57        *tsp_entrypoint.o(.text*)
58        *(.text*)
59        *(.rodata*)
60
61        /*
62         * Keep the .got section in the RO section as it is patched
63         * prior to enabling the MMU and having the .got in RO is better for
64         * security. GOT is a table of addresses so ensure 8-byte alignment.
65         */
66        . = ALIGN(8);
67        __GOT_START__ = .;
68        *(.got)
69        __GOT_END__ = .;
70
71        *(.vectors)
72
73        __RO_END_UNALIGNED__ = .;
74        /*
75         * Memory page(s) mapped to this section will be marked as
76         * read-only, executable.  No RW data from the next section must
77         * creep in.  Ensure the rest of the current memory page is unused.
78         */
79        . = ALIGN(PAGE_SIZE);
80        __RO_END__ = .;
81    } >RAM
82#endif
83
84    /*
85     * Define a linker symbol to mark start of the RW memory area for this
86     * image.
87     */
88    __RW_START__ = . ;
89
90    .data . : {
91        __DATA_START__ = .;
92        *(.data*)
93        __DATA_END__ = .;
94    } >RAM
95
96    /*
97     * .rela.dyn needs to come after .data for the read-elf utility to parse
98     * this section correctly. Ensure 8-byte alignment so that the fields of
99     * RELA data structure are aligned.
100     */
101    . = ALIGN(8);
102    __RELA_START__ = .;
103    .rela.dyn . : {
104    } >RAM
105    __RELA_END__ = .;
106
107#ifdef TSP_PROGBITS_LIMIT
108    ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.")
109#endif
110
111    stacks (NOLOAD) : {
112        __STACKS_START__ = .;
113        *(tzfw_normal_stacks)
114        __STACKS_END__ = .;
115    } >RAM
116
117    /*
118     * The .bss section gets initialised to 0 at runtime.
119     * Its base address should be 16-byte aligned for better performance of the
120     * zero-initialization code.
121     */
122    .bss : ALIGN(16) {
123        __BSS_START__ = .;
124        *(SORT_BY_ALIGNMENT(.bss*))
125        *(COMMON)
126        __BSS_END__ = .;
127    } >RAM
128
129    XLAT_TABLE_SECTION >RAM
130
131#if USE_COHERENT_MEM
132    /*
133     * The base address of the coherent memory section must be page-aligned (4K)
134     * to guarantee that the coherent data are stored on their own pages and
135     * are not mixed with normal data.  This is required to set up the correct
136     * memory attributes for the coherent data page tables.
137     */
138    coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
139        __COHERENT_RAM_START__ = .;
140        *(tzfw_coherent_mem)
141        __COHERENT_RAM_END_UNALIGNED__ = .;
142        /*
143         * Memory page(s) mapped to this section will be marked
144         * as device memory.  No other unexpected data must creep in.
145         * Ensure the rest of the current memory page is unused.
146         */
147        . = ALIGN(PAGE_SIZE);
148        __COHERENT_RAM_END__ = .;
149    } >RAM
150#endif
151
152    /*
153     * Define a linker symbol to mark the end of the RW memory area for this
154     * image.
155     */
156    __RW_END__ = .;
157    __BL32_END__ = .;
158
159    /DISCARD/ : {
160        *(.dynsym .dynstr .hash .gnu.hash)
161    }
162
163    __BSS_SIZE__ = SIZEOF(.bss);
164#if USE_COHERENT_MEM
165    __COHERENT_RAM_UNALIGNED_SIZE__ =
166        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
167#endif
168
169    ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.")
170}
171