xref: /rk3399_ARM-atf/bl32/tsp/tsp.ld.S (revision 6bb49c876c7593ed5f61c20ef3d989dcff8e8d8c) 
1/*
2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/bl_common.ld.h>
8#include <lib/xlat_tables/xlat_tables_defs.h>
9
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(tsp_entrypoint)
13
14MEMORY {
15    RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE
16}
17
18SECTIONS {
19    . = BL32_BASE;
20
21    ASSERT(. == ALIGN(PAGE_SIZE),
22        "BL32_BASE address is not aligned on a page boundary.")
23
24#if SEPARATE_CODE_AND_RODATA
25    .text . : {
26        __TEXT_START__ = .;
27
28        *tsp_entrypoint.o(.text*)
29        *(.text*)
30        *(.vectors)
31
32        . = ALIGN(PAGE_SIZE);
33
34        __TEXT_END__ = .;
35    } >RAM
36
37    .rodata . : {
38        __RODATA_START__ = .;
39
40        *(.rodata*)
41
42        RODATA_COMMON
43
44        . = ALIGN(PAGE_SIZE);
45
46        __RODATA_END__ = .;
47    } >RAM
48#else /* SEPARATE_CODE_AND_RODATA */
49    .ro . : {
50        __RO_START__ = .;
51
52        *tsp_entrypoint.o(.text*)
53        *(.text*)
54        *(.rodata*)
55
56        RODATA_COMMON
57
58        *(.vectors)
59
60        __RO_END_UNALIGNED__ = .;
61
62        /*
63         * Memory page(s) mapped to this section will be marked as read-only,
64         * executable. No RW data from the next section must creep in. Ensure
65         * that the rest of the current memory page is unused.
66         */
67        . = ALIGN(PAGE_SIZE);
68
69        __RO_END__ = .;
70    } >RAM
71#endif /* SEPARATE_CODE_AND_RODATA */
72
73    __RW_START__ = .;
74
75    DATA_SECTION >RAM
76    RELA_SECTION >RAM
77
78#ifdef TSP_PROGBITS_LIMIT
79    ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.")
80#endif /* TSP_PROGBITS_LIMIT */
81
82    STACK_SECTION >RAM
83    BSS_SECTION >RAM
84    XLAT_TABLE_SECTION >RAM
85
86#if USE_COHERENT_MEM
87    /*
88     * The base address of the coherent memory section must be page-aligned to
89     * guarantee that the coherent data are stored on their own pages and are
90     * not mixed with normal data. This is required to set up the correct memory
91     * attributes for the coherent data page tables.
92     */
93    .coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
94        __COHERENT_RAM_START__ = .;
95        *(.tzfw_coherent_mem)
96        __COHERENT_RAM_END_UNALIGNED__ = .;
97
98        /*
99         * Memory page(s) mapped to this section will be marked as device
100         * memory. No other unexpected data must creep in. Ensure that the rest
101         * of the current memory page is unused.
102         */
103        . = ALIGN(PAGE_SIZE);
104
105        __COHERENT_RAM_END__ = .;
106    } >RAM
107#endif /* USE_COHERENT_MEM */
108
109    __RW_END__ = .;
110    __BL32_END__ = .;
111
112    /DISCARD/ : {
113        *(.dynsym .dynstr .hash .gnu.hash)
114    }
115
116    __BSS_SIZE__ = SIZEOF(.bss);
117
118#if USE_COHERENT_MEM
119    __COHERENT_RAM_UNALIGNED_SIZE__ =
120        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
121#endif /* USE_COHERENT_MEM */
122
123    ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.")
124}
125