xref: /rk3399_ARM-atf/bl32/tsp/tsp.ld.S (revision 51faada71a219a8b94cd8d8e423f0f22e9da4d8f) 
1/*
2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <platform_def.h>
32
33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
34OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
35ENTRY(tsp_entrypoint)
36
37
38MEMORY {
39    RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE
40}
41
42
43SECTIONS
44{
45    . = BL32_BASE;
46    ASSERT(. == ALIGN(4096),
47           "BL32_BASE address is not aligned on a page boundary.")
48
49#if SEPARATE_CODE_AND_RODATA
50    .text . : {
51        __TEXT_START__ = .;
52        *tsp_entrypoint.o(.text*)
53        *(.text*)
54        *(.vectors)
55        . = NEXT(4096);
56        __TEXT_END__ = .;
57    } >RAM
58
59    .rodata . : {
60        __RODATA_START__ = .;
61        *(.rodata*)
62        . = NEXT(4096);
63        __RODATA_END__ = .;
64    } >RAM
65#else
66    ro . : {
67        __RO_START__ = .;
68        *tsp_entrypoint.o(.text*)
69        *(.text*)
70        *(.rodata*)
71        *(.vectors)
72        __RO_END_UNALIGNED__ = .;
73        /*
74         * Memory page(s) mapped to this section will be marked as
75         * read-only, executable.  No RW data from the next section must
76         * creep in.  Ensure the rest of the current memory page is unused.
77         */
78        . = NEXT(4096);
79        __RO_END__ = .;
80    } >RAM
81#endif
82
83    /*
84     * Define a linker symbol to mark start of the RW memory area for this
85     * image.
86     */
87    __RW_START__ = . ;
88
89    .data . : {
90        __DATA_START__ = .;
91        *(.data*)
92        __DATA_END__ = .;
93    } >RAM
94
95#ifdef TSP_PROGBITS_LIMIT
96    ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.")
97#endif
98
99    stacks (NOLOAD) : {
100        __STACKS_START__ = .;
101        *(tzfw_normal_stacks)
102        __STACKS_END__ = .;
103    } >RAM
104
105    /*
106     * The .bss section gets initialised to 0 at runtime.
107     * Its base address should be 16-byte aligned for better performance of the
108     * zero-initialization code.
109     */
110    .bss : ALIGN(16) {
111        __BSS_START__ = .;
112        *(SORT_BY_ALIGNMENT(.bss*))
113        *(COMMON)
114        __BSS_END__ = .;
115    } >RAM
116
117    /*
118     * The xlat_table section is for full, aligned page tables (4K).
119     * Removing them from .bss avoids forcing 4K alignment on
120     * the .bss section and eliminates the unecessary zero init
121     */
122    xlat_table (NOLOAD) : {
123        *(xlat_table)
124    } >RAM
125
126#if USE_COHERENT_MEM
127    /*
128     * The base address of the coherent memory section must be page-aligned (4K)
129     * to guarantee that the coherent data are stored on their own pages and
130     * are not mixed with normal data.  This is required to set up the correct
131     * memory attributes for the coherent data page tables.
132     */
133    coherent_ram (NOLOAD) : ALIGN(4096) {
134        __COHERENT_RAM_START__ = .;
135        *(tzfw_coherent_mem)
136        __COHERENT_RAM_END_UNALIGNED__ = .;
137        /*
138         * Memory page(s) mapped to this section will be marked
139         * as device memory.  No other unexpected data must creep in.
140         * Ensure the rest of the current memory page is unused.
141         */
142        . = NEXT(4096);
143        __COHERENT_RAM_END__ = .;
144    } >RAM
145#endif
146
147    /*
148     * Define a linker symbol to mark the end of the RW memory area for this
149     * image.
150     */
151    __RW_END__ = .;
152    __BL32_END__ = .;
153
154    __BSS_SIZE__ = SIZEOF(.bss);
155#if USE_COHERENT_MEM
156    __COHERENT_RAM_UNALIGNED_SIZE__ =
157        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
158#endif
159
160    ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.")
161}
162