xref: /rk3399_ARM-atf/bl32/tsp/tsp.ld.S (revision 3105f7ba9a3a9f6f0e78761e8bdd4da621254730) 
1/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <platform_def.h>
32
33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
34OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
35ENTRY(tsp_entrypoint)
36
37
38MEMORY {
39    RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE
40}
41
42
43SECTIONS
44{
45    . = BL32_BASE;
46    ASSERT(. == ALIGN(4096),
47           "BL32_BASE address is not aligned on a page boundary.")
48
49    ro . : {
50        __RO_START__ = .;
51        *tsp_entrypoint.o(.text*)
52        *(.text*)
53        *(.rodata*)
54        *(.vectors)
55        __RO_END_UNALIGNED__ = .;
56        /*
57         * Memory page(s) mapped to this section will be marked as
58         * read-only, executable.  No RW data from the next section must
59         * creep in.  Ensure the rest of the current memory page is unused.
60         */
61        . = NEXT(4096);
62        __RO_END__ = .;
63    } >RAM
64
65    /*
66     * Define a linker symbol to mark start of the RW memory area for this
67     * image.
68     */
69    __RW_START__ = . ;
70
71    .data . : {
72        __DATA_START__ = .;
73        *(.data*)
74        __DATA_END__ = .;
75    } >RAM
76
77#ifdef TSP_PROGBITS_LIMIT
78    ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.")
79#endif
80
81    stacks (NOLOAD) : {
82        __STACKS_START__ = .;
83        *(tzfw_normal_stacks)
84        __STACKS_END__ = .;
85    } >RAM
86
87    /*
88     * The .bss section gets initialised to 0 at runtime.
89     * Its base address must be 16-byte aligned.
90     */
91    .bss : ALIGN(16) {
92        __BSS_START__ = .;
93        *(SORT_BY_ALIGNMENT(.bss*))
94        *(COMMON)
95        __BSS_END__ = .;
96    } >RAM
97
98    /*
99     * The xlat_table section is for full, aligned page tables (4K).
100     * Removing them from .bss avoids forcing 4K alignment on
101     * the .bss section and eliminates the unecessary zero init
102     */
103    xlat_table (NOLOAD) : {
104        *(xlat_table)
105    } >RAM
106
107#if USE_COHERENT_MEM
108    /*
109     * The base address of the coherent memory section must be page-aligned (4K)
110     * to guarantee that the coherent data are stored on their own pages and
111     * are not mixed with normal data.  This is required to set up the correct
112     * memory attributes for the coherent data page tables.
113     */
114    coherent_ram (NOLOAD) : ALIGN(4096) {
115        __COHERENT_RAM_START__ = .;
116        *(tzfw_coherent_mem)
117        __COHERENT_RAM_END_UNALIGNED__ = .;
118        /*
119         * Memory page(s) mapped to this section will be marked
120         * as device memory.  No other unexpected data must creep in.
121         * Ensure the rest of the current memory page is unused.
122         */
123        . = NEXT(4096);
124        __COHERENT_RAM_END__ = .;
125    } >RAM
126#endif
127
128    /*
129     * Define a linker symbol to mark the end of the RW memory area for this
130     * image.
131     */
132    __RW_END__ = .;
133    __BL32_END__ = .;
134
135    __BSS_SIZE__ = SIZEOF(.bss);
136#if USE_COHERENT_MEM
137    __COHERENT_RAM_UNALIGNED_SIZE__ =
138        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
139#endif
140
141    ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.")
142}
143