xref: /rk3399_ARM-atf/bl32/tsp/tsp.ld.S (revision 27cd1a4762c50eb461f74c7c43eee17b7bdde024) 
1/*
2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/bl_common.ld.h>
8#include <lib/xlat_tables/xlat_tables_defs.h>
9
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(tsp_entrypoint)
13
14
15MEMORY {
16    RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE
17}
18
19
20SECTIONS
21{
22    . = BL32_BASE;
23    ASSERT(. == ALIGN(PAGE_SIZE),
24           "BL32_BASE address is not aligned on a page boundary.")
25
26#if SEPARATE_CODE_AND_RODATA
27    .text . : {
28        __TEXT_START__ = .;
29        *tsp_entrypoint.o(.text*)
30        *(.text*)
31        *(.vectors)
32        . = ALIGN(PAGE_SIZE);
33        __TEXT_END__ = .;
34    } >RAM
35
36    .rodata . : {
37        __RODATA_START__ = .;
38        *(.rodata*)
39
40	RODATA_COMMON
41
42        . = ALIGN(PAGE_SIZE);
43        __RODATA_END__ = .;
44    } >RAM
45#else
46    ro . : {
47        __RO_START__ = .;
48        *tsp_entrypoint.o(.text*)
49        *(.text*)
50        *(.rodata*)
51
52	RODATA_COMMON
53
54        *(.vectors)
55
56        __RO_END_UNALIGNED__ = .;
57        /*
58         * Memory page(s) mapped to this section will be marked as
59         * read-only, executable.  No RW data from the next section must
60         * creep in.  Ensure the rest of the current memory page is unused.
61         */
62        . = ALIGN(PAGE_SIZE);
63        __RO_END__ = .;
64    } >RAM
65#endif
66
67    /*
68     * Define a linker symbol to mark start of the RW memory area for this
69     * image.
70     */
71    __RW_START__ = . ;
72
73    DATA_SECTION >RAM
74
75    /*
76     * .rela.dyn needs to come after .data for the read-elf utility to parse
77     * this section correctly. Ensure 8-byte alignment so that the fields of
78     * RELA data structure are aligned.
79     */
80    . = ALIGN(8);
81    __RELA_START__ = .;
82    .rela.dyn . : {
83    } >RAM
84    __RELA_END__ = .;
85
86#ifdef TSP_PROGBITS_LIMIT
87    ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.")
88#endif
89
90    STACK_SECTION >RAM
91    BSS_SECTION >RAM
92    XLAT_TABLE_SECTION >RAM
93
94#if USE_COHERENT_MEM
95    /*
96     * The base address of the coherent memory section must be page-aligned (4K)
97     * to guarantee that the coherent data are stored on their own pages and
98     * are not mixed with normal data.  This is required to set up the correct
99     * memory attributes for the coherent data page tables.
100     */
101    coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
102        __COHERENT_RAM_START__ = .;
103        *(tzfw_coherent_mem)
104        __COHERENT_RAM_END_UNALIGNED__ = .;
105        /*
106         * Memory page(s) mapped to this section will be marked
107         * as device memory.  No other unexpected data must creep in.
108         * Ensure the rest of the current memory page is unused.
109         */
110        . = ALIGN(PAGE_SIZE);
111        __COHERENT_RAM_END__ = .;
112    } >RAM
113#endif
114
115    /*
116     * Define a linker symbol to mark the end of the RW memory area for this
117     * image.
118     */
119    __RW_END__ = .;
120    __BL32_END__ = .;
121
122    /DISCARD/ : {
123        *(.dynsym .dynstr .hash .gnu.hash)
124    }
125
126    __BSS_SIZE__ = SIZEOF(.bss);
127#if USE_COHERENT_MEM
128    __COHERENT_RAM_UNALIGNED_SIZE__ =
129        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
130#endif
131
132    ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.")
133}
134