xref: /rk3399_ARM-atf/bl32/tsp/tsp.ld.S (revision 0e14a7fbeb3014e719302c9b7f6a24c4030dfaf0) 
1/*
2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <platform_def.h>
8
9OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
10OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
11ENTRY(tsp_entrypoint)
12
13
14MEMORY {
15    RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE
16}
17
18
19SECTIONS
20{
21    . = BL32_BASE;
22    ASSERT(. == ALIGN(4096),
23           "BL32_BASE address is not aligned on a page boundary.")
24
25#if SEPARATE_CODE_AND_RODATA
26    .text . : {
27        __TEXT_START__ = .;
28        *tsp_entrypoint.o(.text*)
29        *(.text*)
30        *(.vectors)
31        . = NEXT(4096);
32        __TEXT_END__ = .;
33    } >RAM
34
35    .rodata . : {
36        __RODATA_START__ = .;
37        *(.rodata*)
38        . = NEXT(4096);
39        __RODATA_END__ = .;
40    } >RAM
41#else
42    ro . : {
43        __RO_START__ = .;
44        *tsp_entrypoint.o(.text*)
45        *(.text*)
46        *(.rodata*)
47        *(.vectors)
48        __RO_END_UNALIGNED__ = .;
49        /*
50         * Memory page(s) mapped to this section will be marked as
51         * read-only, executable.  No RW data from the next section must
52         * creep in.  Ensure the rest of the current memory page is unused.
53         */
54        . = NEXT(4096);
55        __RO_END__ = .;
56    } >RAM
57#endif
58
59    /*
60     * Define a linker symbol to mark start of the RW memory area for this
61     * image.
62     */
63    __RW_START__ = . ;
64
65    .data . : {
66        __DATA_START__ = .;
67        *(.data*)
68        __DATA_END__ = .;
69    } >RAM
70
71#ifdef TSP_PROGBITS_LIMIT
72    ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.")
73#endif
74
75    stacks (NOLOAD) : {
76        __STACKS_START__ = .;
77        *(tzfw_normal_stacks)
78        __STACKS_END__ = .;
79    } >RAM
80
81    /*
82     * The .bss section gets initialised to 0 at runtime.
83     * Its base address should be 16-byte aligned for better performance of the
84     * zero-initialization code.
85     */
86    .bss : ALIGN(16) {
87        __BSS_START__ = .;
88        *(SORT_BY_ALIGNMENT(.bss*))
89        *(COMMON)
90        __BSS_END__ = .;
91    } >RAM
92
93    /*
94     * The xlat_table section is for full, aligned page tables (4K).
95     * Removing them from .bss avoids forcing 4K alignment on
96     * the .bss section and eliminates the unecessary zero init
97     */
98    xlat_table (NOLOAD) : {
99        *(xlat_table)
100    } >RAM
101
102#if USE_COHERENT_MEM
103    /*
104     * The base address of the coherent memory section must be page-aligned (4K)
105     * to guarantee that the coherent data are stored on their own pages and
106     * are not mixed with normal data.  This is required to set up the correct
107     * memory attributes for the coherent data page tables.
108     */
109    coherent_ram (NOLOAD) : ALIGN(4096) {
110        __COHERENT_RAM_START__ = .;
111        *(tzfw_coherent_mem)
112        __COHERENT_RAM_END_UNALIGNED__ = .;
113        /*
114         * Memory page(s) mapped to this section will be marked
115         * as device memory.  No other unexpected data must creep in.
116         * Ensure the rest of the current memory page is unused.
117         */
118        . = NEXT(4096);
119        __COHERENT_RAM_END__ = .;
120    } >RAM
121#endif
122
123    /*
124     * Define a linker symbol to mark the end of the RW memory area for this
125     * image.
126     */
127    __RW_END__ = .;
128    __BL32_END__ = .;
129
130    __BSS_SIZE__ = SIZEOF(.bss);
131#if USE_COHERENT_MEM
132    __COHERENT_RAM_UNALIGNED_SIZE__ =
133        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
134#endif
135
136    ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.")
137}
138