1/* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <bl_common.h> 32#include <arch.h> 33#include <tsp.h> 34#include <asm_macros.S> 35 36 37 /* ---------------------------------------------------- 38 * The caller-saved registers x0-x18 and LR are saved 39 * here. 40 * ---------------------------------------------------- 41 */ 42 43#define SCRATCH_REG_SIZE #(20 * 8) 44 45 .macro save_caller_regs_and_lr 46 sub sp, sp, SCRATCH_REG_SIZE 47 stp x0, x1, [sp] 48 stp x2, x3, [sp, #0x10] 49 stp x4, x5, [sp, #0x20] 50 stp x6, x7, [sp, #0x30] 51 stp x8, x9, [sp, #0x40] 52 stp x10, x11, [sp, #0x50] 53 stp x12, x13, [sp, #0x60] 54 stp x14, x15, [sp, #0x70] 55 stp x16, x17, [sp, #0x80] 56 stp x18, x30, [sp, #0x90] 57 .endm 58 59 .macro restore_caller_regs_and_lr 60 ldp x0, x1, [sp] 61 ldp x2, x3, [sp, #0x10] 62 ldp x4, x5, [sp, #0x20] 63 ldp x6, x7, [sp, #0x30] 64 ldp x8, x9, [sp, #0x40] 65 ldp x10, x11, [sp, #0x50] 66 ldp x12, x13, [sp, #0x60] 67 ldp x14, x15, [sp, #0x70] 68 ldp x16, x17, [sp, #0x80] 69 ldp x18, x30, [sp, #0x90] 70 add sp, sp, SCRATCH_REG_SIZE 71 .endm 72 73 /* ---------------------------------------------------- 74 * Common TSP interrupt handling routine 75 * ---------------------------------------------------- 76 */ 77 .macro handle_tsp_interrupt label 78 /* Enable the SError interrupt */ 79 msr daifclr, #DAIF_ABT_BIT 80 81 save_caller_regs_and_lr 82 bl tsp_common_int_handler 83 cbz x0, interrupt_exit_\label 84 85 /* 86 * This interrupt was not targetted to S-EL1 so send it to 87 * the monitor and wait for execution to resume. 88 */ 89 smc #0 90interrupt_exit_\label: 91 restore_caller_regs_and_lr 92 eret 93 .endm 94 95 .globl tsp_exceptions 96 97 /* ----------------------------------------------------- 98 * TSP exception handlers. 99 * ----------------------------------------------------- 100 */ 101 .section .vectors, "ax"; .align 11 102 103 .align 7 104tsp_exceptions: 105 /* ----------------------------------------------------- 106 * Current EL with _sp_el0 : 0x0 - 0x180. No exceptions 107 * are expected and treated as irrecoverable errors. 108 * ----------------------------------------------------- 109 */ 110sync_exception_sp_el0: 111 bl plat_panic_handler 112 check_vector_size sync_exception_sp_el0 113 114 .align 7 115 116irq_sp_el0: 117 bl plat_panic_handler 118 check_vector_size irq_sp_el0 119 120 .align 7 121fiq_sp_el0: 122 bl plat_panic_handler 123 check_vector_size fiq_sp_el0 124 125 .align 7 126serror_sp_el0: 127 bl plat_panic_handler 128 check_vector_size serror_sp_el0 129 130 131 /* ----------------------------------------------------- 132 * Current EL with SPx: 0x200 - 0x380. Only IRQs/FIQs 133 * are expected and handled 134 * ----------------------------------------------------- 135 */ 136 .align 7 137sync_exception_sp_elx: 138 bl plat_panic_handler 139 check_vector_size sync_exception_sp_elx 140 141 .align 7 142irq_sp_elx: 143 handle_tsp_interrupt irq_sp_elx 144 check_vector_size irq_sp_elx 145 146 .align 7 147fiq_sp_elx: 148 handle_tsp_interrupt fiq_sp_elx 149 check_vector_size fiq_sp_elx 150 151 .align 7 152serror_sp_elx: 153 bl plat_panic_handler 154 check_vector_size serror_sp_elx 155 156 157 /* ----------------------------------------------------- 158 * Lower EL using AArch64 : 0x400 - 0x580. No exceptions 159 * are handled since TSP does not implement a lower EL 160 * ----------------------------------------------------- 161 */ 162 .align 7 163sync_exception_aarch64: 164 bl plat_panic_handler 165 check_vector_size sync_exception_aarch64 166 167 .align 7 168irq_aarch64: 169 bl plat_panic_handler 170 check_vector_size irq_aarch64 171 172 .align 7 173fiq_aarch64: 174 bl plat_panic_handler 175 check_vector_size fiq_aarch64 176 177 .align 7 178serror_aarch64: 179 bl plat_panic_handler 180 check_vector_size serror_aarch64 181 182 183 /* ----------------------------------------------------- 184 * Lower EL using AArch32 : 0x600 - 0x780. No exceptions 185 * handled since the TSP does not implement a lower EL. 186 * ----------------------------------------------------- 187 */ 188 .align 7 189sync_exception_aarch32: 190 bl plat_panic_handler 191 check_vector_size sync_exception_aarch32 192 193 .align 7 194irq_aarch32: 195 bl plat_panic_handler 196 check_vector_size irq_aarch32 197 198 .align 7 199fiq_aarch32: 200 bl plat_panic_handler 201 check_vector_size fiq_aarch32 202 203 .align 7 204serror_aarch32: 205 bl plat_panic_handler 206 check_vector_size serror_aarch32 207 .align 7 208