157356e90SAchin Gupta/* 21c3ea103SAntonio Nino Diaz * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 357356e90SAchin Gupta * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 557356e90SAchin Gupta */ 657356e90SAchin Gupta 757356e90SAchin Gupta#include <arch.h> 857356e90SAchin Gupta#include <asm_macros.S> 9e0ae9fabSSandrine Bailleux#include <bl_common.h> 10e0ae9fabSSandrine Bailleux#include <tsp.h> 1157356e90SAchin Gupta 1257356e90SAchin Gupta 1357356e90SAchin Gupta /* ---------------------------------------------------- 1457356e90SAchin Gupta * The caller-saved registers x0-x18 and LR are saved 1557356e90SAchin Gupta * here. 1657356e90SAchin Gupta * ---------------------------------------------------- 1757356e90SAchin Gupta */ 1857356e90SAchin Gupta 1957356e90SAchin Gupta#define SCRATCH_REG_SIZE #(20 * 8) 2057356e90SAchin Gupta 2157356e90SAchin Gupta .macro save_caller_regs_and_lr 2257356e90SAchin Gupta sub sp, sp, SCRATCH_REG_SIZE 2357356e90SAchin Gupta stp x0, x1, [sp] 2457356e90SAchin Gupta stp x2, x3, [sp, #0x10] 2557356e90SAchin Gupta stp x4, x5, [sp, #0x20] 2657356e90SAchin Gupta stp x6, x7, [sp, #0x30] 2757356e90SAchin Gupta stp x8, x9, [sp, #0x40] 2857356e90SAchin Gupta stp x10, x11, [sp, #0x50] 2957356e90SAchin Gupta stp x12, x13, [sp, #0x60] 3057356e90SAchin Gupta stp x14, x15, [sp, #0x70] 3157356e90SAchin Gupta stp x16, x17, [sp, #0x80] 3257356e90SAchin Gupta stp x18, x30, [sp, #0x90] 3357356e90SAchin Gupta .endm 3457356e90SAchin Gupta 3557356e90SAchin Gupta .macro restore_caller_regs_and_lr 3657356e90SAchin Gupta ldp x0, x1, [sp] 3757356e90SAchin Gupta ldp x2, x3, [sp, #0x10] 3857356e90SAchin Gupta ldp x4, x5, [sp, #0x20] 3957356e90SAchin Gupta ldp x6, x7, [sp, #0x30] 4057356e90SAchin Gupta ldp x8, x9, [sp, #0x40] 4157356e90SAchin Gupta ldp x10, x11, [sp, #0x50] 4257356e90SAchin Gupta ldp x12, x13, [sp, #0x60] 4357356e90SAchin Gupta ldp x14, x15, [sp, #0x70] 4457356e90SAchin Gupta ldp x16, x17, [sp, #0x80] 4557356e90SAchin Gupta ldp x18, x30, [sp, #0x90] 4657356e90SAchin Gupta add sp, sp, SCRATCH_REG_SIZE 4757356e90SAchin Gupta .endm 4857356e90SAchin Gupta 4902446137SSoby Mathew /* ---------------------------------------------------- 5002446137SSoby Mathew * Common TSP interrupt handling routine 5102446137SSoby Mathew * ---------------------------------------------------- 5202446137SSoby Mathew */ 5302446137SSoby Mathew .macro handle_tsp_interrupt label 5402446137SSoby Mathew /* Enable the SError interrupt */ 5502446137SSoby Mathew msr daifclr, #DAIF_ABT_BIT 5602446137SSoby Mathew 5702446137SSoby Mathew save_caller_regs_and_lr 5802446137SSoby Mathew bl tsp_common_int_handler 5902446137SSoby Mathew cbz x0, interrupt_exit_\label 6002446137SSoby Mathew 6102446137SSoby Mathew /* 6202446137SSoby Mathew * This interrupt was not targetted to S-EL1 so send it to 6302446137SSoby Mathew * the monitor and wait for execution to resume. 6402446137SSoby Mathew */ 6502446137SSoby Mathew smc #0 6602446137SSoby Mathewinterrupt_exit_\label: 6702446137SSoby Mathew restore_caller_regs_and_lr 6802446137SSoby Mathew eret 6902446137SSoby Mathew .endm 7002446137SSoby Mathew 7157356e90SAchin Gupta .globl tsp_exceptions 7257356e90SAchin Gupta 7357356e90SAchin Gupta /* ----------------------------------------------------- 7457356e90SAchin Gupta * TSP exception handlers. 7557356e90SAchin Gupta * ----------------------------------------------------- 7657356e90SAchin Gupta */ 77e0ae9fabSSandrine Bailleuxvector_base tsp_exceptions 7857356e90SAchin Gupta /* ----------------------------------------------------- 79e0ae9fabSSandrine Bailleux * Current EL with _sp_el0 : 0x0 - 0x200. No exceptions 8057356e90SAchin Gupta * are expected and treated as irrecoverable errors. 8157356e90SAchin Gupta * ----------------------------------------------------- 8257356e90SAchin Gupta */ 83e0ae9fabSSandrine Bailleuxvector_entry sync_exception_sp_el0 84*4d91838bSJulius Werner b plat_panic_handler 8557356e90SAchin Gupta check_vector_size sync_exception_sp_el0 8657356e90SAchin Gupta 87e0ae9fabSSandrine Bailleuxvector_entry irq_sp_el0 88*4d91838bSJulius Werner b plat_panic_handler 8957356e90SAchin Gupta check_vector_size irq_sp_el0 9057356e90SAchin Gupta 91e0ae9fabSSandrine Bailleuxvector_entry fiq_sp_el0 92*4d91838bSJulius Werner b plat_panic_handler 9357356e90SAchin Gupta check_vector_size fiq_sp_el0 9457356e90SAchin Gupta 95e0ae9fabSSandrine Bailleuxvector_entry serror_sp_el0 96*4d91838bSJulius Werner b plat_panic_handler 9757356e90SAchin Gupta check_vector_size serror_sp_el0 9857356e90SAchin Gupta 9957356e90SAchin Gupta 10057356e90SAchin Gupta /* ----------------------------------------------------- 101e0ae9fabSSandrine Bailleux * Current EL with SPx: 0x200 - 0x400. Only IRQs/FIQs 10257356e90SAchin Gupta * are expected and handled 10357356e90SAchin Gupta * ----------------------------------------------------- 10457356e90SAchin Gupta */ 105e0ae9fabSSandrine Bailleuxvector_entry sync_exception_sp_elx 106*4d91838bSJulius Werner b plat_panic_handler 10757356e90SAchin Gupta check_vector_size sync_exception_sp_elx 10857356e90SAchin Gupta 109e0ae9fabSSandrine Bailleuxvector_entry irq_sp_elx 11002446137SSoby Mathew handle_tsp_interrupt irq_sp_elx 11157356e90SAchin Gupta check_vector_size irq_sp_elx 11257356e90SAchin Gupta 113e0ae9fabSSandrine Bailleuxvector_entry fiq_sp_elx 11402446137SSoby Mathew handle_tsp_interrupt fiq_sp_elx 11557356e90SAchin Gupta check_vector_size fiq_sp_elx 11657356e90SAchin Gupta 117e0ae9fabSSandrine Bailleuxvector_entry serror_sp_elx 118*4d91838bSJulius Werner b plat_panic_handler 11957356e90SAchin Gupta check_vector_size serror_sp_elx 12057356e90SAchin Gupta 12157356e90SAchin Gupta 12257356e90SAchin Gupta /* ----------------------------------------------------- 123e0ae9fabSSandrine Bailleux * Lower EL using AArch64 : 0x400 - 0x600. No exceptions 12457356e90SAchin Gupta * are handled since TSP does not implement a lower EL 12557356e90SAchin Gupta * ----------------------------------------------------- 12657356e90SAchin Gupta */ 127e0ae9fabSSandrine Bailleuxvector_entry sync_exception_aarch64 128*4d91838bSJulius Werner b plat_panic_handler 12957356e90SAchin Gupta check_vector_size sync_exception_aarch64 13057356e90SAchin Gupta 131e0ae9fabSSandrine Bailleuxvector_entry irq_aarch64 132*4d91838bSJulius Werner b plat_panic_handler 13357356e90SAchin Gupta check_vector_size irq_aarch64 13457356e90SAchin Gupta 135e0ae9fabSSandrine Bailleuxvector_entry fiq_aarch64 136*4d91838bSJulius Werner b plat_panic_handler 13757356e90SAchin Gupta check_vector_size fiq_aarch64 13857356e90SAchin Gupta 139e0ae9fabSSandrine Bailleuxvector_entry serror_aarch64 140*4d91838bSJulius Werner b plat_panic_handler 14157356e90SAchin Gupta check_vector_size serror_aarch64 14257356e90SAchin Gupta 14357356e90SAchin Gupta 14457356e90SAchin Gupta /* ----------------------------------------------------- 145e0ae9fabSSandrine Bailleux * Lower EL using AArch32 : 0x600 - 0x800. No exceptions 14657356e90SAchin Gupta * handled since the TSP does not implement a lower EL. 14757356e90SAchin Gupta * ----------------------------------------------------- 14857356e90SAchin Gupta */ 149e0ae9fabSSandrine Bailleuxvector_entry sync_exception_aarch32 150*4d91838bSJulius Werner b plat_panic_handler 15157356e90SAchin Gupta check_vector_size sync_exception_aarch32 15257356e90SAchin Gupta 153e0ae9fabSSandrine Bailleuxvector_entry irq_aarch32 154*4d91838bSJulius Werner b plat_panic_handler 15557356e90SAchin Gupta check_vector_size irq_aarch32 15657356e90SAchin Gupta 157e0ae9fabSSandrine Bailleuxvector_entry fiq_aarch32 158*4d91838bSJulius Werner b plat_panic_handler 15957356e90SAchin Gupta check_vector_size fiq_aarch32 16057356e90SAchin Gupta 161e0ae9fabSSandrine Bailleuxvector_entry serror_aarch32 162*4d91838bSJulius Werner b plat_panic_handler 16357356e90SAchin Gupta check_vector_size serror_aarch32 164