157356e90SAchin Gupta/* 21c3ea103SAntonio Nino Diaz * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 357356e90SAchin Gupta * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 557356e90SAchin Gupta */ 657356e90SAchin Gupta 757356e90SAchin Gupta#include <arch.h> 857356e90SAchin Gupta#include <asm_macros.S> 9*09d40e0eSAntonio Nino Diaz#include <bl32/tsp/tsp.h> 10*09d40e0eSAntonio Nino Diaz#include <common/bl_common.h> 1157356e90SAchin Gupta 1257356e90SAchin Gupta /* ---------------------------------------------------- 1357356e90SAchin Gupta * The caller-saved registers x0-x18 and LR are saved 1457356e90SAchin Gupta * here. 1557356e90SAchin Gupta * ---------------------------------------------------- 1657356e90SAchin Gupta */ 1757356e90SAchin Gupta 1857356e90SAchin Gupta#define SCRATCH_REG_SIZE #(20 * 8) 1957356e90SAchin Gupta 2057356e90SAchin Gupta .macro save_caller_regs_and_lr 2157356e90SAchin Gupta sub sp, sp, SCRATCH_REG_SIZE 2257356e90SAchin Gupta stp x0, x1, [sp] 2357356e90SAchin Gupta stp x2, x3, [sp, #0x10] 2457356e90SAchin Gupta stp x4, x5, [sp, #0x20] 2557356e90SAchin Gupta stp x6, x7, [sp, #0x30] 2657356e90SAchin Gupta stp x8, x9, [sp, #0x40] 2757356e90SAchin Gupta stp x10, x11, [sp, #0x50] 2857356e90SAchin Gupta stp x12, x13, [sp, #0x60] 2957356e90SAchin Gupta stp x14, x15, [sp, #0x70] 3057356e90SAchin Gupta stp x16, x17, [sp, #0x80] 3157356e90SAchin Gupta stp x18, x30, [sp, #0x90] 3257356e90SAchin Gupta .endm 3357356e90SAchin Gupta 3457356e90SAchin Gupta .macro restore_caller_regs_and_lr 3557356e90SAchin Gupta ldp x0, x1, [sp] 3657356e90SAchin Gupta ldp x2, x3, [sp, #0x10] 3757356e90SAchin Gupta ldp x4, x5, [sp, #0x20] 3857356e90SAchin Gupta ldp x6, x7, [sp, #0x30] 3957356e90SAchin Gupta ldp x8, x9, [sp, #0x40] 4057356e90SAchin Gupta ldp x10, x11, [sp, #0x50] 4157356e90SAchin Gupta ldp x12, x13, [sp, #0x60] 4257356e90SAchin Gupta ldp x14, x15, [sp, #0x70] 4357356e90SAchin Gupta ldp x16, x17, [sp, #0x80] 4457356e90SAchin Gupta ldp x18, x30, [sp, #0x90] 4557356e90SAchin Gupta add sp, sp, SCRATCH_REG_SIZE 4657356e90SAchin Gupta .endm 4757356e90SAchin Gupta 4802446137SSoby Mathew /* ---------------------------------------------------- 4902446137SSoby Mathew * Common TSP interrupt handling routine 5002446137SSoby Mathew * ---------------------------------------------------- 5102446137SSoby Mathew */ 5202446137SSoby Mathew .macro handle_tsp_interrupt label 5302446137SSoby Mathew /* Enable the SError interrupt */ 5402446137SSoby Mathew msr daifclr, #DAIF_ABT_BIT 5502446137SSoby Mathew 5602446137SSoby Mathew save_caller_regs_and_lr 5702446137SSoby Mathew bl tsp_common_int_handler 5802446137SSoby Mathew cbz x0, interrupt_exit_\label 5902446137SSoby Mathew 6002446137SSoby Mathew /* 6102446137SSoby Mathew * This interrupt was not targetted to S-EL1 so send it to 6202446137SSoby Mathew * the monitor and wait for execution to resume. 6302446137SSoby Mathew */ 6402446137SSoby Mathew smc #0 6502446137SSoby Mathewinterrupt_exit_\label: 6602446137SSoby Mathew restore_caller_regs_and_lr 6702446137SSoby Mathew eret 6802446137SSoby Mathew .endm 6902446137SSoby Mathew 7057356e90SAchin Gupta .globl tsp_exceptions 7157356e90SAchin Gupta 7257356e90SAchin Gupta /* ----------------------------------------------------- 7357356e90SAchin Gupta * TSP exception handlers. 7457356e90SAchin Gupta * ----------------------------------------------------- 7557356e90SAchin Gupta */ 76e0ae9fabSSandrine Bailleuxvector_base tsp_exceptions 7757356e90SAchin Gupta /* ----------------------------------------------------- 78e0ae9fabSSandrine Bailleux * Current EL with _sp_el0 : 0x0 - 0x200. No exceptions 7957356e90SAchin Gupta * are expected and treated as irrecoverable errors. 8057356e90SAchin Gupta * ----------------------------------------------------- 8157356e90SAchin Gupta */ 82e0ae9fabSSandrine Bailleuxvector_entry sync_exception_sp_el0 834d91838bSJulius Werner b plat_panic_handler 84a9203edaSRoberto Vargasend_vector_entry sync_exception_sp_el0 8557356e90SAchin Gupta 86e0ae9fabSSandrine Bailleuxvector_entry irq_sp_el0 874d91838bSJulius Werner b plat_panic_handler 88a9203edaSRoberto Vargasend_vector_entry irq_sp_el0 8957356e90SAchin Gupta 90e0ae9fabSSandrine Bailleuxvector_entry fiq_sp_el0 914d91838bSJulius Werner b plat_panic_handler 92a9203edaSRoberto Vargasend_vector_entry fiq_sp_el0 9357356e90SAchin Gupta 94e0ae9fabSSandrine Bailleuxvector_entry serror_sp_el0 954d91838bSJulius Werner b plat_panic_handler 96a9203edaSRoberto Vargasend_vector_entry serror_sp_el0 9757356e90SAchin Gupta 9857356e90SAchin Gupta 9957356e90SAchin Gupta /* ----------------------------------------------------- 100e0ae9fabSSandrine Bailleux * Current EL with SPx: 0x200 - 0x400. Only IRQs/FIQs 10157356e90SAchin Gupta * are expected and handled 10257356e90SAchin Gupta * ----------------------------------------------------- 10357356e90SAchin Gupta */ 104e0ae9fabSSandrine Bailleuxvector_entry sync_exception_sp_elx 1054d91838bSJulius Werner b plat_panic_handler 106a9203edaSRoberto Vargasend_vector_entry sync_exception_sp_elx 10757356e90SAchin Gupta 108e0ae9fabSSandrine Bailleuxvector_entry irq_sp_elx 10902446137SSoby Mathew handle_tsp_interrupt irq_sp_elx 110a9203edaSRoberto Vargasend_vector_entry irq_sp_elx 11157356e90SAchin Gupta 112e0ae9fabSSandrine Bailleuxvector_entry fiq_sp_elx 11302446137SSoby Mathew handle_tsp_interrupt fiq_sp_elx 114a9203edaSRoberto Vargasend_vector_entry fiq_sp_elx 11557356e90SAchin Gupta 116e0ae9fabSSandrine Bailleuxvector_entry serror_sp_elx 1174d91838bSJulius Werner b plat_panic_handler 118a9203edaSRoberto Vargasend_vector_entry serror_sp_elx 11957356e90SAchin Gupta 12057356e90SAchin Gupta 12157356e90SAchin Gupta /* ----------------------------------------------------- 122e0ae9fabSSandrine Bailleux * Lower EL using AArch64 : 0x400 - 0x600. No exceptions 12357356e90SAchin Gupta * are handled since TSP does not implement a lower EL 12457356e90SAchin Gupta * ----------------------------------------------------- 12557356e90SAchin Gupta */ 126e0ae9fabSSandrine Bailleuxvector_entry sync_exception_aarch64 1274d91838bSJulius Werner b plat_panic_handler 128a9203edaSRoberto Vargasend_vector_entry sync_exception_aarch64 12957356e90SAchin Gupta 130e0ae9fabSSandrine Bailleuxvector_entry irq_aarch64 1314d91838bSJulius Werner b plat_panic_handler 132a9203edaSRoberto Vargasend_vector_entry irq_aarch64 13357356e90SAchin Gupta 134e0ae9fabSSandrine Bailleuxvector_entry fiq_aarch64 1354d91838bSJulius Werner b plat_panic_handler 136a9203edaSRoberto Vargasend_vector_entry fiq_aarch64 13757356e90SAchin Gupta 138e0ae9fabSSandrine Bailleuxvector_entry serror_aarch64 1394d91838bSJulius Werner b plat_panic_handler 140a9203edaSRoberto Vargasend_vector_entry serror_aarch64 14157356e90SAchin Gupta 14257356e90SAchin Gupta 14357356e90SAchin Gupta /* ----------------------------------------------------- 144e0ae9fabSSandrine Bailleux * Lower EL using AArch32 : 0x600 - 0x800. No exceptions 14557356e90SAchin Gupta * handled since the TSP does not implement a lower EL. 14657356e90SAchin Gupta * ----------------------------------------------------- 14757356e90SAchin Gupta */ 148e0ae9fabSSandrine Bailleuxvector_entry sync_exception_aarch32 1494d91838bSJulius Werner b plat_panic_handler 150a9203edaSRoberto Vargasend_vector_entry sync_exception_aarch32 15157356e90SAchin Gupta 152e0ae9fabSSandrine Bailleuxvector_entry irq_aarch32 1534d91838bSJulius Werner b plat_panic_handler 154a9203edaSRoberto Vargasend_vector_entry irq_aarch32 15557356e90SAchin Gupta 156e0ae9fabSSandrine Bailleuxvector_entry fiq_aarch32 1574d91838bSJulius Werner b plat_panic_handler 158a9203edaSRoberto Vargasend_vector_entry fiq_aarch32 15957356e90SAchin Gupta 160e0ae9fabSSandrine Bailleuxvector_entry serror_aarch32 1614d91838bSJulius Werner b plat_panic_handler 162a9203edaSRoberto Vargasend_vector_entry serror_aarch32 163