1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <tsp.h> 34 35 36 .globl tsp_entrypoint 37 .globl tsp_cpu_on_entry 38 .globl tsp_cpu_off_entry 39 .globl tsp_cpu_suspend_entry 40 .globl tsp_cpu_resume_entry 41 .globl tsp_fast_smc_entry 42 43 /* --------------------------------------------- 44 * Populate the params in x0-x7 from the pointer 45 * to the smc args structure in x0. 46 * --------------------------------------------- 47 */ 48 .macro restore_args_call_smc 49 ldp x6, x7, [x0, #TSP_ARG6] 50 ldp x4, x5, [x0, #TSP_ARG4] 51 ldp x2, x3, [x0, #TSP_ARG2] 52 ldp x0, x1, [x0, #TSP_ARG0] 53 smc #0 54 .endm 55 56 57func tsp_entrypoint 58 59 /* --------------------------------------------- 60 * The entrypoint is expected to be executed 61 * only by the primary cpu (at least for now). 62 * So, make sure no secondary has lost its way. 63 * --------------------------------------------- 64 */ 65 mrs x0, mpidr_el1 66 bl platform_is_primary_cpu 67 cbz x0, tsp_entrypoint_panic 68 69 /* --------------------------------------------- 70 * Set the exception vector to something sane. 71 * --------------------------------------------- 72 */ 73 adr x0, early_exceptions 74 msr vbar_el1, x0 75 76 /* --------------------------------------------- 77 * Enable the instruction cache. 78 * --------------------------------------------- 79 */ 80 mrs x0, sctlr_el1 81 orr x0, x0, #SCTLR_I_BIT 82 msr sctlr_el1, x0 83 isb 84 85 /* --------------------------------------------- 86 * Zero out NOBITS sections. There are 2 of them: 87 * - the .bss section; 88 * - the coherent memory section. 89 * --------------------------------------------- 90 */ 91 ldr x0, =__BSS_START__ 92 ldr x1, =__BSS_SIZE__ 93 bl zeromem16 94 95 ldr x0, =__COHERENT_RAM_START__ 96 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 97 bl zeromem16 98 99 /* -------------------------------------------- 100 * Give ourselves a small coherent stack to 101 * ease the pain of initializing the MMU 102 * -------------------------------------------- 103 */ 104 mrs x0, mpidr_el1 105 bl platform_set_coherent_stack 106 107 /* --------------------------------------------- 108 * Perform early platform setup & platform 109 * specific early arch. setup e.g. mmu setup 110 * --------------------------------------------- 111 */ 112 bl bl32_early_platform_setup 113 bl bl32_plat_arch_setup 114 115 /* --------------------------------------------- 116 * Give ourselves a stack allocated in Normal 117 * -IS-WBWA memory 118 * --------------------------------------------- 119 */ 120 mrs x0, mpidr_el1 121 bl platform_set_stack 122 123 /* --------------------------------------------- 124 * Jump to main function. 125 * --------------------------------------------- 126 */ 127 bl tsp_main 128 129 /* --------------------------------------------- 130 * Tell TSPD that we are done initialising 131 * --------------------------------------------- 132 */ 133 mov x1, x0 134 mov x0, #TSP_ENTRY_DONE 135 smc #0 136 137tsp_entrypoint_panic: 138 b tsp_entrypoint_panic 139 140 /*--------------------------------------------- 141 * This entrypoint is used by the TSPD when this 142 * cpu is to be turned off through a CPU_OFF 143 * psci call to ask the TSP to perform any 144 * bookeeping necessary. In the current 145 * implementation, the TSPD expects the TSP to 146 * re-initialise its state so nothing is done 147 * here except for acknowledging the request. 148 * --------------------------------------------- 149 */ 150func tsp_cpu_off_entry 151 bl tsp_cpu_off_main 152 restore_args_call_smc 153 154 /*--------------------------------------------- 155 * This entrypoint is used by the TSPD when this 156 * cpu is turned on using a CPU_ON psci call to 157 * ask the TSP to initialise itself i.e. setup 158 * the mmu, stacks etc. Minimal architectural 159 * state will be initialised by the TSPD when 160 * this function is entered i.e. Caches and MMU 161 * will be turned off, the execution state 162 * will be aarch64 and exceptions masked. 163 * --------------------------------------------- 164 */ 165func tsp_cpu_on_entry 166 /* --------------------------------------------- 167 * Set the exception vector to something sane. 168 * --------------------------------------------- 169 */ 170 adr x0, early_exceptions 171 msr vbar_el1, x0 172 173 /* --------------------------------------------- 174 * Enable the instruction cache. 175 * --------------------------------------------- 176 */ 177 mrs x0, sctlr_el1 178 orr x0, x0, #SCTLR_I_BIT 179 msr sctlr_el1, x0 180 isb 181 182 /* -------------------------------------------- 183 * Give ourselves a small coherent stack to 184 * ease the pain of initializing the MMU 185 * -------------------------------------------- 186 */ 187 mrs x0, mpidr_el1 188 bl platform_set_coherent_stack 189 190 /* --------------------------------------------- 191 * Initialise the MMU 192 * --------------------------------------------- 193 */ 194 bl enable_mmu_el1 195 196 /* --------------------------------------------- 197 * Give ourselves a stack allocated in Normal 198 * -IS-WBWA memory 199 * --------------------------------------------- 200 */ 201 mrs x0, mpidr_el1 202 bl platform_set_stack 203 204 /* --------------------------------------------- 205 * Enter C runtime to perform any remaining 206 * book keeping 207 * --------------------------------------------- 208 */ 209 bl tsp_cpu_on_main 210 restore_args_call_smc 211 212 /* Should never reach here */ 213tsp_cpu_on_entry_panic: 214 b tsp_cpu_on_entry_panic 215 216 /*--------------------------------------------- 217 * This entrypoint is used by the TSPD when this 218 * cpu is to be suspended through a CPU_SUSPEND 219 * psci call to ask the TSP to perform any 220 * bookeeping necessary. In the current 221 * implementation, the TSPD saves and restores 222 * the EL1 state. 223 * --------------------------------------------- 224 */ 225func tsp_cpu_suspend_entry 226 bl tsp_cpu_suspend_main 227 restore_args_call_smc 228 229 /*--------------------------------------------- 230 * This entrypoint is used by the TSPD when this 231 * cpu resumes execution after an earlier 232 * CPU_SUSPEND psci call to ask the TSP to 233 * restore its saved context. In the current 234 * implementation, the TSPD saves and restores 235 * EL1 state so nothing is done here apart from 236 * acknowledging the request. 237 * --------------------------------------------- 238 */ 239func tsp_cpu_resume_entry 240 bl tsp_cpu_resume_main 241 restore_args_call_smc 242tsp_cpu_resume_panic: 243 b tsp_cpu_resume_panic 244 245 /*--------------------------------------------- 246 * This entrypoint is used by the TSPD to ask 247 * the TSP to service a fast smc request. 248 * --------------------------------------------- 249 */ 250func tsp_fast_smc_entry 251 bl tsp_fast_smc_handler 252 restore_args_call_smc 253tsp_fast_smc_entry_panic: 254 b tsp_fast_smc_entry_panic 255 256