1/* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <bl32/tsp/tsp.h> 10#include <lib/xlat_tables/xlat_tables_defs.h> 11 12#include "../tsp_private.h" 13 14 15 .globl tsp_entrypoint 16 .globl tsp_vector_table 17 18 19 20 /* --------------------------------------------- 21 * Populate the params in x0-x7 from the pointer 22 * to the smc args structure in x0. 23 * --------------------------------------------- 24 */ 25 .macro restore_args_call_smc 26 ldp x6, x7, [x0, #TSP_ARG6] 27 ldp x4, x5, [x0, #TSP_ARG4] 28 ldp x2, x3, [x0, #TSP_ARG2] 29 ldp x0, x1, [x0, #TSP_ARG0] 30 smc #0 31 .endm 32 33 .macro save_eret_context reg1 reg2 34 mrs \reg1, elr_el1 35 mrs \reg2, spsr_el1 36 stp \reg1, \reg2, [sp, #-0x10]! 37 stp x30, x18, [sp, #-0x10]! 38 .endm 39 40 .macro restore_eret_context reg1 reg2 41 ldp x30, x18, [sp], #0x10 42 ldp \reg1, \reg2, [sp], #0x10 43 msr elr_el1, \reg1 44 msr spsr_el1, \reg2 45 .endm 46 47func tsp_entrypoint _align=3 48 49 /* --------------------------------------------- 50 * Set the exception vector to something sane. 51 * --------------------------------------------- 52 */ 53 adr x0, tsp_exceptions 54 msr vbar_el1, x0 55 isb 56 57 /* --------------------------------------------- 58 * Enable the SError interrupt now that the 59 * exception vectors have been setup. 60 * --------------------------------------------- 61 */ 62 msr daifclr, #DAIF_ABT_BIT 63 64 /* --------------------------------------------- 65 * Enable the instruction cache, stack pointer 66 * and data access alignment checks 67 * --------------------------------------------- 68 */ 69 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 70 mrs x0, sctlr_el1 71 orr x0, x0, x1 72 msr sctlr_el1, x0 73 isb 74 75 /* --------------------------------------------- 76 * Invalidate the RW memory used by the BL32 77 * image. This includes the data and NOBITS 78 * sections. This is done to safeguard against 79 * possible corruption of this memory by dirty 80 * cache lines in a system cache as a result of 81 * use by an earlier boot loader stage. 82 * --------------------------------------------- 83 */ 84 adr x0, __RW_START__ 85 adr x1, __RW_END__ 86 sub x1, x1, x0 87 bl inv_dcache_range 88 89 /* --------------------------------------------- 90 * Zero out NOBITS sections. There are 2 of them: 91 * - the .bss section; 92 * - the coherent memory section. 93 * --------------------------------------------- 94 */ 95 ldr x0, =__BSS_START__ 96 ldr x1, =__BSS_SIZE__ 97 bl zeromem 98 99#if USE_COHERENT_MEM 100 ldr x0, =__COHERENT_RAM_START__ 101 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 102 bl zeromem 103#endif 104 105 /* -------------------------------------------- 106 * Allocate a stack whose memory will be marked 107 * as Normal-IS-WBWA when the MMU is enabled. 108 * There is no risk of reading stale stack 109 * memory after enabling the MMU as only the 110 * primary cpu is running at the moment. 111 * -------------------------------------------- 112 */ 113 bl plat_set_my_stack 114 115 /* --------------------------------------------- 116 * Initialize the stack protector canary before 117 * any C code is called. 118 * --------------------------------------------- 119 */ 120#if STACK_PROTECTOR_ENABLED 121 bl update_stack_protector_canary 122#endif 123 124 /* --------------------------------------------- 125 * Perform early platform setup & platform 126 * specific early arch. setup e.g. mmu setup 127 * --------------------------------------------- 128 */ 129 bl tsp_early_platform_setup 130 bl tsp_plat_arch_setup 131 132 /* --------------------------------------------- 133 * Jump to main function. 134 * --------------------------------------------- 135 */ 136 bl tsp_main 137 138 /* --------------------------------------------- 139 * Tell TSPD that we are done initialising 140 * --------------------------------------------- 141 */ 142 mov x1, x0 143 mov x0, #TSP_ENTRY_DONE 144 smc #0 145 146tsp_entrypoint_panic: 147 b tsp_entrypoint_panic 148endfunc tsp_entrypoint 149 150 151 /* ------------------------------------------- 152 * Table of entrypoint vectors provided to the 153 * TSPD for the various entrypoints 154 * ------------------------------------------- 155 */ 156func tsp_vector_table 157 b tsp_yield_smc_entry 158 b tsp_fast_smc_entry 159 b tsp_cpu_on_entry 160 b tsp_cpu_off_entry 161 b tsp_cpu_resume_entry 162 b tsp_cpu_suspend_entry 163 b tsp_sel1_intr_entry 164 b tsp_system_off_entry 165 b tsp_system_reset_entry 166 b tsp_abort_yield_smc_entry 167endfunc tsp_vector_table 168 169 /*--------------------------------------------- 170 * This entrypoint is used by the TSPD when this 171 * cpu is to be turned off through a CPU_OFF 172 * psci call to ask the TSP to perform any 173 * bookeeping necessary. In the current 174 * implementation, the TSPD expects the TSP to 175 * re-initialise its state so nothing is done 176 * here except for acknowledging the request. 177 * --------------------------------------------- 178 */ 179func tsp_cpu_off_entry 180 bl tsp_cpu_off_main 181 restore_args_call_smc 182endfunc tsp_cpu_off_entry 183 184 /*--------------------------------------------- 185 * This entrypoint is used by the TSPD when the 186 * system is about to be switched off (through 187 * a SYSTEM_OFF psci call) to ask the TSP to 188 * perform any necessary bookkeeping. 189 * --------------------------------------------- 190 */ 191func tsp_system_off_entry 192 bl tsp_system_off_main 193 restore_args_call_smc 194endfunc tsp_system_off_entry 195 196 /*--------------------------------------------- 197 * This entrypoint is used by the TSPD when the 198 * system is about to be reset (through a 199 * SYSTEM_RESET psci call) to ask the TSP to 200 * perform any necessary bookkeeping. 201 * --------------------------------------------- 202 */ 203func tsp_system_reset_entry 204 bl tsp_system_reset_main 205 restore_args_call_smc 206endfunc tsp_system_reset_entry 207 208 /*--------------------------------------------- 209 * This entrypoint is used by the TSPD when this 210 * cpu is turned on using a CPU_ON psci call to 211 * ask the TSP to initialise itself i.e. setup 212 * the mmu, stacks etc. Minimal architectural 213 * state will be initialised by the TSPD when 214 * this function is entered i.e. Caches and MMU 215 * will be turned off, the execution state 216 * will be aarch64 and exceptions masked. 217 * --------------------------------------------- 218 */ 219func tsp_cpu_on_entry 220 /* --------------------------------------------- 221 * Set the exception vector to something sane. 222 * --------------------------------------------- 223 */ 224 adr x0, tsp_exceptions 225 msr vbar_el1, x0 226 isb 227 228 /* Enable the SError interrupt */ 229 msr daifclr, #DAIF_ABT_BIT 230 231 /* --------------------------------------------- 232 * Enable the instruction cache, stack pointer 233 * and data access alignment checks 234 * --------------------------------------------- 235 */ 236 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 237 mrs x0, sctlr_el1 238 orr x0, x0, x1 239 msr sctlr_el1, x0 240 isb 241 242 /* -------------------------------------------- 243 * Give ourselves a stack whose memory will be 244 * marked as Normal-IS-WBWA when the MMU is 245 * enabled. 246 * -------------------------------------------- 247 */ 248 bl plat_set_my_stack 249 250 /* -------------------------------------------- 251 * Enable MMU and D-caches together. 252 * -------------------------------------------- 253 */ 254 mov x0, #0 255 bl bl32_plat_enable_mmu 256 257 /* --------------------------------------------- 258 * Enter C runtime to perform any remaining 259 * book keeping 260 * --------------------------------------------- 261 */ 262 bl tsp_cpu_on_main 263 restore_args_call_smc 264 265 /* Should never reach here */ 266tsp_cpu_on_entry_panic: 267 b tsp_cpu_on_entry_panic 268endfunc tsp_cpu_on_entry 269 270 /*--------------------------------------------- 271 * This entrypoint is used by the TSPD when this 272 * cpu is to be suspended through a CPU_SUSPEND 273 * psci call to ask the TSP to perform any 274 * bookeeping necessary. In the current 275 * implementation, the TSPD saves and restores 276 * the EL1 state. 277 * --------------------------------------------- 278 */ 279func tsp_cpu_suspend_entry 280 bl tsp_cpu_suspend_main 281 restore_args_call_smc 282endfunc tsp_cpu_suspend_entry 283 284 /*------------------------------------------------- 285 * This entrypoint is used by the TSPD to pass 286 * control for `synchronously` handling a S-EL1 287 * Interrupt which was triggered while executing 288 * in normal world. 'x0' contains a magic number 289 * which indicates this. TSPD expects control to 290 * be handed back at the end of interrupt 291 * processing. This is done through an SMC. 292 * The handover agreement is: 293 * 294 * 1. PSTATE.DAIF are set upon entry. 'x1' has 295 * the ELR_EL3 from the non-secure state. 296 * 2. TSP has to preserve the callee saved 297 * general purpose registers, SP_EL1/EL0 and 298 * LR. 299 * 3. TSP has to preserve the system and vfp 300 * registers (if applicable). 301 * 4. TSP can use 'x0-x18' to enable its C 302 * runtime. 303 * 5. TSP returns to TSPD using an SMC with 304 * 'x0' = TSP_HANDLED_S_EL1_INTR 305 * ------------------------------------------------ 306 */ 307func tsp_sel1_intr_entry 308#if DEBUG 309 mov_imm x2, TSP_HANDLE_SEL1_INTR_AND_RETURN 310 cmp x0, x2 311 b.ne tsp_sel1_int_entry_panic 312#endif 313 /*------------------------------------------------- 314 * Save any previous context needed to perform 315 * an exception return from S-EL1 e.g. context 316 * from a previous Non secure Interrupt. 317 * Update statistics and handle the S-EL1 318 * interrupt before returning to the TSPD. 319 * IRQ/FIQs are not enabled since that will 320 * complicate the implementation. Execution 321 * will be transferred back to the normal world 322 * in any case. The handler can return 0 323 * if the interrupt was handled or TSP_PREEMPTED 324 * if the expected interrupt was preempted 325 * by an interrupt that should be handled in EL3 326 * e.g. Group 0 interrupt in GICv3. In both 327 * the cases switch to EL3 using SMC with id 328 * TSP_HANDLED_S_EL1_INTR. Any other return value 329 * from the handler will result in panic. 330 * ------------------------------------------------ 331 */ 332 save_eret_context x2 x3 333 bl tsp_update_sync_sel1_intr_stats 334 bl tsp_common_int_handler 335 /* Check if the S-EL1 interrupt has been handled */ 336 cbnz x0, tsp_sel1_intr_check_preemption 337 b tsp_sel1_intr_return 338tsp_sel1_intr_check_preemption: 339 /* Check if the S-EL1 interrupt has been preempted */ 340 mov_imm x1, TSP_PREEMPTED 341 cmp x0, x1 342 b.ne tsp_sel1_int_entry_panic 343tsp_sel1_intr_return: 344 mov_imm x0, TSP_HANDLED_S_EL1_INTR 345 restore_eret_context x2 x3 346 smc #0 347 348 /* Should never reach here */ 349tsp_sel1_int_entry_panic: 350 no_ret plat_panic_handler 351endfunc tsp_sel1_intr_entry 352 353 /*--------------------------------------------- 354 * This entrypoint is used by the TSPD when this 355 * cpu resumes execution after an earlier 356 * CPU_SUSPEND psci call to ask the TSP to 357 * restore its saved context. In the current 358 * implementation, the TSPD saves and restores 359 * EL1 state so nothing is done here apart from 360 * acknowledging the request. 361 * --------------------------------------------- 362 */ 363func tsp_cpu_resume_entry 364 bl tsp_cpu_resume_main 365 restore_args_call_smc 366 367 /* Should never reach here */ 368 no_ret plat_panic_handler 369endfunc tsp_cpu_resume_entry 370 371 /*--------------------------------------------- 372 * This entrypoint is used by the TSPD to ask 373 * the TSP to service a fast smc request. 374 * --------------------------------------------- 375 */ 376func tsp_fast_smc_entry 377 bl tsp_smc_handler 378 restore_args_call_smc 379 380 /* Should never reach here */ 381 no_ret plat_panic_handler 382endfunc tsp_fast_smc_entry 383 384 /*--------------------------------------------- 385 * This entrypoint is used by the TSPD to ask 386 * the TSP to service a Yielding SMC request. 387 * We will enable preemption during execution 388 * of tsp_smc_handler. 389 * --------------------------------------------- 390 */ 391func tsp_yield_smc_entry 392 msr daifclr, #DAIF_FIQ_BIT | DAIF_IRQ_BIT 393 bl tsp_smc_handler 394 msr daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT 395 restore_args_call_smc 396 397 /* Should never reach here */ 398 no_ret plat_panic_handler 399endfunc tsp_yield_smc_entry 400 401 /*--------------------------------------------------------------------- 402 * This entrypoint is used by the TSPD to abort a pre-empted Yielding 403 * SMC. It could be on behalf of non-secure world or because a CPU 404 * suspend/CPU off request needs to abort the preempted SMC. 405 * -------------------------------------------------------------------- 406 */ 407func tsp_abort_yield_smc_entry 408 409 /* 410 * Exceptions masking is already done by the TSPD when entering this 411 * hook so there is no need to do it here. 412 */ 413 414 /* Reset the stack used by the pre-empted SMC */ 415 bl plat_set_my_stack 416 417 /* 418 * Allow some cleanup such as releasing locks. 419 */ 420 bl tsp_abort_smc_handler 421 422 restore_args_call_smc 423 424 /* Should never reach here */ 425 bl plat_panic_handler 426endfunc tsp_abort_yield_smc_entry 427