1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <tsp.h> 34#include <xlat_tables.h> 35 36 37 .globl tsp_entrypoint 38 .globl tsp_vector_table 39 40 41 42 /* --------------------------------------------- 43 * Populate the params in x0-x7 from the pointer 44 * to the smc args structure in x0. 45 * --------------------------------------------- 46 */ 47 .macro restore_args_call_smc 48 ldp x6, x7, [x0, #TSP_ARG6] 49 ldp x4, x5, [x0, #TSP_ARG4] 50 ldp x2, x3, [x0, #TSP_ARG2] 51 ldp x0, x1, [x0, #TSP_ARG0] 52 smc #0 53 .endm 54 55 .macro save_eret_context reg1 reg2 56 mrs \reg1, elr_el1 57 mrs \reg2, spsr_el1 58 stp \reg1, \reg2, [sp, #-0x10]! 59 stp x30, x18, [sp, #-0x10]! 60 .endm 61 62 .macro restore_eret_context reg1 reg2 63 ldp x30, x18, [sp], #0x10 64 ldp \reg1, \reg2, [sp], #0x10 65 msr elr_el1, \reg1 66 msr spsr_el1, \reg2 67 .endm 68 69 .section .text, "ax" 70 .align 3 71 72func tsp_entrypoint 73 74 /* --------------------------------------------- 75 * Set the exception vector to something sane. 76 * --------------------------------------------- 77 */ 78 adr x0, tsp_exceptions 79 msr vbar_el1, x0 80 81 /* --------------------------------------------- 82 * Enable the instruction cache, stack pointer 83 * and data access alignment checks 84 * --------------------------------------------- 85 */ 86 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 87 mrs x0, sctlr_el1 88 orr x0, x0, x1 89 msr sctlr_el1, x0 90 isb 91 92 /* --------------------------------------------- 93 * Zero out NOBITS sections. There are 2 of them: 94 * - the .bss section; 95 * - the coherent memory section. 96 * --------------------------------------------- 97 */ 98 ldr x0, =__BSS_START__ 99 ldr x1, =__BSS_SIZE__ 100 bl zeromem16 101 102 ldr x0, =__COHERENT_RAM_START__ 103 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 104 bl zeromem16 105 106 /* -------------------------------------------- 107 * Allocate a stack whose memory will be marked 108 * as Normal-IS-WBWA when the MMU is enabled. 109 * There is no risk of reading stale stack 110 * memory after enabling the MMU as only the 111 * primary cpu is running at the moment. 112 * -------------------------------------------- 113 */ 114 mrs x0, mpidr_el1 115 bl platform_set_stack 116 117 /* --------------------------------------------- 118 * Perform early platform setup & platform 119 * specific early arch. setup e.g. mmu setup 120 * --------------------------------------------- 121 */ 122 bl bl32_early_platform_setup 123 bl bl32_plat_arch_setup 124 125 /* --------------------------------------------- 126 * Jump to main function. 127 * --------------------------------------------- 128 */ 129 bl tsp_main 130 131 /* --------------------------------------------- 132 * Tell TSPD that we are done initialising 133 * --------------------------------------------- 134 */ 135 mov x1, x0 136 mov x0, #TSP_ENTRY_DONE 137 smc #0 138 139tsp_entrypoint_panic: 140 b tsp_entrypoint_panic 141 142 143 /* ------------------------------------------- 144 * Table of entrypoint vectors provided to the 145 * TSPD for the various entrypoints 146 * ------------------------------------------- 147 */ 148func tsp_vector_table 149 b tsp_std_smc_entry 150 b tsp_fast_smc_entry 151 b tsp_cpu_on_entry 152 b tsp_cpu_off_entry 153 b tsp_cpu_resume_entry 154 b tsp_cpu_suspend_entry 155 b tsp_fiq_entry 156 157 /*--------------------------------------------- 158 * This entrypoint is used by the TSPD when this 159 * cpu is to be turned off through a CPU_OFF 160 * psci call to ask the TSP to perform any 161 * bookeeping necessary. In the current 162 * implementation, the TSPD expects the TSP to 163 * re-initialise its state so nothing is done 164 * here except for acknowledging the request. 165 * --------------------------------------------- 166 */ 167func tsp_cpu_off_entry 168 bl tsp_cpu_off_main 169 restore_args_call_smc 170 171 /*--------------------------------------------- 172 * This entrypoint is used by the TSPD when this 173 * cpu is turned on using a CPU_ON psci call to 174 * ask the TSP to initialise itself i.e. setup 175 * the mmu, stacks etc. Minimal architectural 176 * state will be initialised by the TSPD when 177 * this function is entered i.e. Caches and MMU 178 * will be turned off, the execution state 179 * will be aarch64 and exceptions masked. 180 * --------------------------------------------- 181 */ 182func tsp_cpu_on_entry 183 /* --------------------------------------------- 184 * Set the exception vector to something sane. 185 * --------------------------------------------- 186 */ 187 adr x0, tsp_exceptions 188 msr vbar_el1, x0 189 190 /* --------------------------------------------- 191 * Enable the instruction cache, stack pointer 192 * and data access alignment checks 193 * --------------------------------------------- 194 */ 195 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 196 mrs x0, sctlr_el1 197 orr x0, x0, x1 198 msr sctlr_el1, x0 199 isb 200 201 /* -------------------------------------------- 202 * Give ourselves a stack whose memory will be 203 * marked as Normal-IS-WBWA when the MMU is 204 * enabled. 205 * -------------------------------------------- 206 */ 207 mrs x0, mpidr_el1 208 bl platform_set_stack 209 210 /* -------------------------------------------- 211 * Enable the MMU with the DCache disabled. It 212 * is safe to use stacks allocated in normal 213 * memory as a result. All memory accesses are 214 * marked nGnRnE when the MMU is disabled. So 215 * all the stack writes will make it to memory. 216 * All memory accesses are marked Non-cacheable 217 * when the MMU is enabled but D$ is disabled. 218 * So used stack memory is guaranteed to be 219 * visible immediately after the MMU is enabled 220 * Enabling the DCache at the same time as the 221 * MMU can lead to speculatively fetched and 222 * possibly stale stack memory being read from 223 * other caches. This can lead to coherency 224 * issues. 225 * -------------------------------------------- 226 */ 227 mov x0, #DISABLE_DCACHE 228 bl bl32_plat_enable_mmu 229 230 /* --------------------------------------------- 231 * Enable the Data cache now that the MMU has 232 * been enabled. The stack has been unwound. It 233 * will be written first before being read. This 234 * will invalidate any stale cache lines resi- 235 * -dent in other caches. We assume that 236 * interconnect coherency has been enabled for 237 * this cluster by EL3 firmware. 238 * --------------------------------------------- 239 */ 240 mrs x0, sctlr_el1 241 orr x0, x0, #SCTLR_C_BIT 242 msr sctlr_el1, x0 243 isb 244 245 /* --------------------------------------------- 246 * Enter C runtime to perform any remaining 247 * book keeping 248 * --------------------------------------------- 249 */ 250 bl tsp_cpu_on_main 251 restore_args_call_smc 252 253 /* Should never reach here */ 254tsp_cpu_on_entry_panic: 255 b tsp_cpu_on_entry_panic 256 257 /*--------------------------------------------- 258 * This entrypoint is used by the TSPD when this 259 * cpu is to be suspended through a CPU_SUSPEND 260 * psci call to ask the TSP to perform any 261 * bookeeping necessary. In the current 262 * implementation, the TSPD saves and restores 263 * the EL1 state. 264 * --------------------------------------------- 265 */ 266func tsp_cpu_suspend_entry 267 bl tsp_cpu_suspend_main 268 restore_args_call_smc 269 270 /*--------------------------------------------- 271 * This entrypoint is used by the TSPD to pass 272 * control for handling a pending S-EL1 FIQ. 273 * 'x0' contains a magic number which indicates 274 * this. TSPD expects control to be handed back 275 * at the end of FIQ processing. This is done 276 * through an SMC. The handover agreement is: 277 * 278 * 1. PSTATE.DAIF are set upon entry. 'x1' has 279 * the ELR_EL3 from the non-secure state. 280 * 2. TSP has to preserve the callee saved 281 * general purpose registers, SP_EL1/EL0 and 282 * LR. 283 * 3. TSP has to preserve the system and vfp 284 * registers (if applicable). 285 * 4. TSP can use 'x0-x18' to enable its C 286 * runtime. 287 * 5. TSP returns to TSPD using an SMC with 288 * 'x0' = TSP_HANDLED_S_EL1_FIQ 289 * --------------------------------------------- 290 */ 291func tsp_fiq_entry 292#if DEBUG 293 mov x2, #(TSP_HANDLE_FIQ_AND_RETURN & ~0xffff) 294 movk x2, #(TSP_HANDLE_FIQ_AND_RETURN & 0xffff) 295 cmp x0, x2 296 b.ne tsp_fiq_entry_panic 297#endif 298 /*--------------------------------------------- 299 * Save any previous context needed to perform 300 * an exception return from S-EL1 e.g. context 301 * from a previous IRQ. Update statistics and 302 * handle the FIQ before returning to the TSPD. 303 * IRQ/FIQs are not enabled since that will 304 * complicate the implementation. Execution 305 * will be transferred back to the normal world 306 * in any case. A non-zero return value from the 307 * fiq handler is an error. 308 * --------------------------------------------- 309 */ 310 save_eret_context x2 x3 311 bl tsp_update_sync_fiq_stats 312 bl tsp_fiq_handler 313 cbnz x0, tsp_fiq_entry_panic 314 restore_eret_context x2 x3 315 mov x0, #(TSP_HANDLED_S_EL1_FIQ & ~0xffff) 316 movk x0, #(TSP_HANDLED_S_EL1_FIQ & 0xffff) 317 smc #0 318 319tsp_fiq_entry_panic: 320 b tsp_fiq_entry_panic 321 322 /*--------------------------------------------- 323 * This entrypoint is used by the TSPD when this 324 * cpu resumes execution after an earlier 325 * CPU_SUSPEND psci call to ask the TSP to 326 * restore its saved context. In the current 327 * implementation, the TSPD saves and restores 328 * EL1 state so nothing is done here apart from 329 * acknowledging the request. 330 * --------------------------------------------- 331 */ 332func tsp_cpu_resume_entry 333 bl tsp_cpu_resume_main 334 restore_args_call_smc 335tsp_cpu_resume_panic: 336 b tsp_cpu_resume_panic 337 338 /*--------------------------------------------- 339 * This entrypoint is used by the TSPD to ask 340 * the TSP to service a fast smc request. 341 * --------------------------------------------- 342 */ 343func tsp_fast_smc_entry 344 bl tsp_smc_handler 345 restore_args_call_smc 346tsp_fast_smc_entry_panic: 347 b tsp_fast_smc_entry_panic 348 349 /*--------------------------------------------- 350 * This entrypoint is used by the TSPD to ask 351 * the TSP to service a std smc request. 352 * We will enable preemption during execution 353 * of tsp_smc_handler. 354 * --------------------------------------------- 355 */ 356func tsp_std_smc_entry 357 msr daifclr, #DAIF_FIQ_BIT | DAIF_IRQ_BIT 358 bl tsp_smc_handler 359 msr daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT 360 restore_args_call_smc 361tsp_std_smc_entry_panic: 362 b tsp_std_smc_entry_panic 363