1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <tsp.h> 34 35 36 .globl tsp_entrypoint 37 .globl tsp_vector_table 38 39 40 41 /* --------------------------------------------- 42 * Populate the params in x0-x7 from the pointer 43 * to the smc args structure in x0. 44 * --------------------------------------------- 45 */ 46 .macro restore_args_call_smc 47 ldp x6, x7, [x0, #TSP_ARG6] 48 ldp x4, x5, [x0, #TSP_ARG4] 49 ldp x2, x3, [x0, #TSP_ARG2] 50 ldp x0, x1, [x0, #TSP_ARG0] 51 smc #0 52 .endm 53 54 .macro save_eret_context reg1 reg2 55 mrs \reg1, elr_el1 56 mrs \reg2, spsr_el1 57 stp \reg1, \reg2, [sp, #-0x10]! 58 stp x30, x18, [sp, #-0x10]! 59 .endm 60 61 .macro restore_eret_context reg1 reg2 62 ldp x30, x18, [sp], #0x10 63 ldp \reg1, \reg2, [sp], #0x10 64 msr elr_el1, \reg1 65 msr spsr_el1, \reg2 66 .endm 67 68 .section .text, "ax" 69 .align 3 70 71func tsp_entrypoint 72 73 /* --------------------------------------------- 74 * The entrypoint is expected to be executed 75 * only by the primary cpu (at least for now). 76 * So, make sure no secondary has lost its way. 77 * --------------------------------------------- 78 */ 79 mrs x0, mpidr_el1 80 bl platform_is_primary_cpu 81 cbz x0, tsp_entrypoint_panic 82 83 /* --------------------------------------------- 84 * Set the exception vector to something sane. 85 * --------------------------------------------- 86 */ 87 adr x0, tsp_exceptions 88 msr vbar_el1, x0 89 90 /* --------------------------------------------- 91 * Enable the instruction cache. 92 * --------------------------------------------- 93 */ 94 mrs x0, sctlr_el1 95 orr x0, x0, #SCTLR_I_BIT 96 msr sctlr_el1, x0 97 isb 98 99 /* --------------------------------------------- 100 * Zero out NOBITS sections. There are 2 of them: 101 * - the .bss section; 102 * - the coherent memory section. 103 * --------------------------------------------- 104 */ 105 ldr x0, =__BSS_START__ 106 ldr x1, =__BSS_SIZE__ 107 bl zeromem16 108 109 ldr x0, =__COHERENT_RAM_START__ 110 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 111 bl zeromem16 112 113 /* -------------------------------------------- 114 * Allocate a stack whose memory will be marked 115 * as Normal-IS-WBWA when the MMU is enabled. 116 * There is no risk of reading stale stack 117 * memory after enabling the MMU as only the 118 * primary cpu is running at the moment. 119 * -------------------------------------------- 120 */ 121 mrs x0, mpidr_el1 122 bl platform_set_stack 123 124 /* --------------------------------------------- 125 * Perform early platform setup & platform 126 * specific early arch. setup e.g. mmu setup 127 * --------------------------------------------- 128 */ 129 bl bl32_early_platform_setup 130 bl bl32_plat_arch_setup 131 132 /* --------------------------------------------- 133 * Jump to main function. 134 * --------------------------------------------- 135 */ 136 bl tsp_main 137 138 /* --------------------------------------------- 139 * Tell TSPD that we are done initialising 140 * --------------------------------------------- 141 */ 142 mov x1, x0 143 mov x0, #TSP_ENTRY_DONE 144 smc #0 145 146tsp_entrypoint_panic: 147 b tsp_entrypoint_panic 148 149 150 /* ------------------------------------------- 151 * Table of entrypoint vectors provided to the 152 * TSPD for the various entrypoints 153 * ------------------------------------------- 154 */ 155func tsp_vector_table 156 b tsp_std_smc_entry 157 b tsp_fast_smc_entry 158 b tsp_cpu_on_entry 159 b tsp_cpu_off_entry 160 b tsp_cpu_resume_entry 161 b tsp_cpu_suspend_entry 162 b tsp_fiq_entry 163 164 /*--------------------------------------------- 165 * This entrypoint is used by the TSPD when this 166 * cpu is to be turned off through a CPU_OFF 167 * psci call to ask the TSP to perform any 168 * bookeeping necessary. In the current 169 * implementation, the TSPD expects the TSP to 170 * re-initialise its state so nothing is done 171 * here except for acknowledging the request. 172 * --------------------------------------------- 173 */ 174func tsp_cpu_off_entry 175 bl tsp_cpu_off_main 176 restore_args_call_smc 177 178 /*--------------------------------------------- 179 * This entrypoint is used by the TSPD when this 180 * cpu is turned on using a CPU_ON psci call to 181 * ask the TSP to initialise itself i.e. setup 182 * the mmu, stacks etc. Minimal architectural 183 * state will be initialised by the TSPD when 184 * this function is entered i.e. Caches and MMU 185 * will be turned off, the execution state 186 * will be aarch64 and exceptions masked. 187 * --------------------------------------------- 188 */ 189func tsp_cpu_on_entry 190 /* --------------------------------------------- 191 * Set the exception vector to something sane. 192 * --------------------------------------------- 193 */ 194 adr x0, tsp_exceptions 195 msr vbar_el1, x0 196 197 /* --------------------------------------------- 198 * Enable the instruction cache. 199 * --------------------------------------------- 200 */ 201 mrs x0, sctlr_el1 202 orr x0, x0, #SCTLR_I_BIT 203 msr sctlr_el1, x0 204 isb 205 206 /* -------------------------------------------- 207 * Give ourselves a small coherent stack to 208 * ease the pain of initializing the MMU 209 * -------------------------------------------- 210 */ 211 mrs x0, mpidr_el1 212 bl platform_set_coherent_stack 213 214 /* --------------------------------------------- 215 * Initialise the MMU 216 * --------------------------------------------- 217 */ 218 bl bl32_plat_enable_mmu 219 220 /* --------------------------------------------- 221 * Give ourselves a stack allocated in Normal 222 * -IS-WBWA memory 223 * --------------------------------------------- 224 */ 225 mrs x0, mpidr_el1 226 bl platform_set_stack 227 228 /* --------------------------------------------- 229 * Enter C runtime to perform any remaining 230 * book keeping 231 * --------------------------------------------- 232 */ 233 bl tsp_cpu_on_main 234 restore_args_call_smc 235 236 /* Should never reach here */ 237tsp_cpu_on_entry_panic: 238 b tsp_cpu_on_entry_panic 239 240 /*--------------------------------------------- 241 * This entrypoint is used by the TSPD when this 242 * cpu is to be suspended through a CPU_SUSPEND 243 * psci call to ask the TSP to perform any 244 * bookeeping necessary. In the current 245 * implementation, the TSPD saves and restores 246 * the EL1 state. 247 * --------------------------------------------- 248 */ 249func tsp_cpu_suspend_entry 250 bl tsp_cpu_suspend_main 251 restore_args_call_smc 252 253 /*--------------------------------------------- 254 * This entrypoint is used by the TSPD to pass 255 * control for handling a pending S-EL1 FIQ. 256 * 'x0' contains a magic number which indicates 257 * this. TSPD expects control to be handed back 258 * at the end of FIQ processing. This is done 259 * through an SMC. The handover agreement is: 260 * 261 * 1. PSTATE.DAIF are set upon entry. 'x1' has 262 * the ELR_EL3 from the non-secure state. 263 * 2. TSP has to preserve the callee saved 264 * general purpose registers, SP_EL1/EL0 and 265 * LR. 266 * 3. TSP has to preserve the system and vfp 267 * registers (if applicable). 268 * 4. TSP can use 'x0-x18' to enable its C 269 * runtime. 270 * 5. TSP returns to TSPD using an SMC with 271 * 'x0' = TSP_HANDLED_S_EL1_FIQ 272 * --------------------------------------------- 273 */ 274func tsp_fiq_entry 275#if DEBUG 276 mov x2, #(TSP_HANDLE_FIQ_AND_RETURN & ~0xffff) 277 movk x2, #(TSP_HANDLE_FIQ_AND_RETURN & 0xffff) 278 cmp x0, x2 279 b.ne tsp_fiq_entry_panic 280#endif 281 /*--------------------------------------------- 282 * Save any previous context needed to perform 283 * an exception return from S-EL1 e.g. context 284 * from a previous IRQ. Update statistics and 285 * handle the FIQ before returning to the TSPD. 286 * IRQ/FIQs are not enabled since that will 287 * complicate the implementation. Execution 288 * will be transferred back to the normal world 289 * in any case. A non-zero return value from the 290 * fiq handler is an error. 291 * --------------------------------------------- 292 */ 293 save_eret_context x2 x3 294 bl tsp_update_sync_fiq_stats 295 bl tsp_fiq_handler 296 cbnz x0, tsp_fiq_entry_panic 297 restore_eret_context x2 x3 298 mov x0, #(TSP_HANDLED_S_EL1_FIQ & ~0xffff) 299 movk x0, #(TSP_HANDLED_S_EL1_FIQ & 0xffff) 300 smc #0 301 302tsp_fiq_entry_panic: 303 b tsp_fiq_entry_panic 304 305 /*--------------------------------------------- 306 * This entrypoint is used by the TSPD when this 307 * cpu resumes execution after an earlier 308 * CPU_SUSPEND psci call to ask the TSP to 309 * restore its saved context. In the current 310 * implementation, the TSPD saves and restores 311 * EL1 state so nothing is done here apart from 312 * acknowledging the request. 313 * --------------------------------------------- 314 */ 315func tsp_cpu_resume_entry 316 bl tsp_cpu_resume_main 317 restore_args_call_smc 318tsp_cpu_resume_panic: 319 b tsp_cpu_resume_panic 320 321 /*--------------------------------------------- 322 * This entrypoint is used by the TSPD to ask 323 * the TSP to service a fast smc request. 324 * --------------------------------------------- 325 */ 326func tsp_fast_smc_entry 327 bl tsp_smc_handler 328 restore_args_call_smc 329tsp_fast_smc_entry_panic: 330 b tsp_fast_smc_entry_panic 331 332 /*--------------------------------------------- 333 * This entrypoint is used by the TSPD to ask 334 * the TSP to service a std smc request. 335 * We will enable preemption during execution 336 * of tsp_smc_handler. 337 * --------------------------------------------- 338 */ 339func tsp_std_smc_entry 340 msr daifclr, #DAIF_FIQ_BIT | DAIF_IRQ_BIT 341 bl tsp_smc_handler 342 msr daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT 343 restore_args_call_smc 344tsp_std_smc_entry_panic: 345 b tsp_std_smc_entry_panic 346