1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <tsp.h> 34#include <xlat_tables.h> 35#include "../tsp_private.h" 36 37 38 .globl tsp_entrypoint 39 .globl tsp_vector_table 40 41 42 43 /* --------------------------------------------- 44 * Populate the params in x0-x7 from the pointer 45 * to the smc args structure in x0. 46 * --------------------------------------------- 47 */ 48 .macro restore_args_call_smc 49 ldp x6, x7, [x0, #TSP_ARG6] 50 ldp x4, x5, [x0, #TSP_ARG4] 51 ldp x2, x3, [x0, #TSP_ARG2] 52 ldp x0, x1, [x0, #TSP_ARG0] 53 smc #0 54 .endm 55 56 .macro save_eret_context reg1 reg2 57 mrs \reg1, elr_el1 58 mrs \reg2, spsr_el1 59 stp \reg1, \reg2, [sp, #-0x10]! 60 stp x30, x18, [sp, #-0x10]! 61 .endm 62 63 .macro restore_eret_context reg1 reg2 64 ldp x30, x18, [sp], #0x10 65 ldp \reg1, \reg2, [sp], #0x10 66 msr elr_el1, \reg1 67 msr spsr_el1, \reg2 68 .endm 69 70 .section .text, "ax" 71 .align 3 72 73func tsp_entrypoint 74 75 /* --------------------------------------------- 76 * Set the exception vector to something sane. 77 * --------------------------------------------- 78 */ 79 adr x0, tsp_exceptions 80 msr vbar_el1, x0 81 isb 82 83 /* --------------------------------------------- 84 * Enable the SError interrupt now that the 85 * exception vectors have been setup. 86 * --------------------------------------------- 87 */ 88 msr daifclr, #DAIF_ABT_BIT 89 90 /* --------------------------------------------- 91 * Enable the instruction cache, stack pointer 92 * and data access alignment checks 93 * --------------------------------------------- 94 */ 95 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 96 mrs x0, sctlr_el1 97 orr x0, x0, x1 98 msr sctlr_el1, x0 99 isb 100 101 /* --------------------------------------------- 102 * Zero out NOBITS sections. There are 2 of them: 103 * - the .bss section; 104 * - the coherent memory section. 105 * --------------------------------------------- 106 */ 107 ldr x0, =__BSS_START__ 108 ldr x1, =__BSS_SIZE__ 109 bl zeromem16 110 111 ldr x0, =__COHERENT_RAM_START__ 112 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 113 bl zeromem16 114 115 /* -------------------------------------------- 116 * Allocate a stack whose memory will be marked 117 * as Normal-IS-WBWA when the MMU is enabled. 118 * There is no risk of reading stale stack 119 * memory after enabling the MMU as only the 120 * primary cpu is running at the moment. 121 * -------------------------------------------- 122 */ 123 mrs x0, mpidr_el1 124 bl platform_set_stack 125 126 /* --------------------------------------------- 127 * Perform early platform setup & platform 128 * specific early arch. setup e.g. mmu setup 129 * --------------------------------------------- 130 */ 131 bl tsp_early_platform_setup 132 bl tsp_plat_arch_setup 133 134 /* --------------------------------------------- 135 * Jump to main function. 136 * --------------------------------------------- 137 */ 138 bl tsp_main 139 140 /* --------------------------------------------- 141 * Tell TSPD that we are done initialising 142 * --------------------------------------------- 143 */ 144 mov x1, x0 145 mov x0, #TSP_ENTRY_DONE 146 smc #0 147 148tsp_entrypoint_panic: 149 b tsp_entrypoint_panic 150 151 152 /* ------------------------------------------- 153 * Table of entrypoint vectors provided to the 154 * TSPD for the various entrypoints 155 * ------------------------------------------- 156 */ 157func tsp_vector_table 158 b tsp_std_smc_entry 159 b tsp_fast_smc_entry 160 b tsp_cpu_on_entry 161 b tsp_cpu_off_entry 162 b tsp_cpu_resume_entry 163 b tsp_cpu_suspend_entry 164 b tsp_fiq_entry 165 166 /*--------------------------------------------- 167 * This entrypoint is used by the TSPD when this 168 * cpu is to be turned off through a CPU_OFF 169 * psci call to ask the TSP to perform any 170 * bookeeping necessary. In the current 171 * implementation, the TSPD expects the TSP to 172 * re-initialise its state so nothing is done 173 * here except for acknowledging the request. 174 * --------------------------------------------- 175 */ 176func tsp_cpu_off_entry 177 bl tsp_cpu_off_main 178 restore_args_call_smc 179 180 /*--------------------------------------------- 181 * This entrypoint is used by the TSPD when this 182 * cpu is turned on using a CPU_ON psci call to 183 * ask the TSP to initialise itself i.e. setup 184 * the mmu, stacks etc. Minimal architectural 185 * state will be initialised by the TSPD when 186 * this function is entered i.e. Caches and MMU 187 * will be turned off, the execution state 188 * will be aarch64 and exceptions masked. 189 * --------------------------------------------- 190 */ 191func tsp_cpu_on_entry 192 /* --------------------------------------------- 193 * Set the exception vector to something sane. 194 * --------------------------------------------- 195 */ 196 adr x0, tsp_exceptions 197 msr vbar_el1, x0 198 isb 199 200 /* Enable the SError interrupt */ 201 msr daifclr, #DAIF_ABT_BIT 202 203 /* --------------------------------------------- 204 * Enable the instruction cache, stack pointer 205 * and data access alignment checks 206 * --------------------------------------------- 207 */ 208 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 209 mrs x0, sctlr_el1 210 orr x0, x0, x1 211 msr sctlr_el1, x0 212 isb 213 214 /* -------------------------------------------- 215 * Give ourselves a stack whose memory will be 216 * marked as Normal-IS-WBWA when the MMU is 217 * enabled. 218 * -------------------------------------------- 219 */ 220 mrs x0, mpidr_el1 221 bl platform_set_stack 222 223 /* -------------------------------------------- 224 * Enable the MMU with the DCache disabled. It 225 * is safe to use stacks allocated in normal 226 * memory as a result. All memory accesses are 227 * marked nGnRnE when the MMU is disabled. So 228 * all the stack writes will make it to memory. 229 * All memory accesses are marked Non-cacheable 230 * when the MMU is enabled but D$ is disabled. 231 * So used stack memory is guaranteed to be 232 * visible immediately after the MMU is enabled 233 * Enabling the DCache at the same time as the 234 * MMU can lead to speculatively fetched and 235 * possibly stale stack memory being read from 236 * other caches. This can lead to coherency 237 * issues. 238 * -------------------------------------------- 239 */ 240 mov x0, #DISABLE_DCACHE 241 bl bl32_plat_enable_mmu 242 243 /* --------------------------------------------- 244 * Enable the Data cache now that the MMU has 245 * been enabled. The stack has been unwound. It 246 * will be written first before being read. This 247 * will invalidate any stale cache lines resi- 248 * -dent in other caches. We assume that 249 * interconnect coherency has been enabled for 250 * this cluster by EL3 firmware. 251 * --------------------------------------------- 252 */ 253 mrs x0, sctlr_el1 254 orr x0, x0, #SCTLR_C_BIT 255 msr sctlr_el1, x0 256 isb 257 258 /* --------------------------------------------- 259 * Enter C runtime to perform any remaining 260 * book keeping 261 * --------------------------------------------- 262 */ 263 bl tsp_cpu_on_main 264 restore_args_call_smc 265 266 /* Should never reach here */ 267tsp_cpu_on_entry_panic: 268 b tsp_cpu_on_entry_panic 269 270 /*--------------------------------------------- 271 * This entrypoint is used by the TSPD when this 272 * cpu is to be suspended through a CPU_SUSPEND 273 * psci call to ask the TSP to perform any 274 * bookeeping necessary. In the current 275 * implementation, the TSPD saves and restores 276 * the EL1 state. 277 * --------------------------------------------- 278 */ 279func tsp_cpu_suspend_entry 280 bl tsp_cpu_suspend_main 281 restore_args_call_smc 282 283 /*--------------------------------------------- 284 * This entrypoint is used by the TSPD to pass 285 * control for handling a pending S-EL1 FIQ. 286 * 'x0' contains a magic number which indicates 287 * this. TSPD expects control to be handed back 288 * at the end of FIQ processing. This is done 289 * through an SMC. The handover agreement is: 290 * 291 * 1. PSTATE.DAIF are set upon entry. 'x1' has 292 * the ELR_EL3 from the non-secure state. 293 * 2. TSP has to preserve the callee saved 294 * general purpose registers, SP_EL1/EL0 and 295 * LR. 296 * 3. TSP has to preserve the system and vfp 297 * registers (if applicable). 298 * 4. TSP can use 'x0-x18' to enable its C 299 * runtime. 300 * 5. TSP returns to TSPD using an SMC with 301 * 'x0' = TSP_HANDLED_S_EL1_FIQ 302 * --------------------------------------------- 303 */ 304func tsp_fiq_entry 305#if DEBUG 306 mov x2, #(TSP_HANDLE_FIQ_AND_RETURN & ~0xffff) 307 movk x2, #(TSP_HANDLE_FIQ_AND_RETURN & 0xffff) 308 cmp x0, x2 309 b.ne tsp_fiq_entry_panic 310#endif 311 /*--------------------------------------------- 312 * Save any previous context needed to perform 313 * an exception return from S-EL1 e.g. context 314 * from a previous IRQ. Update statistics and 315 * handle the FIQ before returning to the TSPD. 316 * IRQ/FIQs are not enabled since that will 317 * complicate the implementation. Execution 318 * will be transferred back to the normal world 319 * in any case. A non-zero return value from the 320 * fiq handler is an error. 321 * --------------------------------------------- 322 */ 323 save_eret_context x2 x3 324 bl tsp_update_sync_fiq_stats 325 bl tsp_fiq_handler 326 cbnz x0, tsp_fiq_entry_panic 327 restore_eret_context x2 x3 328 mov x0, #(TSP_HANDLED_S_EL1_FIQ & ~0xffff) 329 movk x0, #(TSP_HANDLED_S_EL1_FIQ & 0xffff) 330 smc #0 331 332tsp_fiq_entry_panic: 333 b tsp_fiq_entry_panic 334 335 /*--------------------------------------------- 336 * This entrypoint is used by the TSPD when this 337 * cpu resumes execution after an earlier 338 * CPU_SUSPEND psci call to ask the TSP to 339 * restore its saved context. In the current 340 * implementation, the TSPD saves and restores 341 * EL1 state so nothing is done here apart from 342 * acknowledging the request. 343 * --------------------------------------------- 344 */ 345func tsp_cpu_resume_entry 346 bl tsp_cpu_resume_main 347 restore_args_call_smc 348tsp_cpu_resume_panic: 349 b tsp_cpu_resume_panic 350 351 /*--------------------------------------------- 352 * This entrypoint is used by the TSPD to ask 353 * the TSP to service a fast smc request. 354 * --------------------------------------------- 355 */ 356func tsp_fast_smc_entry 357 bl tsp_smc_handler 358 restore_args_call_smc 359tsp_fast_smc_entry_panic: 360 b tsp_fast_smc_entry_panic 361 362 /*--------------------------------------------- 363 * This entrypoint is used by the TSPD to ask 364 * the TSP to service a std smc request. 365 * We will enable preemption during execution 366 * of tsp_smc_handler. 367 * --------------------------------------------- 368 */ 369func tsp_std_smc_entry 370 msr daifclr, #DAIF_FIQ_BIT | DAIF_IRQ_BIT 371 bl tsp_smc_handler 372 msr daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT 373 restore_args_call_smc 374tsp_std_smc_entry_panic: 375 b tsp_std_smc_entry_panic 376