1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <tsp.h> 34 35 36 .globl tsp_entrypoint 37 .globl tsp_cpu_on_entry 38 .globl tsp_cpu_off_entry 39 .globl tsp_cpu_suspend_entry 40 .globl tsp_cpu_resume_entry 41 .globl tsp_fast_smc_entry 42 43 /* --------------------------------------------- 44 * Populate the params in x0-x7 from the pointer 45 * to the smc args structure in x0. 46 * --------------------------------------------- 47 */ 48 .macro restore_args_call_smc 49 ldp x6, x7, [x0, #TSP_ARG6] 50 ldp x4, x5, [x0, #TSP_ARG4] 51 ldp x2, x3, [x0, #TSP_ARG2] 52 ldp x0, x1, [x0, #TSP_ARG0] 53 smc #0 54 .endm 55 56 57func tsp_entrypoint 58 /*--------------------------------------------- 59 * Store the extents of the tzram available to 60 * BL32 for future use. 61 * TODO: We are assuming that x9-x10 will not be 62 * corrupted by any function before platform 63 * setup. 64 * --------------------------------------------- 65 */ 66 mov x9, x0 67 mov x10, x1 68 69 /* --------------------------------------------- 70 * The entrypoint is expected to be executed 71 * only by the primary cpu (at least for now). 72 * So, make sure no secondary has lost its way. 73 * --------------------------------------------- 74 */ 75 mrs x0, mpidr_el1 76 bl platform_is_primary_cpu 77 cbz x0, tsp_entrypoint_panic 78 79 /* --------------------------------------------- 80 * Set the exception vector to something sane. 81 * --------------------------------------------- 82 */ 83 adr x0, early_exceptions 84 msr vbar_el1, x0 85 86 /* --------------------------------------------- 87 * Enable the instruction cache. 88 * --------------------------------------------- 89 */ 90 mrs x0, sctlr_el1 91 orr x0, x0, #SCTLR_I_BIT 92 msr sctlr_el1, x0 93 isb 94 95 /* --------------------------------------------- 96 * Zero out NOBITS sections. There are 2 of them: 97 * - the .bss section; 98 * - the coherent memory section. 99 * --------------------------------------------- 100 */ 101 ldr x0, =__BSS_START__ 102 ldr x1, =__BSS_SIZE__ 103 bl zeromem16 104 105 ldr x0, =__COHERENT_RAM_START__ 106 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 107 bl zeromem16 108 109 /* -------------------------------------------- 110 * Give ourselves a small coherent stack to 111 * ease the pain of initializing the MMU 112 * -------------------------------------------- 113 */ 114 mrs x0, mpidr_el1 115 bl platform_set_coherent_stack 116 117 /* --------------------------------------------- 118 * Perform early platform setup & platform 119 * specific early arch. setup e.g. mmu setup 120 * --------------------------------------------- 121 */ 122 mov x0, x9 123 mov x1, x10 124 bl bl32_early_platform_setup 125 bl bl32_plat_arch_setup 126 127 /* --------------------------------------------- 128 * Give ourselves a stack allocated in Normal 129 * -IS-WBWA memory 130 * --------------------------------------------- 131 */ 132 mrs x0, mpidr_el1 133 bl platform_set_stack 134 135 /* --------------------------------------------- 136 * Jump to main function. 137 * --------------------------------------------- 138 */ 139 bl tsp_main 140 141 /* --------------------------------------------- 142 * Tell TSPD that we are done initialising 143 * --------------------------------------------- 144 */ 145 mov x1, x0 146 mov x0, #TSP_ENTRY_DONE 147 smc #0 148 149tsp_entrypoint_panic: 150 b tsp_entrypoint_panic 151 152 /*--------------------------------------------- 153 * This entrypoint is used by the TSPD when this 154 * cpu is to be turned off through a CPU_OFF 155 * psci call to ask the TSP to perform any 156 * bookeeping necessary. In the current 157 * implementation, the TSPD expects the TSP to 158 * re-initialise its state so nothing is done 159 * here except for acknowledging the request. 160 * --------------------------------------------- 161 */ 162func tsp_cpu_off_entry 163 bl tsp_cpu_off_main 164 restore_args_call_smc 165 166 /*--------------------------------------------- 167 * This entrypoint is used by the TSPD when this 168 * cpu is turned on using a CPU_ON psci call to 169 * ask the TSP to initialise itself i.e. setup 170 * the mmu, stacks etc. Minimal architectural 171 * state will be initialised by the TSPD when 172 * this function is entered i.e. Caches and MMU 173 * will be turned off, the execution state 174 * will be aarch64 and exceptions masked. 175 * --------------------------------------------- 176 */ 177func tsp_cpu_on_entry 178 /* --------------------------------------------- 179 * Set the exception vector to something sane. 180 * --------------------------------------------- 181 */ 182 adr x0, early_exceptions 183 msr vbar_el1, x0 184 185 /* --------------------------------------------- 186 * Enable the instruction cache. 187 * --------------------------------------------- 188 */ 189 mrs x0, sctlr_el1 190 orr x0, x0, #SCTLR_I_BIT 191 msr sctlr_el1, x0 192 isb 193 194 /* -------------------------------------------- 195 * Give ourselves a small coherent stack to 196 * ease the pain of initializing the MMU 197 * -------------------------------------------- 198 */ 199 mrs x0, mpidr_el1 200 bl platform_set_coherent_stack 201 202 /* --------------------------------------------- 203 * Initialise the MMU 204 * --------------------------------------------- 205 */ 206 bl enable_mmu 207 208 /* --------------------------------------------- 209 * Give ourselves a stack allocated in Normal 210 * -IS-WBWA memory 211 * --------------------------------------------- 212 */ 213 mrs x0, mpidr_el1 214 bl platform_set_stack 215 216 /* --------------------------------------------- 217 * Enter C runtime to perform any remaining 218 * book keeping 219 * --------------------------------------------- 220 */ 221 bl tsp_cpu_on_main 222 restore_args_call_smc 223 224 /* Should never reach here */ 225tsp_cpu_on_entry_panic: 226 b tsp_cpu_on_entry_panic 227 228 /*--------------------------------------------- 229 * This entrypoint is used by the TSPD when this 230 * cpu is to be suspended through a CPU_SUSPEND 231 * psci call to ask the TSP to perform any 232 * bookeeping necessary. In the current 233 * implementation, the TSPD saves and restores 234 * the EL1 state. 235 * --------------------------------------------- 236 */ 237func tsp_cpu_suspend_entry 238 bl tsp_cpu_suspend_main 239 restore_args_call_smc 240 241 /*--------------------------------------------- 242 * This entrypoint is used by the TSPD when this 243 * cpu resumes execution after an earlier 244 * CPU_SUSPEND psci call to ask the TSP to 245 * restore its saved context. In the current 246 * implementation, the TSPD saves and restores 247 * EL1 state so nothing is done here apart from 248 * acknowledging the request. 249 * --------------------------------------------- 250 */ 251func tsp_cpu_resume_entry 252 bl tsp_cpu_resume_main 253 restore_args_call_smc 254tsp_cpu_resume_panic: 255 b tsp_cpu_resume_panic 256 257 /*--------------------------------------------- 258 * This entrypoint is used by the TSPD to ask 259 * the TSP to service a fast smc request. 260 * --------------------------------------------- 261 */ 262func tsp_fast_smc_entry 263 bl tsp_fast_smc_handler 264 restore_args_call_smc 265tsp_fast_smc_entry_panic: 266 b tsp_fast_smc_entry_panic 267 268