1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <tsp.h> 34#include <xlat_tables.h> 35#include "../tsp_private.h" 36 37 38 .globl tsp_entrypoint 39 .globl tsp_vector_table 40 41 42 43 /* --------------------------------------------- 44 * Populate the params in x0-x7 from the pointer 45 * to the smc args structure in x0. 46 * --------------------------------------------- 47 */ 48 .macro restore_args_call_smc 49 ldp x6, x7, [x0, #TSP_ARG6] 50 ldp x4, x5, [x0, #TSP_ARG4] 51 ldp x2, x3, [x0, #TSP_ARG2] 52 ldp x0, x1, [x0, #TSP_ARG0] 53 smc #0 54 .endm 55 56 .macro save_eret_context reg1 reg2 57 mrs \reg1, elr_el1 58 mrs \reg2, spsr_el1 59 stp \reg1, \reg2, [sp, #-0x10]! 60 stp x30, x18, [sp, #-0x10]! 61 .endm 62 63 .macro restore_eret_context reg1 reg2 64 ldp x30, x18, [sp], #0x10 65 ldp \reg1, \reg2, [sp], #0x10 66 msr elr_el1, \reg1 67 msr spsr_el1, \reg2 68 .endm 69 70 .section .text, "ax" 71 .align 3 72 73func tsp_entrypoint 74 75 /* --------------------------------------------- 76 * Set the exception vector to something sane. 77 * --------------------------------------------- 78 */ 79 adr x0, tsp_exceptions 80 msr vbar_el1, x0 81 isb 82 83 /* --------------------------------------------- 84 * Enable the SError interrupt now that the 85 * exception vectors have been setup. 86 * --------------------------------------------- 87 */ 88 msr daifclr, #DAIF_ABT_BIT 89 90 /* --------------------------------------------- 91 * Enable the instruction cache, stack pointer 92 * and data access alignment checks 93 * --------------------------------------------- 94 */ 95 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 96 mrs x0, sctlr_el1 97 orr x0, x0, x1 98 msr sctlr_el1, x0 99 isb 100 101 /* --------------------------------------------- 102 * Zero out NOBITS sections. There are 2 of them: 103 * - the .bss section; 104 * - the coherent memory section. 105 * --------------------------------------------- 106 */ 107 ldr x0, =__BSS_START__ 108 ldr x1, =__BSS_SIZE__ 109 bl zeromem16 110 111#if USE_COHERENT_MEM 112 ldr x0, =__COHERENT_RAM_START__ 113 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 114 bl zeromem16 115#endif 116 117 /* -------------------------------------------- 118 * Allocate a stack whose memory will be marked 119 * as Normal-IS-WBWA when the MMU is enabled. 120 * There is no risk of reading stale stack 121 * memory after enabling the MMU as only the 122 * primary cpu is running at the moment. 123 * -------------------------------------------- 124 */ 125 mrs x0, mpidr_el1 126 bl platform_set_stack 127 128 /* --------------------------------------------- 129 * Perform early platform setup & platform 130 * specific early arch. setup e.g. mmu setup 131 * --------------------------------------------- 132 */ 133 bl tsp_early_platform_setup 134 bl tsp_plat_arch_setup 135 136 /* --------------------------------------------- 137 * Jump to main function. 138 * --------------------------------------------- 139 */ 140 bl tsp_main 141 142 /* --------------------------------------------- 143 * Tell TSPD that we are done initialising 144 * --------------------------------------------- 145 */ 146 mov x1, x0 147 mov x0, #TSP_ENTRY_DONE 148 smc #0 149 150tsp_entrypoint_panic: 151 b tsp_entrypoint_panic 152endfunc tsp_entrypoint 153 154 155 /* ------------------------------------------- 156 * Table of entrypoint vectors provided to the 157 * TSPD for the various entrypoints 158 * ------------------------------------------- 159 */ 160func tsp_vector_table 161 b tsp_std_smc_entry 162 b tsp_fast_smc_entry 163 b tsp_cpu_on_entry 164 b tsp_cpu_off_entry 165 b tsp_cpu_resume_entry 166 b tsp_cpu_suspend_entry 167 b tsp_fiq_entry 168 b tsp_system_off_entry 169 b tsp_system_reset_entry 170endfunc tsp_vector_table 171 172 /*--------------------------------------------- 173 * This entrypoint is used by the TSPD when this 174 * cpu is to be turned off through a CPU_OFF 175 * psci call to ask the TSP to perform any 176 * bookeeping necessary. In the current 177 * implementation, the TSPD expects the TSP to 178 * re-initialise its state so nothing is done 179 * here except for acknowledging the request. 180 * --------------------------------------------- 181 */ 182func tsp_cpu_off_entry 183 bl tsp_cpu_off_main 184 restore_args_call_smc 185endfunc tsp_cpu_off_entry 186 187 /*--------------------------------------------- 188 * This entrypoint is used by the TSPD when the 189 * system is about to be switched off (through 190 * a SYSTEM_OFF psci call) to ask the TSP to 191 * perform any necessary bookkeeping. 192 * --------------------------------------------- 193 */ 194func tsp_system_off_entry 195 bl tsp_system_off_main 196 restore_args_call_smc 197endfunc tsp_system_off_entry 198 199 /*--------------------------------------------- 200 * This entrypoint is used by the TSPD when the 201 * system is about to be reset (through a 202 * SYSTEM_RESET psci call) to ask the TSP to 203 * perform any necessary bookkeeping. 204 * --------------------------------------------- 205 */ 206func tsp_system_reset_entry 207 bl tsp_system_reset_main 208 restore_args_call_smc 209endfunc tsp_system_reset_entry 210 211 /*--------------------------------------------- 212 * This entrypoint is used by the TSPD when this 213 * cpu is turned on using a CPU_ON psci call to 214 * ask the TSP to initialise itself i.e. setup 215 * the mmu, stacks etc. Minimal architectural 216 * state will be initialised by the TSPD when 217 * this function is entered i.e. Caches and MMU 218 * will be turned off, the execution state 219 * will be aarch64 and exceptions masked. 220 * --------------------------------------------- 221 */ 222func tsp_cpu_on_entry 223 /* --------------------------------------------- 224 * Set the exception vector to something sane. 225 * --------------------------------------------- 226 */ 227 adr x0, tsp_exceptions 228 msr vbar_el1, x0 229 isb 230 231 /* Enable the SError interrupt */ 232 msr daifclr, #DAIF_ABT_BIT 233 234 /* --------------------------------------------- 235 * Enable the instruction cache, stack pointer 236 * and data access alignment checks 237 * --------------------------------------------- 238 */ 239 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 240 mrs x0, sctlr_el1 241 orr x0, x0, x1 242 msr sctlr_el1, x0 243 isb 244 245 /* -------------------------------------------- 246 * Give ourselves a stack whose memory will be 247 * marked as Normal-IS-WBWA when the MMU is 248 * enabled. 249 * -------------------------------------------- 250 */ 251 mrs x0, mpidr_el1 252 bl platform_set_stack 253 254 /* -------------------------------------------- 255 * Enable the MMU with the DCache disabled. It 256 * is safe to use stacks allocated in normal 257 * memory as a result. All memory accesses are 258 * marked nGnRnE when the MMU is disabled. So 259 * all the stack writes will make it to memory. 260 * All memory accesses are marked Non-cacheable 261 * when the MMU is enabled but D$ is disabled. 262 * So used stack memory is guaranteed to be 263 * visible immediately after the MMU is enabled 264 * Enabling the DCache at the same time as the 265 * MMU can lead to speculatively fetched and 266 * possibly stale stack memory being read from 267 * other caches. This can lead to coherency 268 * issues. 269 * -------------------------------------------- 270 */ 271 mov x0, #DISABLE_DCACHE 272 bl bl32_plat_enable_mmu 273 274 /* --------------------------------------------- 275 * Enable the Data cache now that the MMU has 276 * been enabled. The stack has been unwound. It 277 * will be written first before being read. This 278 * will invalidate any stale cache lines resi- 279 * -dent in other caches. We assume that 280 * interconnect coherency has been enabled for 281 * this cluster by EL3 firmware. 282 * --------------------------------------------- 283 */ 284 mrs x0, sctlr_el1 285 orr x0, x0, #SCTLR_C_BIT 286 msr sctlr_el1, x0 287 isb 288 289 /* --------------------------------------------- 290 * Enter C runtime to perform any remaining 291 * book keeping 292 * --------------------------------------------- 293 */ 294 bl tsp_cpu_on_main 295 restore_args_call_smc 296 297 /* Should never reach here */ 298tsp_cpu_on_entry_panic: 299 b tsp_cpu_on_entry_panic 300endfunc tsp_cpu_on_entry 301 302 /*--------------------------------------------- 303 * This entrypoint is used by the TSPD when this 304 * cpu is to be suspended through a CPU_SUSPEND 305 * psci call to ask the TSP to perform any 306 * bookeeping necessary. In the current 307 * implementation, the TSPD saves and restores 308 * the EL1 state. 309 * --------------------------------------------- 310 */ 311func tsp_cpu_suspend_entry 312 bl tsp_cpu_suspend_main 313 restore_args_call_smc 314endfunc tsp_cpu_suspend_entry 315 316 /*--------------------------------------------- 317 * This entrypoint is used by the TSPD to pass 318 * control for handling a pending S-EL1 FIQ. 319 * 'x0' contains a magic number which indicates 320 * this. TSPD expects control to be handed back 321 * at the end of FIQ processing. This is done 322 * through an SMC. The handover agreement is: 323 * 324 * 1. PSTATE.DAIF are set upon entry. 'x1' has 325 * the ELR_EL3 from the non-secure state. 326 * 2. TSP has to preserve the callee saved 327 * general purpose registers, SP_EL1/EL0 and 328 * LR. 329 * 3. TSP has to preserve the system and vfp 330 * registers (if applicable). 331 * 4. TSP can use 'x0-x18' to enable its C 332 * runtime. 333 * 5. TSP returns to TSPD using an SMC with 334 * 'x0' = TSP_HANDLED_S_EL1_FIQ 335 * --------------------------------------------- 336 */ 337func tsp_fiq_entry 338#if DEBUG 339 mov x2, #(TSP_HANDLE_FIQ_AND_RETURN & ~0xffff) 340 movk x2, #(TSP_HANDLE_FIQ_AND_RETURN & 0xffff) 341 cmp x0, x2 342 b.ne tsp_fiq_entry_panic 343#endif 344 /*--------------------------------------------- 345 * Save any previous context needed to perform 346 * an exception return from S-EL1 e.g. context 347 * from a previous IRQ. Update statistics and 348 * handle the FIQ before returning to the TSPD. 349 * IRQ/FIQs are not enabled since that will 350 * complicate the implementation. Execution 351 * will be transferred back to the normal world 352 * in any case. A non-zero return value from the 353 * fiq handler is an error. 354 * --------------------------------------------- 355 */ 356 save_eret_context x2 x3 357 bl tsp_update_sync_fiq_stats 358 bl tsp_fiq_handler 359 cbnz x0, tsp_fiq_entry_panic 360 restore_eret_context x2 x3 361 mov x0, #(TSP_HANDLED_S_EL1_FIQ & ~0xffff) 362 movk x0, #(TSP_HANDLED_S_EL1_FIQ & 0xffff) 363 smc #0 364 365tsp_fiq_entry_panic: 366 b tsp_fiq_entry_panic 367endfunc tsp_fiq_entry 368 369 /*--------------------------------------------- 370 * This entrypoint is used by the TSPD when this 371 * cpu resumes execution after an earlier 372 * CPU_SUSPEND psci call to ask the TSP to 373 * restore its saved context. In the current 374 * implementation, the TSPD saves and restores 375 * EL1 state so nothing is done here apart from 376 * acknowledging the request. 377 * --------------------------------------------- 378 */ 379func tsp_cpu_resume_entry 380 bl tsp_cpu_resume_main 381 restore_args_call_smc 382tsp_cpu_resume_panic: 383 b tsp_cpu_resume_panic 384endfunc tsp_cpu_resume_entry 385 386 /*--------------------------------------------- 387 * This entrypoint is used by the TSPD to ask 388 * the TSP to service a fast smc request. 389 * --------------------------------------------- 390 */ 391func tsp_fast_smc_entry 392 bl tsp_smc_handler 393 restore_args_call_smc 394tsp_fast_smc_entry_panic: 395 b tsp_fast_smc_entry_panic 396endfunc tsp_fast_smc_entry 397 398 /*--------------------------------------------- 399 * This entrypoint is used by the TSPD to ask 400 * the TSP to service a std smc request. 401 * We will enable preemption during execution 402 * of tsp_smc_handler. 403 * --------------------------------------------- 404 */ 405func tsp_std_smc_entry 406 msr daifclr, #DAIF_FIQ_BIT | DAIF_IRQ_BIT 407 bl tsp_smc_handler 408 msr daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT 409 restore_args_call_smc 410tsp_std_smc_entry_panic: 411 b tsp_std_smc_entry_panic 412endfunc tsp_std_smc_entry 413