1/* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <bl32/tsp/tsp.h> 10#include <lib/xlat_tables/xlat_tables_defs.h> 11 12#include "../tsp_private.h" 13 14 15 .globl tsp_entrypoint 16 .globl tsp_vector_table 17 18 19 20 /* --------------------------------------------- 21 * Populate the params in x0-x7 from the pointer 22 * to the smc args structure in x0. 23 * --------------------------------------------- 24 */ 25 .macro restore_args_call_smc 26 ldp x6, x7, [x0, #TSP_ARG6] 27 ldp x4, x5, [x0, #TSP_ARG4] 28 ldp x2, x3, [x0, #TSP_ARG2] 29 ldp x0, x1, [x0, #TSP_ARG0] 30 smc #0 31 .endm 32 33 .macro save_eret_context reg1 reg2 34 mrs \reg1, elr_el1 35 mrs \reg2, spsr_el1 36 stp \reg1, \reg2, [sp, #-0x10]! 37 stp x30, x18, [sp, #-0x10]! 38 .endm 39 40 .macro restore_eret_context reg1 reg2 41 ldp x30, x18, [sp], #0x10 42 ldp \reg1, \reg2, [sp], #0x10 43 msr elr_el1, \reg1 44 msr spsr_el1, \reg2 45 .endm 46 47func tsp_entrypoint _align=3 48 49 /* --------------------------------------------- 50 * Set the exception vector to something sane. 51 * --------------------------------------------- 52 */ 53 adr x0, tsp_exceptions 54 msr vbar_el1, x0 55 isb 56 57 /* --------------------------------------------- 58 * Enable the SError interrupt now that the 59 * exception vectors have been setup. 60 * --------------------------------------------- 61 */ 62 msr daifclr, #DAIF_ABT_BIT 63 64 /* --------------------------------------------- 65 * Enable the instruction cache, stack pointer 66 * and data access alignment checks and disable 67 * speculative loads. 68 * --------------------------------------------- 69 */ 70 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 71 mrs x0, sctlr_el1 72 orr x0, x0, x1 73 bic x0, x0, #SCTLR_DSSBS_BIT 74 msr sctlr_el1, x0 75 isb 76 77 /* --------------------------------------------- 78 * Invalidate the RW memory used by the BL32 79 * image. This includes the data and NOBITS 80 * sections. This is done to safeguard against 81 * possible corruption of this memory by dirty 82 * cache lines in a system cache as a result of 83 * use by an earlier boot loader stage. 84 * --------------------------------------------- 85 */ 86 adr x0, __RW_START__ 87 adr x1, __RW_END__ 88 sub x1, x1, x0 89 bl inv_dcache_range 90 91 /* --------------------------------------------- 92 * Zero out NOBITS sections. There are 2 of them: 93 * - the .bss section; 94 * - the coherent memory section. 95 * --------------------------------------------- 96 */ 97 ldr x0, =__BSS_START__ 98 ldr x1, =__BSS_SIZE__ 99 bl zeromem 100 101#if USE_COHERENT_MEM 102 ldr x0, =__COHERENT_RAM_START__ 103 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 104 bl zeromem 105#endif 106 107 /* -------------------------------------------- 108 * Allocate a stack whose memory will be marked 109 * as Normal-IS-WBWA when the MMU is enabled. 110 * There is no risk of reading stale stack 111 * memory after enabling the MMU as only the 112 * primary cpu is running at the moment. 113 * -------------------------------------------- 114 */ 115 bl plat_set_my_stack 116 117 /* --------------------------------------------- 118 * Initialize the stack protector canary before 119 * any C code is called. 120 * --------------------------------------------- 121 */ 122#if STACK_PROTECTOR_ENABLED 123 bl update_stack_protector_canary 124#endif 125 126 /* --------------------------------------------- 127 * Perform TSP setup 128 * --------------------------------------------- 129 */ 130 bl tsp_setup 131 132 /* --------------------------------------------- 133 * Enable pointer authentication 134 * --------------------------------------------- 135 */ 136#if ENABLE_PAUTH 137 mrs x0, sctlr_el1 138 orr x0, x0, #SCTLR_EnIA_BIT 139#if ENABLE_BTI 140 /* --------------------------------------------- 141 * Enable PAC branch type compatibility 142 * --------------------------------------------- 143 */ 144 bic x0, x0, #(SCTLR_BT0_BIT | SCTLR_BT1_BIT) 145#endif /* ENABLE_BTI */ 146 msr sctlr_el1, x0 147 isb 148#endif /* ENABLE_PAUTH */ 149 150 /* --------------------------------------------- 151 * Jump to main function. 152 * --------------------------------------------- 153 */ 154 bl tsp_main 155 156 /* --------------------------------------------- 157 * Tell TSPD that we are done initialising 158 * --------------------------------------------- 159 */ 160 mov x1, x0 161 mov x0, #TSP_ENTRY_DONE 162 smc #0 163 164tsp_entrypoint_panic: 165 b tsp_entrypoint_panic 166endfunc tsp_entrypoint 167 168 169 /* ------------------------------------------- 170 * Table of entrypoint vectors provided to the 171 * TSPD for the various entrypoints 172 * ------------------------------------------- 173 */ 174vector_base tsp_vector_table 175 b tsp_yield_smc_entry 176 b tsp_fast_smc_entry 177 b tsp_cpu_on_entry 178 b tsp_cpu_off_entry 179 b tsp_cpu_resume_entry 180 b tsp_cpu_suspend_entry 181 b tsp_sel1_intr_entry 182 b tsp_system_off_entry 183 b tsp_system_reset_entry 184 b tsp_abort_yield_smc_entry 185 186 /*--------------------------------------------- 187 * This entrypoint is used by the TSPD when this 188 * cpu is to be turned off through a CPU_OFF 189 * psci call to ask the TSP to perform any 190 * bookeeping necessary. In the current 191 * implementation, the TSPD expects the TSP to 192 * re-initialise its state so nothing is done 193 * here except for acknowledging the request. 194 * --------------------------------------------- 195 */ 196func tsp_cpu_off_entry 197 bl tsp_cpu_off_main 198 restore_args_call_smc 199endfunc tsp_cpu_off_entry 200 201 /*--------------------------------------------- 202 * This entrypoint is used by the TSPD when the 203 * system is about to be switched off (through 204 * a SYSTEM_OFF psci call) to ask the TSP to 205 * perform any necessary bookkeeping. 206 * --------------------------------------------- 207 */ 208func tsp_system_off_entry 209 bl tsp_system_off_main 210 restore_args_call_smc 211endfunc tsp_system_off_entry 212 213 /*--------------------------------------------- 214 * This entrypoint is used by the TSPD when the 215 * system is about to be reset (through a 216 * SYSTEM_RESET psci call) to ask the TSP to 217 * perform any necessary bookkeeping. 218 * --------------------------------------------- 219 */ 220func tsp_system_reset_entry 221 bl tsp_system_reset_main 222 restore_args_call_smc 223endfunc tsp_system_reset_entry 224 225 /*--------------------------------------------- 226 * This entrypoint is used by the TSPD when this 227 * cpu is turned on using a CPU_ON psci call to 228 * ask the TSP to initialise itself i.e. setup 229 * the mmu, stacks etc. Minimal architectural 230 * state will be initialised by the TSPD when 231 * this function is entered i.e. Caches and MMU 232 * will be turned off, the execution state 233 * will be aarch64 and exceptions masked. 234 * --------------------------------------------- 235 */ 236func tsp_cpu_on_entry 237 /* --------------------------------------------- 238 * Set the exception vector to something sane. 239 * --------------------------------------------- 240 */ 241 adr x0, tsp_exceptions 242 msr vbar_el1, x0 243 isb 244 245 /* Enable the SError interrupt */ 246 msr daifclr, #DAIF_ABT_BIT 247 248 /* --------------------------------------------- 249 * Enable the instruction cache, stack pointer 250 * and data access alignment checks 251 * --------------------------------------------- 252 */ 253 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 254 mrs x0, sctlr_el1 255 orr x0, x0, x1 256 msr sctlr_el1, x0 257 isb 258 259 /* -------------------------------------------- 260 * Give ourselves a stack whose memory will be 261 * marked as Normal-IS-WBWA when the MMU is 262 * enabled. 263 * -------------------------------------------- 264 */ 265 bl plat_set_my_stack 266 267 /* -------------------------------------------- 268 * Enable MMU and D-caches together. 269 * -------------------------------------------- 270 */ 271 mov x0, #0 272 bl bl32_plat_enable_mmu 273 274 /* --------------------------------------------- 275 * Enter C runtime to perform any remaining 276 * book keeping 277 * --------------------------------------------- 278 */ 279 bl tsp_cpu_on_main 280 restore_args_call_smc 281 282 /* Should never reach here */ 283tsp_cpu_on_entry_panic: 284 b tsp_cpu_on_entry_panic 285endfunc tsp_cpu_on_entry 286 287 /*--------------------------------------------- 288 * This entrypoint is used by the TSPD when this 289 * cpu is to be suspended through a CPU_SUSPEND 290 * psci call to ask the TSP to perform any 291 * bookeeping necessary. In the current 292 * implementation, the TSPD saves and restores 293 * the EL1 state. 294 * --------------------------------------------- 295 */ 296func tsp_cpu_suspend_entry 297 bl tsp_cpu_suspend_main 298 restore_args_call_smc 299endfunc tsp_cpu_suspend_entry 300 301 /*------------------------------------------------- 302 * This entrypoint is used by the TSPD to pass 303 * control for `synchronously` handling a S-EL1 304 * Interrupt which was triggered while executing 305 * in normal world. 'x0' contains a magic number 306 * which indicates this. TSPD expects control to 307 * be handed back at the end of interrupt 308 * processing. This is done through an SMC. 309 * The handover agreement is: 310 * 311 * 1. PSTATE.DAIF are set upon entry. 'x1' has 312 * the ELR_EL3 from the non-secure state. 313 * 2. TSP has to preserve the callee saved 314 * general purpose registers, SP_EL1/EL0 and 315 * LR. 316 * 3. TSP has to preserve the system and vfp 317 * registers (if applicable). 318 * 4. TSP can use 'x0-x18' to enable its C 319 * runtime. 320 * 5. TSP returns to TSPD using an SMC with 321 * 'x0' = TSP_HANDLED_S_EL1_INTR 322 * ------------------------------------------------ 323 */ 324func tsp_sel1_intr_entry 325#if DEBUG 326 mov_imm x2, TSP_HANDLE_SEL1_INTR_AND_RETURN 327 cmp x0, x2 328 b.ne tsp_sel1_int_entry_panic 329#endif 330 /*------------------------------------------------- 331 * Save any previous context needed to perform 332 * an exception return from S-EL1 e.g. context 333 * from a previous Non secure Interrupt. 334 * Update statistics and handle the S-EL1 335 * interrupt before returning to the TSPD. 336 * IRQ/FIQs are not enabled since that will 337 * complicate the implementation. Execution 338 * will be transferred back to the normal world 339 * in any case. The handler can return 0 340 * if the interrupt was handled or TSP_PREEMPTED 341 * if the expected interrupt was preempted 342 * by an interrupt that should be handled in EL3 343 * e.g. Group 0 interrupt in GICv3. In both 344 * the cases switch to EL3 using SMC with id 345 * TSP_HANDLED_S_EL1_INTR. Any other return value 346 * from the handler will result in panic. 347 * ------------------------------------------------ 348 */ 349 save_eret_context x2 x3 350 bl tsp_update_sync_sel1_intr_stats 351 bl tsp_common_int_handler 352 /* Check if the S-EL1 interrupt has been handled */ 353 cbnz x0, tsp_sel1_intr_check_preemption 354 b tsp_sel1_intr_return 355tsp_sel1_intr_check_preemption: 356 /* Check if the S-EL1 interrupt has been preempted */ 357 mov_imm x1, TSP_PREEMPTED 358 cmp x0, x1 359 b.ne tsp_sel1_int_entry_panic 360tsp_sel1_intr_return: 361 mov_imm x0, TSP_HANDLED_S_EL1_INTR 362 restore_eret_context x2 x3 363 smc #0 364 365 /* Should never reach here */ 366tsp_sel1_int_entry_panic: 367 no_ret plat_panic_handler 368endfunc tsp_sel1_intr_entry 369 370 /*--------------------------------------------- 371 * This entrypoint is used by the TSPD when this 372 * cpu resumes execution after an earlier 373 * CPU_SUSPEND psci call to ask the TSP to 374 * restore its saved context. In the current 375 * implementation, the TSPD saves and restores 376 * EL1 state so nothing is done here apart from 377 * acknowledging the request. 378 * --------------------------------------------- 379 */ 380func tsp_cpu_resume_entry 381 bl tsp_cpu_resume_main 382 restore_args_call_smc 383 384 /* Should never reach here */ 385 no_ret plat_panic_handler 386endfunc tsp_cpu_resume_entry 387 388 /*--------------------------------------------- 389 * This entrypoint is used by the TSPD to ask 390 * the TSP to service a fast smc request. 391 * --------------------------------------------- 392 */ 393func tsp_fast_smc_entry 394 bl tsp_smc_handler 395 restore_args_call_smc 396 397 /* Should never reach here */ 398 no_ret plat_panic_handler 399endfunc tsp_fast_smc_entry 400 401 /*--------------------------------------------- 402 * This entrypoint is used by the TSPD to ask 403 * the TSP to service a Yielding SMC request. 404 * We will enable preemption during execution 405 * of tsp_smc_handler. 406 * --------------------------------------------- 407 */ 408func tsp_yield_smc_entry 409 msr daifclr, #DAIF_FIQ_BIT | DAIF_IRQ_BIT 410 bl tsp_smc_handler 411 msr daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT 412 restore_args_call_smc 413 414 /* Should never reach here */ 415 no_ret plat_panic_handler 416endfunc tsp_yield_smc_entry 417 418 /*--------------------------------------------------------------------- 419 * This entrypoint is used by the TSPD to abort a pre-empted Yielding 420 * SMC. It could be on behalf of non-secure world or because a CPU 421 * suspend/CPU off request needs to abort the preempted SMC. 422 * -------------------------------------------------------------------- 423 */ 424func tsp_abort_yield_smc_entry 425 426 /* 427 * Exceptions masking is already done by the TSPD when entering this 428 * hook so there is no need to do it here. 429 */ 430 431 /* Reset the stack used by the pre-empted SMC */ 432 bl plat_set_my_stack 433 434 /* 435 * Allow some cleanup such as releasing locks. 436 */ 437 bl tsp_abort_smc_handler 438 439 restore_args_call_smc 440 441 /* Should never reach here */ 442 bl plat_panic_handler 443endfunc tsp_abort_yield_smc_entry 444