1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <tsp.h> 34#include <xlat_tables.h> 35 36 37 .globl tsp_entrypoint 38 .globl tsp_vector_table 39 40 41 42 /* --------------------------------------------- 43 * Populate the params in x0-x7 from the pointer 44 * to the smc args structure in x0. 45 * --------------------------------------------- 46 */ 47 .macro restore_args_call_smc 48 ldp x6, x7, [x0, #TSP_ARG6] 49 ldp x4, x5, [x0, #TSP_ARG4] 50 ldp x2, x3, [x0, #TSP_ARG2] 51 ldp x0, x1, [x0, #TSP_ARG0] 52 smc #0 53 .endm 54 55 .macro save_eret_context reg1 reg2 56 mrs \reg1, elr_el1 57 mrs \reg2, spsr_el1 58 stp \reg1, \reg2, [sp, #-0x10]! 59 stp x30, x18, [sp, #-0x10]! 60 .endm 61 62 .macro restore_eret_context reg1 reg2 63 ldp x30, x18, [sp], #0x10 64 ldp \reg1, \reg2, [sp], #0x10 65 msr elr_el1, \reg1 66 msr spsr_el1, \reg2 67 .endm 68 69 .section .text, "ax" 70 .align 3 71 72func tsp_entrypoint 73 74 /* --------------------------------------------- 75 * The entrypoint is expected to be executed 76 * only by the primary cpu (at least for now). 77 * So, make sure no secondary has lost its way. 78 * --------------------------------------------- 79 */ 80 mrs x0, mpidr_el1 81 bl platform_is_primary_cpu 82 cbz x0, tsp_entrypoint_panic 83 84 /* --------------------------------------------- 85 * Set the exception vector to something sane. 86 * --------------------------------------------- 87 */ 88 adr x0, tsp_exceptions 89 msr vbar_el1, x0 90 91 /* --------------------------------------------- 92 * Enable the instruction cache, stack pointer 93 * and data access alignment checks 94 * --------------------------------------------- 95 */ 96 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 97 mrs x0, sctlr_el1 98 orr x0, x0, x1 99 msr sctlr_el1, x0 100 isb 101 102 /* --------------------------------------------- 103 * Zero out NOBITS sections. There are 2 of them: 104 * - the .bss section; 105 * - the coherent memory section. 106 * --------------------------------------------- 107 */ 108 ldr x0, =__BSS_START__ 109 ldr x1, =__BSS_SIZE__ 110 bl zeromem16 111 112 ldr x0, =__COHERENT_RAM_START__ 113 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 114 bl zeromem16 115 116 /* -------------------------------------------- 117 * Allocate a stack whose memory will be marked 118 * as Normal-IS-WBWA when the MMU is enabled. 119 * There is no risk of reading stale stack 120 * memory after enabling the MMU as only the 121 * primary cpu is running at the moment. 122 * -------------------------------------------- 123 */ 124 mrs x0, mpidr_el1 125 bl platform_set_stack 126 127 /* --------------------------------------------- 128 * Perform early platform setup & platform 129 * specific early arch. setup e.g. mmu setup 130 * --------------------------------------------- 131 */ 132 bl bl32_early_platform_setup 133 bl bl32_plat_arch_setup 134 135 /* --------------------------------------------- 136 * Jump to main function. 137 * --------------------------------------------- 138 */ 139 bl tsp_main 140 141 /* --------------------------------------------- 142 * Tell TSPD that we are done initialising 143 * --------------------------------------------- 144 */ 145 mov x1, x0 146 mov x0, #TSP_ENTRY_DONE 147 smc #0 148 149tsp_entrypoint_panic: 150 b tsp_entrypoint_panic 151 152 153 /* ------------------------------------------- 154 * Table of entrypoint vectors provided to the 155 * TSPD for the various entrypoints 156 * ------------------------------------------- 157 */ 158func tsp_vector_table 159 b tsp_std_smc_entry 160 b tsp_fast_smc_entry 161 b tsp_cpu_on_entry 162 b tsp_cpu_off_entry 163 b tsp_cpu_resume_entry 164 b tsp_cpu_suspend_entry 165 b tsp_fiq_entry 166 167 /*--------------------------------------------- 168 * This entrypoint is used by the TSPD when this 169 * cpu is to be turned off through a CPU_OFF 170 * psci call to ask the TSP to perform any 171 * bookeeping necessary. In the current 172 * implementation, the TSPD expects the TSP to 173 * re-initialise its state so nothing is done 174 * here except for acknowledging the request. 175 * --------------------------------------------- 176 */ 177func tsp_cpu_off_entry 178 bl tsp_cpu_off_main 179 restore_args_call_smc 180 181 /*--------------------------------------------- 182 * This entrypoint is used by the TSPD when this 183 * cpu is turned on using a CPU_ON psci call to 184 * ask the TSP to initialise itself i.e. setup 185 * the mmu, stacks etc. Minimal architectural 186 * state will be initialised by the TSPD when 187 * this function is entered i.e. Caches and MMU 188 * will be turned off, the execution state 189 * will be aarch64 and exceptions masked. 190 * --------------------------------------------- 191 */ 192func tsp_cpu_on_entry 193 /* --------------------------------------------- 194 * Set the exception vector to something sane. 195 * --------------------------------------------- 196 */ 197 adr x0, tsp_exceptions 198 msr vbar_el1, x0 199 200 /* --------------------------------------------- 201 * Enable the instruction cache, stack pointer 202 * and data access alignment checks 203 * --------------------------------------------- 204 */ 205 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 206 mrs x0, sctlr_el1 207 orr x0, x0, x1 208 msr sctlr_el1, x0 209 isb 210 211 /* -------------------------------------------- 212 * Give ourselves a stack whose memory will be 213 * marked as Normal-IS-WBWA when the MMU is 214 * enabled. 215 * -------------------------------------------- 216 */ 217 mrs x0, mpidr_el1 218 bl platform_set_stack 219 220 /* -------------------------------------------- 221 * Enable the MMU with the DCache disabled. It 222 * is safe to use stacks allocated in normal 223 * memory as a result. All memory accesses are 224 * marked nGnRnE when the MMU is disabled. So 225 * all the stack writes will make it to memory. 226 * All memory accesses are marked Non-cacheable 227 * when the MMU is enabled but D$ is disabled. 228 * So used stack memory is guaranteed to be 229 * visible immediately after the MMU is enabled 230 * Enabling the DCache at the same time as the 231 * MMU can lead to speculatively fetched and 232 * possibly stale stack memory being read from 233 * other caches. This can lead to coherency 234 * issues. 235 * -------------------------------------------- 236 */ 237 mov x0, #DISABLE_DCACHE 238 bl bl32_plat_enable_mmu 239 240 /* --------------------------------------------- 241 * Enable the Data cache now that the MMU has 242 * been enabled. The stack has been unwound. It 243 * will be written first before being read. This 244 * will invalidate any stale cache lines resi- 245 * -dent in other caches. We assume that 246 * interconnect coherency has been enabled for 247 * this cluster by EL3 firmware. 248 * --------------------------------------------- 249 */ 250 mrs x0, sctlr_el1 251 orr x0, x0, #SCTLR_C_BIT 252 msr sctlr_el1, x0 253 isb 254 255 /* --------------------------------------------- 256 * Enter C runtime to perform any remaining 257 * book keeping 258 * --------------------------------------------- 259 */ 260 bl tsp_cpu_on_main 261 restore_args_call_smc 262 263 /* Should never reach here */ 264tsp_cpu_on_entry_panic: 265 b tsp_cpu_on_entry_panic 266 267 /*--------------------------------------------- 268 * This entrypoint is used by the TSPD when this 269 * cpu is to be suspended through a CPU_SUSPEND 270 * psci call to ask the TSP to perform any 271 * bookeeping necessary. In the current 272 * implementation, the TSPD saves and restores 273 * the EL1 state. 274 * --------------------------------------------- 275 */ 276func tsp_cpu_suspend_entry 277 bl tsp_cpu_suspend_main 278 restore_args_call_smc 279 280 /*--------------------------------------------- 281 * This entrypoint is used by the TSPD to pass 282 * control for handling a pending S-EL1 FIQ. 283 * 'x0' contains a magic number which indicates 284 * this. TSPD expects control to be handed back 285 * at the end of FIQ processing. This is done 286 * through an SMC. The handover agreement is: 287 * 288 * 1. PSTATE.DAIF are set upon entry. 'x1' has 289 * the ELR_EL3 from the non-secure state. 290 * 2. TSP has to preserve the callee saved 291 * general purpose registers, SP_EL1/EL0 and 292 * LR. 293 * 3. TSP has to preserve the system and vfp 294 * registers (if applicable). 295 * 4. TSP can use 'x0-x18' to enable its C 296 * runtime. 297 * 5. TSP returns to TSPD using an SMC with 298 * 'x0' = TSP_HANDLED_S_EL1_FIQ 299 * --------------------------------------------- 300 */ 301func tsp_fiq_entry 302#if DEBUG 303 mov x2, #(TSP_HANDLE_FIQ_AND_RETURN & ~0xffff) 304 movk x2, #(TSP_HANDLE_FIQ_AND_RETURN & 0xffff) 305 cmp x0, x2 306 b.ne tsp_fiq_entry_panic 307#endif 308 /*--------------------------------------------- 309 * Save any previous context needed to perform 310 * an exception return from S-EL1 e.g. context 311 * from a previous IRQ. Update statistics and 312 * handle the FIQ before returning to the TSPD. 313 * IRQ/FIQs are not enabled since that will 314 * complicate the implementation. Execution 315 * will be transferred back to the normal world 316 * in any case. A non-zero return value from the 317 * fiq handler is an error. 318 * --------------------------------------------- 319 */ 320 save_eret_context x2 x3 321 bl tsp_update_sync_fiq_stats 322 bl tsp_fiq_handler 323 cbnz x0, tsp_fiq_entry_panic 324 restore_eret_context x2 x3 325 mov x0, #(TSP_HANDLED_S_EL1_FIQ & ~0xffff) 326 movk x0, #(TSP_HANDLED_S_EL1_FIQ & 0xffff) 327 smc #0 328 329tsp_fiq_entry_panic: 330 b tsp_fiq_entry_panic 331 332 /*--------------------------------------------- 333 * This entrypoint is used by the TSPD when this 334 * cpu resumes execution after an earlier 335 * CPU_SUSPEND psci call to ask the TSP to 336 * restore its saved context. In the current 337 * implementation, the TSPD saves and restores 338 * EL1 state so nothing is done here apart from 339 * acknowledging the request. 340 * --------------------------------------------- 341 */ 342func tsp_cpu_resume_entry 343 bl tsp_cpu_resume_main 344 restore_args_call_smc 345tsp_cpu_resume_panic: 346 b tsp_cpu_resume_panic 347 348 /*--------------------------------------------- 349 * This entrypoint is used by the TSPD to ask 350 * the TSP to service a fast smc request. 351 * --------------------------------------------- 352 */ 353func tsp_fast_smc_entry 354 bl tsp_smc_handler 355 restore_args_call_smc 356tsp_fast_smc_entry_panic: 357 b tsp_fast_smc_entry_panic 358 359 /*--------------------------------------------- 360 * This entrypoint is used by the TSPD to ask 361 * the TSP to service a std smc request. 362 * We will enable preemption during execution 363 * of tsp_smc_handler. 364 * --------------------------------------------- 365 */ 366func tsp_std_smc_entry 367 msr daifclr, #DAIF_FIQ_BIT | DAIF_IRQ_BIT 368 bl tsp_smc_handler 369 msr daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT 370 restore_args_call_smc 371tsp_std_smc_entry_panic: 372 b tsp_std_smc_entry_panic 373