1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <tsp.h> 34#include <xlat_tables.h> 35 36 37 .globl tsp_entrypoint 38 .globl tsp_vector_table 39 40 41 42 /* --------------------------------------------- 43 * Populate the params in x0-x7 from the pointer 44 * to the smc args structure in x0. 45 * --------------------------------------------- 46 */ 47 .macro restore_args_call_smc 48 ldp x6, x7, [x0, #TSP_ARG6] 49 ldp x4, x5, [x0, #TSP_ARG4] 50 ldp x2, x3, [x0, #TSP_ARG2] 51 ldp x0, x1, [x0, #TSP_ARG0] 52 smc #0 53 .endm 54 55 .macro save_eret_context reg1 reg2 56 mrs \reg1, elr_el1 57 mrs \reg2, spsr_el1 58 stp \reg1, \reg2, [sp, #-0x10]! 59 stp x30, x18, [sp, #-0x10]! 60 .endm 61 62 .macro restore_eret_context reg1 reg2 63 ldp x30, x18, [sp], #0x10 64 ldp \reg1, \reg2, [sp], #0x10 65 msr elr_el1, \reg1 66 msr spsr_el1, \reg2 67 .endm 68 69 .section .text, "ax" 70 .align 3 71 72func tsp_entrypoint 73 74 /* --------------------------------------------- 75 * The entrypoint is expected to be executed 76 * only by the primary cpu (at least for now). 77 * So, make sure no secondary has lost its way. 78 * --------------------------------------------- 79 */ 80 mrs x0, mpidr_el1 81 bl platform_is_primary_cpu 82 cbz x0, tsp_entrypoint_panic 83 84 /* --------------------------------------------- 85 * Set the exception vector to something sane. 86 * --------------------------------------------- 87 */ 88 adr x0, tsp_exceptions 89 msr vbar_el1, x0 90 91 /* --------------------------------------------- 92 * Enable the instruction cache. 93 * --------------------------------------------- 94 */ 95 mrs x0, sctlr_el1 96 orr x0, x0, #SCTLR_I_BIT 97 msr sctlr_el1, x0 98 isb 99 100 /* --------------------------------------------- 101 * Zero out NOBITS sections. There are 2 of them: 102 * - the .bss section; 103 * - the coherent memory section. 104 * --------------------------------------------- 105 */ 106 ldr x0, =__BSS_START__ 107 ldr x1, =__BSS_SIZE__ 108 bl zeromem16 109 110 ldr x0, =__COHERENT_RAM_START__ 111 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 112 bl zeromem16 113 114 /* -------------------------------------------- 115 * Allocate a stack whose memory will be marked 116 * as Normal-IS-WBWA when the MMU is enabled. 117 * There is no risk of reading stale stack 118 * memory after enabling the MMU as only the 119 * primary cpu is running at the moment. 120 * -------------------------------------------- 121 */ 122 mrs x0, mpidr_el1 123 bl platform_set_stack 124 125 /* --------------------------------------------- 126 * Perform early platform setup & platform 127 * specific early arch. setup e.g. mmu setup 128 * --------------------------------------------- 129 */ 130 bl bl32_early_platform_setup 131 bl bl32_plat_arch_setup 132 133 /* --------------------------------------------- 134 * Jump to main function. 135 * --------------------------------------------- 136 */ 137 bl tsp_main 138 139 /* --------------------------------------------- 140 * Tell TSPD that we are done initialising 141 * --------------------------------------------- 142 */ 143 mov x1, x0 144 mov x0, #TSP_ENTRY_DONE 145 smc #0 146 147tsp_entrypoint_panic: 148 b tsp_entrypoint_panic 149 150 151 /* ------------------------------------------- 152 * Table of entrypoint vectors provided to the 153 * TSPD for the various entrypoints 154 * ------------------------------------------- 155 */ 156func tsp_vector_table 157 b tsp_std_smc_entry 158 b tsp_fast_smc_entry 159 b tsp_cpu_on_entry 160 b tsp_cpu_off_entry 161 b tsp_cpu_resume_entry 162 b tsp_cpu_suspend_entry 163 b tsp_fiq_entry 164 165 /*--------------------------------------------- 166 * This entrypoint is used by the TSPD when this 167 * cpu is to be turned off through a CPU_OFF 168 * psci call to ask the TSP to perform any 169 * bookeeping necessary. In the current 170 * implementation, the TSPD expects the TSP to 171 * re-initialise its state so nothing is done 172 * here except for acknowledging the request. 173 * --------------------------------------------- 174 */ 175func tsp_cpu_off_entry 176 bl tsp_cpu_off_main 177 restore_args_call_smc 178 179 /*--------------------------------------------- 180 * This entrypoint is used by the TSPD when this 181 * cpu is turned on using a CPU_ON psci call to 182 * ask the TSP to initialise itself i.e. setup 183 * the mmu, stacks etc. Minimal architectural 184 * state will be initialised by the TSPD when 185 * this function is entered i.e. Caches and MMU 186 * will be turned off, the execution state 187 * will be aarch64 and exceptions masked. 188 * --------------------------------------------- 189 */ 190func tsp_cpu_on_entry 191 /* --------------------------------------------- 192 * Set the exception vector to something sane. 193 * --------------------------------------------- 194 */ 195 adr x0, tsp_exceptions 196 msr vbar_el1, x0 197 198 /* --------------------------------------------- 199 * Enable the instruction cache. 200 * --------------------------------------------- 201 */ 202 mrs x0, sctlr_el1 203 orr x0, x0, #SCTLR_I_BIT 204 msr sctlr_el1, x0 205 isb 206 207 /* -------------------------------------------- 208 * Give ourselves a stack whose memory will be 209 * marked as Normal-IS-WBWA when the MMU is 210 * enabled. 211 * -------------------------------------------- 212 */ 213 mrs x0, mpidr_el1 214 bl platform_set_stack 215 216 /* -------------------------------------------- 217 * Enable the MMU with the DCache disabled. It 218 * is safe to use stacks allocated in normal 219 * memory as a result. All memory accesses are 220 * marked nGnRnE when the MMU is disabled. So 221 * all the stack writes will make it to memory. 222 * All memory accesses are marked Non-cacheable 223 * when the MMU is enabled but D$ is disabled. 224 * So used stack memory is guaranteed to be 225 * visible immediately after the MMU is enabled 226 * Enabling the DCache at the same time as the 227 * MMU can lead to speculatively fetched and 228 * possibly stale stack memory being read from 229 * other caches. This can lead to coherency 230 * issues. 231 * -------------------------------------------- 232 */ 233 mov x0, #DISABLE_DCACHE 234 bl bl32_plat_enable_mmu 235 236 /* --------------------------------------------- 237 * Enable the Data cache now that the MMU has 238 * been enabled. The stack has been unwound. It 239 * will be written first before being read. This 240 * will invalidate any stale cache lines resi- 241 * -dent in other caches. We assume that 242 * interconnect coherency has been enabled for 243 * this cluster by EL3 firmware. 244 * --------------------------------------------- 245 */ 246 mrs x0, sctlr_el1 247 orr x0, x0, #SCTLR_C_BIT 248 msr sctlr_el1, x0 249 isb 250 251 /* --------------------------------------------- 252 * Enter C runtime to perform any remaining 253 * book keeping 254 * --------------------------------------------- 255 */ 256 bl tsp_cpu_on_main 257 restore_args_call_smc 258 259 /* Should never reach here */ 260tsp_cpu_on_entry_panic: 261 b tsp_cpu_on_entry_panic 262 263 /*--------------------------------------------- 264 * This entrypoint is used by the TSPD when this 265 * cpu is to be suspended through a CPU_SUSPEND 266 * psci call to ask the TSP to perform any 267 * bookeeping necessary. In the current 268 * implementation, the TSPD saves and restores 269 * the EL1 state. 270 * --------------------------------------------- 271 */ 272func tsp_cpu_suspend_entry 273 bl tsp_cpu_suspend_main 274 restore_args_call_smc 275 276 /*--------------------------------------------- 277 * This entrypoint is used by the TSPD to pass 278 * control for handling a pending S-EL1 FIQ. 279 * 'x0' contains a magic number which indicates 280 * this. TSPD expects control to be handed back 281 * at the end of FIQ processing. This is done 282 * through an SMC. The handover agreement is: 283 * 284 * 1. PSTATE.DAIF are set upon entry. 'x1' has 285 * the ELR_EL3 from the non-secure state. 286 * 2. TSP has to preserve the callee saved 287 * general purpose registers, SP_EL1/EL0 and 288 * LR. 289 * 3. TSP has to preserve the system and vfp 290 * registers (if applicable). 291 * 4. TSP can use 'x0-x18' to enable its C 292 * runtime. 293 * 5. TSP returns to TSPD using an SMC with 294 * 'x0' = TSP_HANDLED_S_EL1_FIQ 295 * --------------------------------------------- 296 */ 297func tsp_fiq_entry 298#if DEBUG 299 mov x2, #(TSP_HANDLE_FIQ_AND_RETURN & ~0xffff) 300 movk x2, #(TSP_HANDLE_FIQ_AND_RETURN & 0xffff) 301 cmp x0, x2 302 b.ne tsp_fiq_entry_panic 303#endif 304 /*--------------------------------------------- 305 * Save any previous context needed to perform 306 * an exception return from S-EL1 e.g. context 307 * from a previous IRQ. Update statistics and 308 * handle the FIQ before returning to the TSPD. 309 * IRQ/FIQs are not enabled since that will 310 * complicate the implementation. Execution 311 * will be transferred back to the normal world 312 * in any case. A non-zero return value from the 313 * fiq handler is an error. 314 * --------------------------------------------- 315 */ 316 save_eret_context x2 x3 317 bl tsp_update_sync_fiq_stats 318 bl tsp_fiq_handler 319 cbnz x0, tsp_fiq_entry_panic 320 restore_eret_context x2 x3 321 mov x0, #(TSP_HANDLED_S_EL1_FIQ & ~0xffff) 322 movk x0, #(TSP_HANDLED_S_EL1_FIQ & 0xffff) 323 smc #0 324 325tsp_fiq_entry_panic: 326 b tsp_fiq_entry_panic 327 328 /*--------------------------------------------- 329 * This entrypoint is used by the TSPD when this 330 * cpu resumes execution after an earlier 331 * CPU_SUSPEND psci call to ask the TSP to 332 * restore its saved context. In the current 333 * implementation, the TSPD saves and restores 334 * EL1 state so nothing is done here apart from 335 * acknowledging the request. 336 * --------------------------------------------- 337 */ 338func tsp_cpu_resume_entry 339 bl tsp_cpu_resume_main 340 restore_args_call_smc 341tsp_cpu_resume_panic: 342 b tsp_cpu_resume_panic 343 344 /*--------------------------------------------- 345 * This entrypoint is used by the TSPD to ask 346 * the TSP to service a fast smc request. 347 * --------------------------------------------- 348 */ 349func tsp_fast_smc_entry 350 bl tsp_smc_handler 351 restore_args_call_smc 352tsp_fast_smc_entry_panic: 353 b tsp_fast_smc_entry_panic 354 355 /*--------------------------------------------- 356 * This entrypoint is used by the TSPD to ask 357 * the TSP to service a std smc request. 358 * We will enable preemption during execution 359 * of tsp_smc_handler. 360 * --------------------------------------------- 361 */ 362func tsp_std_smc_entry 363 msr daifclr, #DAIF_FIQ_BIT | DAIF_IRQ_BIT 364 bl tsp_smc_handler 365 msr daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT 366 restore_args_call_smc 367tsp_std_smc_entry_panic: 368 b tsp_std_smc_entry_panic 369