1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <context.h> 12 #include <context_mgmt.h> 13 #include <debug.h> 14 #include <platform.h> 15 #include <platform_def.h> 16 #include <platform_sp_min.h> 17 #include <psci.h> 18 #include <runtime_svc.h> 19 #include <smcc_helpers.h> 20 #include <stddef.h> 21 #include <stdint.h> 22 #include <string.h> 23 #include <types.h> 24 #include <utils.h> 25 #include "sp_min_private.h" 26 27 /* Pointers to per-core cpu contexts */ 28 static void *sp_min_cpu_ctx_ptr[PLATFORM_CORE_COUNT]; 29 30 /* SP_MIN only stores the non secure smc context */ 31 static smc_ctx_t sp_min_smc_context[PLATFORM_CORE_COUNT]; 32 33 /****************************************************************************** 34 * Define the smcc helper library API's 35 *****************************************************************************/ 36 void *smc_get_ctx(int security_state) 37 { 38 assert(security_state == NON_SECURE); 39 return &sp_min_smc_context[plat_my_core_pos()]; 40 } 41 42 void smc_set_next_ctx(int security_state) 43 { 44 assert(security_state == NON_SECURE); 45 /* SP_MIN stores only non secure smc context. Nothing to do here */ 46 } 47 48 void *smc_get_next_ctx(void) 49 { 50 return &sp_min_smc_context[plat_my_core_pos()]; 51 } 52 53 /******************************************************************************* 54 * This function returns a pointer to the most recent 'cpu_context' structure 55 * for the calling CPU that was set as the context for the specified security 56 * state. NULL is returned if no such structure has been specified. 57 ******************************************************************************/ 58 void *cm_get_context(uint32_t security_state) 59 { 60 assert(security_state == NON_SECURE); 61 return sp_min_cpu_ctx_ptr[plat_my_core_pos()]; 62 } 63 64 /******************************************************************************* 65 * This function sets the pointer to the current 'cpu_context' structure for the 66 * specified security state for the calling CPU 67 ******************************************************************************/ 68 void cm_set_context(void *context, uint32_t security_state) 69 { 70 assert(security_state == NON_SECURE); 71 sp_min_cpu_ctx_ptr[plat_my_core_pos()] = context; 72 } 73 74 /******************************************************************************* 75 * This function returns a pointer to the most recent 'cpu_context' structure 76 * for the CPU identified by `cpu_idx` that was set as the context for the 77 * specified security state. NULL is returned if no such structure has been 78 * specified. 79 ******************************************************************************/ 80 void *cm_get_context_by_index(unsigned int cpu_idx, 81 unsigned int security_state) 82 { 83 assert(security_state == NON_SECURE); 84 return sp_min_cpu_ctx_ptr[cpu_idx]; 85 } 86 87 /******************************************************************************* 88 * This function sets the pointer to the current 'cpu_context' structure for the 89 * specified security state for the CPU identified by CPU index. 90 ******************************************************************************/ 91 void cm_set_context_by_index(unsigned int cpu_idx, void *context, 92 unsigned int security_state) 93 { 94 assert(security_state == NON_SECURE); 95 sp_min_cpu_ctx_ptr[cpu_idx] = context; 96 } 97 98 static void copy_cpu_ctx_to_smc_stx(const regs_t *cpu_reg_ctx, 99 smc_ctx_t *next_smc_ctx) 100 { 101 next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0); 102 next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR); 103 next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR); 104 next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR); 105 } 106 107 /******************************************************************************* 108 * This function invokes the PSCI library interface to initialize the 109 * non secure cpu context and copies the relevant cpu context register values 110 * to smc context. These registers will get programmed during `smc_exit`. 111 ******************************************************************************/ 112 static void sp_min_prepare_next_image_entry(void) 113 { 114 entry_point_info_t *next_image_info; 115 cpu_context_t *ctx = cm_get_context(NON_SECURE); 116 u_register_t ns_sctlr; 117 118 /* Program system registers to proceed to non-secure */ 119 next_image_info = sp_min_plat_get_bl33_ep_info(); 120 assert(next_image_info); 121 assert(NON_SECURE == GET_SECURITY_STATE(next_image_info->h.attr)); 122 123 INFO("SP_MIN: Preparing exit to normal world\n"); 124 125 psci_prepare_next_non_secure_ctx(next_image_info); 126 smc_set_next_ctx(NON_SECURE); 127 128 /* Copy r0, lr and spsr from cpu context to SMC context */ 129 copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)), 130 smc_get_next_ctx()); 131 132 /* Temporarily set the NS bit to access NS SCTLR */ 133 write_scr(read_scr() | SCR_NS_BIT); 134 isb(); 135 ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR); 136 write_sctlr(ns_sctlr); 137 isb(); 138 139 write_scr(read_scr() & ~SCR_NS_BIT); 140 isb(); 141 } 142 143 /****************************************************************************** 144 * Implement the ARM Standard Service function to get arguments for a 145 * particular service. 146 *****************************************************************************/ 147 uintptr_t get_arm_std_svc_args(unsigned int svc_mask) 148 { 149 /* Setup the arguments for PSCI Library */ 150 DEFINE_STATIC_PSCI_LIB_ARGS_V1(psci_args, sp_min_warm_entrypoint); 151 152 /* PSCI is the only ARM Standard Service implemented */ 153 assert(svc_mask == PSCI_FID_MASK); 154 155 return (uintptr_t)&psci_args; 156 } 157 158 /****************************************************************************** 159 * The SP_MIN main function. Do the platform and PSCI Library setup. Also 160 * initialize the runtime service framework. 161 *****************************************************************************/ 162 void sp_min_main(void) 163 { 164 NOTICE("SP_MIN: %s\n", version_string); 165 NOTICE("SP_MIN: %s\n", build_message); 166 167 /* Perform the SP_MIN platform setup */ 168 sp_min_platform_setup(); 169 170 /* Initialize the runtime services e.g. psci */ 171 INFO("SP_MIN: Initializing runtime services\n"); 172 runtime_svc_init(); 173 174 /* 175 * We are ready to enter the next EL. Prepare entry into the image 176 * corresponding to the desired security state after the next ERET. 177 */ 178 sp_min_prepare_next_image_entry(); 179 } 180 181 /****************************************************************************** 182 * This function is invoked during warm boot. Invoke the PSCI library 183 * warm boot entry point which takes care of Architectural and platform setup/ 184 * restore. Copy the relevant cpu_context register values to smc context which 185 * will get programmed during `smc_exit`. 186 *****************************************************************************/ 187 void sp_min_warm_boot(void) 188 { 189 smc_ctx_t *next_smc_ctx; 190 191 psci_warmboot_entrypoint(); 192 193 smc_set_next_ctx(NON_SECURE); 194 195 next_smc_ctx = smc_get_next_ctx(); 196 zeromem(next_smc_ctx, sizeof(smc_ctx_t)); 197 198 copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)), 199 next_smc_ctx); 200 } 201