1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <bl_common.h> 34#include <context.h> 35#include <el3_common_macros.S> 36#include <runtime_svc.h> 37#include <smcc_helpers.h> 38#include <smcc_macros.S> 39#include <xlat_tables.h> 40 41 .globl sp_min_vector_table 42 .globl sp_min_entrypoint 43 .globl sp_min_warm_entrypoint 44 45 46vector_base sp_min_vector_table 47 b sp_min_entrypoint 48 b plat_panic_handler /* Undef */ 49 b handle_smc /* Syscall */ 50 b plat_panic_handler /* Prefetch abort */ 51 b plat_panic_handler /* Data abort */ 52 b plat_panic_handler /* Reserved */ 53 b plat_panic_handler /* IRQ */ 54 b plat_panic_handler /* FIQ */ 55 56 57/* 58 * The Cold boot/Reset entrypoint for SP_MIN 59 */ 60func sp_min_entrypoint 61#if !RESET_TO_SP_MIN 62 /* --------------------------------------------------------------- 63 * Preceding bootloader has populated r0 with a pointer to a 64 * 'bl_params_t' structure & r1 with a pointer to platform 65 * specific structure 66 * --------------------------------------------------------------- 67 */ 68 mov r11, r0 69 mov r12, r1 70 71 /* --------------------------------------------------------------------- 72 * For !RESET_TO_SP_MIN systems, only the primary CPU ever reaches 73 * sp_min_entrypoint() during the cold boot flow, so the cold/warm boot 74 * and primary/secondary CPU logic should not be executed in this case. 75 * 76 * Also, assume that the previous bootloader has already set up the CPU 77 * endianness and has initialised the memory. 78 * --------------------------------------------------------------------- 79 */ 80 el3_entrypoint_common \ 81 _set_endian=0 \ 82 _warm_boot_mailbox=0 \ 83 _secondary_cold_boot=0 \ 84 _init_memory=0 \ 85 _init_c_runtime=1 \ 86 _exception_vectors=sp_min_vector_table 87 88 /* --------------------------------------------------------------------- 89 * Relay the previous bootloader's arguments to the platform layer 90 * --------------------------------------------------------------------- 91 */ 92 mov r0, r11 93 mov r1, r12 94#else 95 /* --------------------------------------------------------------------- 96 * For RESET_TO_SP_MIN systems which have a programmable reset address, 97 * sp_min_entrypoint() is executed only on the cold boot path so we can 98 * skip the warm boot mailbox mechanism. 99 * --------------------------------------------------------------------- 100 */ 101 el3_entrypoint_common \ 102 _set_endian=1 \ 103 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 104 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 105 _init_memory=1 \ 106 _init_c_runtime=1 \ 107 _exception_vectors=sp_min_vector_table 108 109 /* --------------------------------------------------------------------- 110 * For RESET_TO_SP_MIN systems, BL32 (SP_MIN) is the first bootloader 111 * to run so there's no argument to relay from a previous bootloader. 112 * Zero the arguments passed to the platform layer to reflect that. 113 * --------------------------------------------------------------------- 114 */ 115 mov r0, #0 116 mov r1, #0 117#endif /* RESET_TO_SP_MIN */ 118 119 bl sp_min_early_platform_setup 120 bl sp_min_plat_arch_setup 121 122 /* Jump to the main function */ 123 bl sp_min_main 124 125 /* ------------------------------------------------------------- 126 * Clean the .data & .bss sections to main memory. This ensures 127 * that any global data which was initialised by the primary CPU 128 * is visible to secondary CPUs before they enable their data 129 * caches and participate in coherency. 130 * ------------------------------------------------------------- 131 */ 132 ldr r0, =__DATA_START__ 133 ldr r1, =__DATA_END__ 134 sub r1, r1, r0 135 bl clean_dcache_range 136 137 ldr r0, =__BSS_START__ 138 ldr r1, =__BSS_END__ 139 sub r1, r1, r0 140 bl clean_dcache_range 141 142 /* Program the registers in cpu_context and exit monitor mode */ 143 mov r0, #NON_SECURE 144 bl cm_get_context 145 146 /* Restore the SCR */ 147 ldr r2, [r0, #CTX_REGS_OFFSET + CTX_SCR] 148 stcopr r2, SCR 149 isb 150 151 /* Restore the SCTLR */ 152 ldr r2, [r0, #CTX_REGS_OFFSET + CTX_NS_SCTLR] 153 stcopr r2, SCTLR 154 155 bl smc_get_next_ctx 156 /* The other cpu_context registers have been copied to smc context */ 157 b sp_min_exit 158endfunc sp_min_entrypoint 159 160 161/* 162 * SMC handling function for SP_MIN. 163 */ 164func handle_smc 165 smcc_save_gp_mode_regs 166 167 /* r0 points to smc_context */ 168 mov r2, r0 /* handle */ 169 ldcopr r0, SCR 170 171 /* Save SCR in stack */ 172 push {r0} 173 and r3, r0, #SCR_NS_BIT /* flags */ 174 175 /* Switch to Secure Mode*/ 176 bic r0, #SCR_NS_BIT 177 stcopr r0, SCR 178 isb 179 ldr r0, [r2, #SMC_CTX_GPREG_R0] /* smc_fid */ 180 /* Check whether an SMC64 is issued */ 181 tst r0, #(FUNCID_CC_MASK << FUNCID_CC_SHIFT) 182 beq 1f /* SMC32 is detected */ 183 mov r0, #SMC_UNK 184 str r0, [r2, #SMC_CTX_GPREG_R0] 185 mov r0, r2 186 b 2f /* Skip handling the SMC */ 1871: 188 mov r1, #0 /* cookie */ 189 bl handle_runtime_svc 1902: 191 /* r0 points to smc context */ 192 193 /* Restore SCR from stack */ 194 pop {r1} 195 stcopr r1, SCR 196 isb 197 198 b sp_min_exit 199endfunc handle_smc 200 201 202/* 203 * The Warm boot entrypoint for SP_MIN. 204 */ 205func sp_min_warm_entrypoint 206 /* 207 * On the warm boot path, most of the EL3 initialisations performed by 208 * 'el3_entrypoint_common' must be skipped: 209 * 210 * - Only when the platform bypasses the BL1/BL32 (SP_MIN) entrypoint by 211 * programming the reset address do we need to set the CPU endianness. 212 * In other cases, we assume this has been taken care by the 213 * entrypoint code. 214 * 215 * - No need to determine the type of boot, we know it is a warm boot. 216 * 217 * - Do not try to distinguish between primary and secondary CPUs, this 218 * notion only exists for a cold boot. 219 * 220 * - No need to initialise the memory or the C runtime environment, 221 * it has been done once and for all on the cold boot path. 222 */ 223 el3_entrypoint_common \ 224 _set_endian=PROGRAMMABLE_RESET_ADDRESS \ 225 _warm_boot_mailbox=0 \ 226 _secondary_cold_boot=0 \ 227 _init_memory=0 \ 228 _init_c_runtime=0 \ 229 _exception_vectors=sp_min_vector_table 230 231 /* -------------------------------------------- 232 * Enable the MMU with the DCache disabled. It 233 * is safe to use stacks allocated in normal 234 * memory as a result. All memory accesses are 235 * marked nGnRnE when the MMU is disabled. So 236 * all the stack writes will make it to memory. 237 * All memory accesses are marked Non-cacheable 238 * when the MMU is enabled but D$ is disabled. 239 * So used stack memory is guaranteed to be 240 * visible immediately after the MMU is enabled 241 * Enabling the DCache at the same time as the 242 * MMU can lead to speculatively fetched and 243 * possibly stale stack memory being read from 244 * other caches. This can lead to coherency 245 * issues. 246 * -------------------------------------------- 247 */ 248 mov r0, #DISABLE_DCACHE 249 bl bl32_plat_enable_mmu 250 251 bl sp_min_warm_boot 252 253 /* Program the registers in cpu_context and exit monitor mode */ 254 mov r0, #NON_SECURE 255 bl cm_get_context 256 257 /* Restore the SCR */ 258 ldr r2, [r0, #CTX_REGS_OFFSET + CTX_SCR] 259 stcopr r2, SCR 260 isb 261 262 /* Restore the SCTLR */ 263 ldr r2, [r0, #CTX_REGS_OFFSET + CTX_NS_SCTLR] 264 stcopr r2, SCTLR 265 266 bl smc_get_next_ctx 267 268 /* The other cpu_context registers have been copied to smc context */ 269 b sp_min_exit 270endfunc sp_min_warm_entrypoint 271 272/* 273 * The function to restore the registers from SMC context and return 274 * to the mode restored to SPSR. 275 * 276 * Arguments : r0 must point to the SMC context to restore from. 277 */ 278func sp_min_exit 279 smcc_restore_gp_mode_regs 280 eret 281endfunc sp_min_exit 282