1/* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <bl_common.h> 10#include <context.h> 11#include <el3_common_macros.S> 12#include <runtime_svc.h> 13#include <smcc_helpers.h> 14#include <smcc_macros.S> 15#include <xlat_tables_defs.h> 16 17 .globl sp_min_vector_table 18 .globl sp_min_entrypoint 19 .globl sp_min_warm_entrypoint 20 21 22vector_base sp_min_vector_table 23 b sp_min_entrypoint 24 b plat_panic_handler /* Undef */ 25 b handle_smc /* Syscall */ 26 b plat_panic_handler /* Prefetch abort */ 27 b plat_panic_handler /* Data abort */ 28 b plat_panic_handler /* Reserved */ 29 b plat_panic_handler /* IRQ */ 30 b plat_panic_handler /* FIQ */ 31 32 33/* 34 * The Cold boot/Reset entrypoint for SP_MIN 35 */ 36func sp_min_entrypoint 37#if !RESET_TO_SP_MIN 38 /* --------------------------------------------------------------- 39 * Preceding bootloader has populated r0 with a pointer to a 40 * 'bl_params_t' structure & r1 with a pointer to platform 41 * specific structure 42 * --------------------------------------------------------------- 43 */ 44 mov r11, r0 45 mov r12, r1 46 47 /* --------------------------------------------------------------------- 48 * For !RESET_TO_SP_MIN systems, only the primary CPU ever reaches 49 * sp_min_entrypoint() during the cold boot flow, so the cold/warm boot 50 * and primary/secondary CPU logic should not be executed in this case. 51 * 52 * Also, assume that the previous bootloader has already initialised the 53 * SCTLR, including the CPU endianness, and has initialised the memory. 54 * --------------------------------------------------------------------- 55 */ 56 el3_entrypoint_common \ 57 _init_sctlr=0 \ 58 _warm_boot_mailbox=0 \ 59 _secondary_cold_boot=0 \ 60 _init_memory=0 \ 61 _init_c_runtime=1 \ 62 _exception_vectors=sp_min_vector_table 63 64 /* --------------------------------------------------------------------- 65 * Relay the previous bootloader's arguments to the platform layer 66 * --------------------------------------------------------------------- 67 */ 68 mov r0, r11 69 mov r1, r12 70#else 71 /* --------------------------------------------------------------------- 72 * For RESET_TO_SP_MIN systems which have a programmable reset address, 73 * sp_min_entrypoint() is executed only on the cold boot path so we can 74 * skip the warm boot mailbox mechanism. 75 * --------------------------------------------------------------------- 76 */ 77 el3_entrypoint_common \ 78 _init_sctlr=1 \ 79 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 80 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 81 _init_memory=1 \ 82 _init_c_runtime=1 \ 83 _exception_vectors=sp_min_vector_table 84 85 /* --------------------------------------------------------------------- 86 * For RESET_TO_SP_MIN systems, BL32 (SP_MIN) is the first bootloader 87 * to run so there's no argument to relay from a previous bootloader. 88 * Zero the arguments passed to the platform layer to reflect that. 89 * --------------------------------------------------------------------- 90 */ 91 mov r0, #0 92 mov r1, #0 93#endif /* RESET_TO_SP_MIN */ 94 95 bl sp_min_early_platform_setup 96 bl sp_min_plat_arch_setup 97 98 /* Jump to the main function */ 99 bl sp_min_main 100 101 /* ------------------------------------------------------------- 102 * Clean the .data & .bss sections to main memory. This ensures 103 * that any global data which was initialised by the primary CPU 104 * is visible to secondary CPUs before they enable their data 105 * caches and participate in coherency. 106 * ------------------------------------------------------------- 107 */ 108 ldr r0, =__DATA_START__ 109 ldr r1, =__DATA_END__ 110 sub r1, r1, r0 111 bl clean_dcache_range 112 113 ldr r0, =__BSS_START__ 114 ldr r1, =__BSS_END__ 115 sub r1, r1, r0 116 bl clean_dcache_range 117 118 bl smc_get_next_ctx 119 120 /* r0 points to `smc_ctx_t` */ 121 /* The PSCI cpu_context registers have been copied to `smc_ctx_t` */ 122 b sp_min_exit 123endfunc sp_min_entrypoint 124 125 126/* 127 * SMC handling function for SP_MIN. 128 */ 129func handle_smc 130 /* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */ 131 str lr, [sp, #SMC_CTX_LR_MON] 132 133 smcc_save_gp_mode_regs 134 135 /* 136 * `sp` still points to `smc_ctx_t`. Save it to a register 137 * and restore the C runtime stack pointer to `sp`. 138 */ 139 mov r2, sp /* handle */ 140 ldr sp, [r2, #SMC_CTX_SP_MON] 141 142 ldr r0, [r2, #SMC_CTX_SCR] 143 and r3, r0, #SCR_NS_BIT /* flags */ 144 145 /* Switch to Secure Mode*/ 146 bic r0, #SCR_NS_BIT 147 stcopr r0, SCR 148 isb 149 150 ldr r0, [r2, #SMC_CTX_GPREG_R0] /* smc_fid */ 151 /* Check whether an SMC64 is issued */ 152 tst r0, #(FUNCID_CC_MASK << FUNCID_CC_SHIFT) 153 beq 1f 154 /* SMC32 is not detected. Return error back to caller */ 155 mov r0, #SMC_UNK 156 str r0, [r2, #SMC_CTX_GPREG_R0] 157 mov r0, r2 158 b sp_min_exit 1591: 160 /* SMC32 is detected */ 161 mov r1, #0 /* cookie */ 162 bl handle_runtime_svc 163 164 /* `r0` points to `smc_ctx_t` */ 165 b sp_min_exit 166endfunc handle_smc 167 168/* 169 * The Warm boot entrypoint for SP_MIN. 170 */ 171func sp_min_warm_entrypoint 172 /* 173 * On the warm boot path, most of the EL3 initialisations performed by 174 * 'el3_entrypoint_common' must be skipped: 175 * 176 * - Only when the platform bypasses the BL1/BL32 (SP_MIN) entrypoint by 177 * programming the reset address do we need to initialied the SCTLR. 178 * In other cases, we assume this has been taken care by the 179 * entrypoint code. 180 * 181 * - No need to determine the type of boot, we know it is a warm boot. 182 * 183 * - Do not try to distinguish between primary and secondary CPUs, this 184 * notion only exists for a cold boot. 185 * 186 * - No need to initialise the memory or the C runtime environment, 187 * it has been done once and for all on the cold boot path. 188 */ 189 el3_entrypoint_common \ 190 _init_sctlr=PROGRAMMABLE_RESET_ADDRESS \ 191 _warm_boot_mailbox=0 \ 192 _secondary_cold_boot=0 \ 193 _init_memory=0 \ 194 _init_c_runtime=0 \ 195 _exception_vectors=sp_min_vector_table 196 197 /* 198 * We're about to enable MMU and participate in PSCI state coordination. 199 * 200 * The PSCI implementation invokes platform routines that enable CPUs to 201 * participate in coherency. On a system where CPUs are not 202 * cache-coherent without appropriate platform specific programming, 203 * having caches enabled until such time might lead to coherency issues 204 * (resulting from stale data getting speculatively fetched, among 205 * others). Therefore we keep data caches disabled even after enabling 206 * the MMU for such platforms. 207 * 208 * On systems with hardware-assisted coherency, or on single cluster 209 * platforms, such platform specific programming is not required to 210 * enter coherency (as CPUs already are); and there's no reason to have 211 * caches disabled either. 212 */ 213 mov r0, #DISABLE_DCACHE 214 bl bl32_plat_enable_mmu 215 216#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY 217 ldcopr r0, SCTLR 218 orr r0, r0, #SCTLR_C_BIT 219 stcopr r0, SCTLR 220 isb 221#endif 222 223 bl sp_min_warm_boot 224 bl smc_get_next_ctx 225 /* r0 points to `smc_ctx_t` */ 226 /* The PSCI cpu_context registers have been copied to `smc_ctx_t` */ 227 b sp_min_exit 228endfunc sp_min_warm_entrypoint 229 230/* 231 * The function to restore the registers from SMC context and return 232 * to the mode restored to SPSR. 233 * 234 * Arguments : r0 must point to the SMC context to restore from. 235 */ 236func sp_min_exit 237 monitor_exit 238endfunc sp_min_exit 239