1 /* 2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <assert.h> 32 #include <bl_common.h> 33 #include <context_mgmt.h> 34 #include <errno.h> 35 #include <interrupt_mgmt.h> 36 #include <platform.h> 37 #include <stdio.h> 38 39 /******************************************************************************* 40 * Local structure and corresponding array to keep track of the state of the 41 * registered interrupt handlers for each interrupt type. 42 * The field descriptions are: 43 * 44 * 'flags' : Bit[0], Routing model for this interrupt type when execution is 45 * not in EL3 in the secure state. '1' implies that this 46 * interrupt will be routed to EL3. '0' implies that this 47 * interrupt will be routed to the current exception level. 48 * 49 * Bit[1], Routing model for this interrupt type when execution is 50 * not in EL3 in the non-secure state. '1' implies that this 51 * interrupt will be routed to EL3. '0' implies that this 52 * interrupt will be routed to the current exception level. 53 * 54 * All other bits are reserved and SBZ. 55 * 56 * 'scr_el3[2]' : Mapping of the routing model in the 'flags' field to the 57 * value of the SCR_EL3.IRQ or FIQ bit for each security state. 58 * There are two instances of this field corresponding to the 59 * two security states. 60 ******************************************************************************/ 61 typedef struct intr_type_desc { 62 interrupt_type_handler_t handler; 63 uint32_t flags; 64 uint32_t scr_el3[2]; 65 } intr_type_desc_t; 66 67 static intr_type_desc_t intr_type_descs[MAX_INTR_TYPES]; 68 69 /******************************************************************************* 70 * This function validates the interrupt type. 71 ******************************************************************************/ 72 static int32_t validate_interrupt_type(uint32_t type) 73 { 74 if (type == INTR_TYPE_S_EL1 || type == INTR_TYPE_NS || 75 type == INTR_TYPE_EL3) 76 return 0; 77 78 return -EINVAL; 79 } 80 81 /******************************************************************************* 82 * This function validates the routing model for this type of interrupt 83 ******************************************************************************/ 84 static int32_t validate_routing_model(uint32_t type, uint32_t flags) 85 { 86 flags >>= INTR_RM_FLAGS_SHIFT; 87 flags &= INTR_RM_FLAGS_MASK; 88 89 if (type == INTR_TYPE_S_EL1) 90 return validate_sel1_interrupt_rm(flags); 91 92 if (type == INTR_TYPE_NS) 93 return validate_ns_interrupt_rm(flags); 94 95 if (type == INTR_TYPE_EL3) 96 return validate_el3_interrupt_rm(flags); 97 98 return -EINVAL; 99 } 100 101 /******************************************************************************* 102 * This function returns the cached copy of the SCR_EL3 which contains the 103 * routing model (expressed through the IRQ and FIQ bits) for a security state 104 * which was stored through a call to 'set_routing_model()' earlier. 105 ******************************************************************************/ 106 uint32_t get_scr_el3_from_routing_model(uint32_t security_state) 107 { 108 uint32_t scr_el3; 109 110 assert(sec_state_is_valid(security_state)); 111 scr_el3 = intr_type_descs[INTR_TYPE_NS].scr_el3[security_state]; 112 scr_el3 |= intr_type_descs[INTR_TYPE_S_EL1].scr_el3[security_state]; 113 scr_el3 |= intr_type_descs[INTR_TYPE_EL3].scr_el3[security_state]; 114 return scr_el3; 115 } 116 117 /******************************************************************************* 118 * This function uses the 'interrupt_type_flags' parameter to obtain the value 119 * of the trap bit (IRQ/FIQ) in the SCR_EL3 for a security state for this 120 * interrupt type. It uses it to update the SCR_EL3 in the cpu context and the 121 * 'intr_type_desc' for that security state. 122 ******************************************************************************/ 123 static void set_scr_el3_from_rm(uint32_t type, 124 uint32_t interrupt_type_flags, 125 uint32_t security_state) 126 { 127 uint32_t flag, bit_pos; 128 129 flag = get_interrupt_rm_flag(interrupt_type_flags, security_state); 130 bit_pos = plat_interrupt_type_to_line(type, security_state); 131 intr_type_descs[type].scr_el3[security_state] = flag << bit_pos; 132 133 /* Update scr_el3 only if there is a context available. If not, it 134 * will be updated later during context initialization which will obtain 135 * the scr_el3 value to be used via get_scr_el3_from_routing_model() */ 136 if (cm_get_context(security_state)) 137 cm_write_scr_el3_bit(security_state, bit_pos, flag); 138 } 139 140 /******************************************************************************* 141 * This function validates the routing model specified in the 'flags' and 142 * updates internal data structures to reflect the new routing model. It also 143 * updates the copy of SCR_EL3 for each security state with the new routing 144 * model in the 'cpu_context' structure for this cpu. 145 ******************************************************************************/ 146 int32_t set_routing_model(uint32_t type, uint32_t flags) 147 { 148 int32_t rc; 149 150 rc = validate_interrupt_type(type); 151 if (rc) 152 return rc; 153 154 rc = validate_routing_model(type, flags); 155 if (rc) 156 return rc; 157 158 /* Update the routing model in internal data structures */ 159 intr_type_descs[type].flags = flags; 160 set_scr_el3_from_rm(type, flags, SECURE); 161 set_scr_el3_from_rm(type, flags, NON_SECURE); 162 163 return 0; 164 } 165 166 /****************************************************************************** 167 * This function disables the routing model of interrupt 'type' from the 168 * specified 'security_state' on the local core. The disable is in effect 169 * till the core powers down or till the next enable for that interrupt 170 * type. 171 *****************************************************************************/ 172 int disable_intr_rm_local(uint32_t type, uint32_t security_state) 173 { 174 uint32_t bit_pos, flag; 175 176 assert(intr_type_descs[type].handler); 177 178 flag = get_interrupt_rm_flag(INTR_DEFAULT_RM, security_state); 179 180 bit_pos = plat_interrupt_type_to_line(type, security_state); 181 cm_write_scr_el3_bit(security_state, bit_pos, flag); 182 183 return 0; 184 } 185 186 /****************************************************************************** 187 * This function enables the routing model of interrupt 'type' from the 188 * specified 'security_state' on the local core. 189 *****************************************************************************/ 190 int enable_intr_rm_local(uint32_t type, uint32_t security_state) 191 { 192 uint32_t bit_pos, flag; 193 194 assert(intr_type_descs[type].handler); 195 196 flag = get_interrupt_rm_flag(intr_type_descs[type].flags, 197 security_state); 198 199 bit_pos = plat_interrupt_type_to_line(type, security_state); 200 cm_write_scr_el3_bit(security_state, bit_pos, flag); 201 202 return 0; 203 } 204 205 /******************************************************************************* 206 * This function registers a handler for the 'type' of interrupt specified. It 207 * also validates the routing model specified in the 'flags' for this type of 208 * interrupt. 209 ******************************************************************************/ 210 int32_t register_interrupt_type_handler(uint32_t type, 211 interrupt_type_handler_t handler, 212 uint32_t flags) 213 { 214 int32_t rc; 215 216 /* Validate the 'handler' parameter */ 217 if (!handler) 218 return -EINVAL; 219 220 /* Validate the 'flags' parameter */ 221 if (flags & INTR_TYPE_FLAGS_MASK) 222 return -EINVAL; 223 224 /* Check if a handler has already been registered */ 225 if (intr_type_descs[type].handler) 226 return -EALREADY; 227 228 rc = set_routing_model(type, flags); 229 if (rc) 230 return rc; 231 232 /* Save the handler */ 233 intr_type_descs[type].handler = handler; 234 235 return 0; 236 } 237 238 /******************************************************************************* 239 * This function is called when an interrupt is generated and returns the 240 * handler for the interrupt type (if registered). It returns NULL if the 241 * interrupt type is not supported or its handler has not been registered. 242 ******************************************************************************/ 243 interrupt_type_handler_t get_interrupt_type_handler(uint32_t type) 244 { 245 if (validate_interrupt_type(type)) 246 return NULL; 247 248 return intr_type_descs[type].handler; 249 } 250 251