xref: /rk3399_ARM-atf/bl31/bl31.ld.S (revision cd529320988a559c3408292f09e443233d2157c3) 
1/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <platform.h>
32
33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
34OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
35
36
37MEMORY {
38    RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
39}
40
41
42SECTIONS
43{
44    . = BL31_BASE;
45    ASSERT(. == ALIGN(4096),
46           "BL31_BASE address is not aligned on a page boundary.")
47
48    ro . : {
49        __RO_START__ = .;
50        *bl31_entrypoint.o(.text)
51        *(.text)
52        *(.rodata*)
53
54        /* Ensure 8-byte alignment for descriptors */
55        . = ALIGN(8);
56        __RT_SVC_DESCS_START__ = .;
57        *(rt_svc_descs)
58        __RT_SVC_DESCS_END__ = .;
59
60        *(.vectors)
61        __RO_END_UNALIGNED__ = .;
62        /*
63         * Memory page(s) mapped to this section will be marked as read-only,
64         * executable.  No RW data from the next section must creep in.
65         * Ensure the rest of the current memory page is unused.
66         */
67        . = NEXT(4096);
68        __RO_END__ = .;
69    } >RAM
70
71    /*
72     * The xlat_table section is for full, aligned page tables (4K).
73     * Removing them from .bss avoids forcing 4K alignment on
74     * the .bss section and eliminates the unecessary zero init
75     */
76    xlat_table (NOLOAD) : {
77        *(xlat_table)
78    } >RAM
79
80    .data . : {
81        __DATA_START__ = .;
82        *(.data)
83        __DATA_END__ = .;
84    } >RAM
85
86    stacks (NOLOAD) : {
87        __STACKS_START__ = .;
88        *(tzfw_normal_stacks)
89        __STACKS_END__ = .;
90    } >RAM
91
92    /*
93     * The .bss section gets initialised to 0 at runtime.
94     * Its base address must be 16-byte aligned.
95     */
96    .bss : ALIGN(16) {
97        __BSS_START__ = .;
98        *(.bss)
99        *(COMMON)
100        __BSS_END__ = .;
101    } >RAM
102
103    /*
104     * The .xlat_table section is for full, aligned page tables (4K).
105     * Removing them from .bss avoids forcing 4K alignment on
106     * the .bss section and eliminates the unecessary zero init
107     */
108    xlat_table (NOLOAD) : {
109        *(xlat_table)
110    } >RAM
111
112    /*
113     * The base address of the coherent memory section must be page-aligned (4K)
114     * to guarantee that the coherent data are stored on their own pages and
115     * are not mixed with normal data.  This is required to set up the correct
116     * memory attributes for the coherent data page tables.
117     */
118    coherent_ram (NOLOAD) : ALIGN(4096) {
119        __COHERENT_RAM_START__ = .;
120        *(tzfw_coherent_mem)
121        __COHERENT_RAM_END_UNALIGNED__ = .;
122        /*
123         * Memory page(s) mapped to this section will be marked
124         * as device memory.  No other unexpected data must creep in.
125         * Ensure the rest of the current memory page is unused.
126         */
127        . = NEXT(4096);
128        __COHERENT_RAM_END__ = .;
129    } >RAM
130
131    __BL31_END__ = .;
132
133    __BSS_SIZE__ = SIZEOF(.bss);
134    __COHERENT_RAM_UNALIGNED_SIZE__ =
135        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
136
137    ASSERT(. <= BL2_BASE, "BL31 image overlaps BL2 image.")
138}
139