1/* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9#include <lib/xlat_tables/xlat_tables_defs.h> 10 11OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 12OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 13ENTRY(bl31_entrypoint) 14 15 16MEMORY { 17 RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE 18} 19 20#ifdef PLAT_EXTRA_LD_SCRIPT 21#include <plat.ld.S> 22#endif 23 24SECTIONS 25{ 26 . = BL31_BASE; 27 ASSERT(. == ALIGN(PAGE_SIZE), 28 "BL31_BASE address is not aligned on a page boundary.") 29 30 __BL31_START__ = .; 31 32#if SEPARATE_CODE_AND_RODATA 33 .text . : { 34 __TEXT_START__ = .; 35 *bl31_entrypoint.o(.text*) 36 *(.text*) 37 *(.vectors) 38 . = ALIGN(PAGE_SIZE); 39 __TEXT_END__ = .; 40 } >RAM 41 42 .rodata . : { 43 __RODATA_START__ = .; 44 *(.rodata*) 45 46 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 47 . = ALIGN(8); 48 __RT_SVC_DESCS_START__ = .; 49 KEEP(*(rt_svc_descs)) 50 __RT_SVC_DESCS_END__ = .; 51 52#if ENABLE_PMF 53 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 54 . = ALIGN(8); 55 __PMF_SVC_DESCS_START__ = .; 56 KEEP(*(pmf_svc_descs)) 57 __PMF_SVC_DESCS_END__ = .; 58#endif /* ENABLE_PMF */ 59 60 /* 61 * Ensure 8-byte alignment for cpu_ops so that its fields are also 62 * aligned. Also ensure cpu_ops inclusion. 63 */ 64 . = ALIGN(8); 65 __CPU_OPS_START__ = .; 66 KEEP(*(cpu_ops)) 67 __CPU_OPS_END__ = .; 68 69 /* 70 * Keep the .got section in the RO section as it is patched 71 * prior to enabling the MMU and having the .got in RO is better for 72 * security. GOT is a table of addresses so ensure 8-byte alignment. 73 */ 74 . = ALIGN(8); 75 __GOT_START__ = .; 76 *(.got) 77 __GOT_END__ = .; 78 79 /* Place pubsub sections for events */ 80 . = ALIGN(8); 81#include <lib/el3_runtime/pubsub_events.h> 82 83 . = ALIGN(PAGE_SIZE); 84 __RODATA_END__ = .; 85 } >RAM 86#else 87 ro . : { 88 __RO_START__ = .; 89 *bl31_entrypoint.o(.text*) 90 *(.text*) 91 *(.rodata*) 92 93 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 94 . = ALIGN(8); 95 __RT_SVC_DESCS_START__ = .; 96 KEEP(*(rt_svc_descs)) 97 __RT_SVC_DESCS_END__ = .; 98 99#if ENABLE_PMF 100 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 101 . = ALIGN(8); 102 __PMF_SVC_DESCS_START__ = .; 103 KEEP(*(pmf_svc_descs)) 104 __PMF_SVC_DESCS_END__ = .; 105#endif /* ENABLE_PMF */ 106 107 /* 108 * Ensure 8-byte alignment for cpu_ops so that its fields are also 109 * aligned. Also ensure cpu_ops inclusion. 110 */ 111 . = ALIGN(8); 112 __CPU_OPS_START__ = .; 113 KEEP(*(cpu_ops)) 114 __CPU_OPS_END__ = .; 115 116 /* 117 * Keep the .got section in the RO section as it is patched 118 * prior to enabling the MMU and having the .got in RO is better for 119 * security. GOT is a table of addresses so ensure 8-byte alignment. 120 */ 121 . = ALIGN(8); 122 __GOT_START__ = .; 123 *(.got) 124 __GOT_END__ = .; 125 126 /* Place pubsub sections for events */ 127 . = ALIGN(8); 128#include <lib/el3_runtime/pubsub_events.h> 129 130 *(.vectors) 131 __RO_END_UNALIGNED__ = .; 132 /* 133 * Memory page(s) mapped to this section will be marked as read-only, 134 * executable. No RW data from the next section must creep in. 135 * Ensure the rest of the current memory page is unused. 136 */ 137 . = ALIGN(PAGE_SIZE); 138 __RO_END__ = .; 139 } >RAM 140#endif 141 142 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 143 "cpu_ops not defined for this platform.") 144 145#if ENABLE_SPM 146#ifndef SPM_SHIM_EXCEPTIONS_VMA 147#define SPM_SHIM_EXCEPTIONS_VMA RAM 148#endif 149 150 /* 151 * Exception vectors of the SPM shim layer. They must be aligned to a 2K 152 * address, but we need to place them in a separate page so that we can set 153 * individual permissions to them, so the actual alignment needed is 4K. 154 * 155 * There's no need to include this into the RO section of BL31 because it 156 * doesn't need to be accessed by BL31. 157 */ 158 spm_shim_exceptions : ALIGN(PAGE_SIZE) { 159 __SPM_SHIM_EXCEPTIONS_START__ = .; 160 *(.spm_shim_exceptions) 161 . = ALIGN(PAGE_SIZE); 162 __SPM_SHIM_EXCEPTIONS_END__ = .; 163 } >SPM_SHIM_EXCEPTIONS_VMA AT>RAM 164 165 PROVIDE(__SPM_SHIM_EXCEPTIONS_LMA__ = LOADADDR(spm_shim_exceptions)); 166 . = LOADADDR(spm_shim_exceptions) + SIZEOF(spm_shim_exceptions); 167#endif 168 169 /* 170 * Define a linker symbol to mark start of the RW memory area for this 171 * image. 172 */ 173 __RW_START__ = . ; 174 175 /* 176 * .data must be placed at a lower address than the stacks if the stack 177 * protector is enabled. Alternatively, the .data.stack_protector_canary 178 * section can be placed independently of the main .data section. 179 */ 180 .data . : { 181 __DATA_START__ = .; 182 *(.data*) 183 __DATA_END__ = .; 184 } >RAM 185 186 /* 187 * .rela.dyn needs to come after .data for the read-elf utility to parse 188 * this section correctly. Ensure 8-byte alignment so that the fields of 189 * RELA data structure are aligned. 190 */ 191 . = ALIGN(8); 192 __RELA_START__ = .; 193 .rela.dyn . : { 194 } >RAM 195 __RELA_END__ = .; 196 197#ifdef BL31_PROGBITS_LIMIT 198 ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.") 199#endif 200 201 stacks (NOLOAD) : { 202 __STACKS_START__ = .; 203 *(tzfw_normal_stacks) 204 __STACKS_END__ = .; 205 } >RAM 206 207 /* 208 * The .bss section gets initialised to 0 at runtime. 209 * Its base address should be 16-byte aligned for better performance of the 210 * zero-initialization code. 211 */ 212 .bss (NOLOAD) : ALIGN(16) { 213 __BSS_START__ = .; 214 *(.bss*) 215 *(COMMON) 216#if !USE_COHERENT_MEM 217 /* 218 * Bakery locks are stored in normal .bss memory 219 * 220 * Each lock's data is spread across multiple cache lines, one per CPU, 221 * but multiple locks can share the same cache line. 222 * The compiler will allocate enough memory for one CPU's bakery locks, 223 * the remaining cache lines are allocated by the linker script 224 */ 225 . = ALIGN(CACHE_WRITEBACK_GRANULE); 226 __BAKERY_LOCK_START__ = .; 227 *(bakery_lock) 228 . = ALIGN(CACHE_WRITEBACK_GRANULE); 229 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__); 230 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 231 __BAKERY_LOCK_END__ = .; 232 233 /* 234 * If BL31 doesn't use any bakery lock then __PERCPU_BAKERY_LOCK_SIZE__ 235 * will be zero. For this reason, the only two valid values for 236 * __PERCPU_BAKERY_LOCK_SIZE__ are 0 or the platform defined value 237 * PLAT_PERCPU_BAKERY_LOCK_SIZE. 238 */ 239#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 240 ASSERT((__PERCPU_BAKERY_LOCK_SIZE__ == 0) || (__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE), 241 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); 242#endif 243#endif 244 245#if ENABLE_PMF 246 /* 247 * Time-stamps are stored in normal .bss memory 248 * 249 * The compiler will allocate enough memory for one CPU's time-stamps, 250 * the remaining memory for other CPUs is allocated by the 251 * linker script 252 */ 253 . = ALIGN(CACHE_WRITEBACK_GRANULE); 254 __PMF_TIMESTAMP_START__ = .; 255 KEEP(*(pmf_timestamp_array)) 256 . = ALIGN(CACHE_WRITEBACK_GRANULE); 257 __PMF_PERCPU_TIMESTAMP_END__ = .; 258 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); 259 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 260 __PMF_TIMESTAMP_END__ = .; 261#endif /* ENABLE_PMF */ 262 __BSS_END__ = .; 263 } >RAM 264 265 /* 266 * The xlat_table section is for full, aligned page tables (4K). 267 * Removing them from .bss avoids forcing 4K alignment on 268 * the .bss section. The tables are initialized to zero by the translation 269 * tables library. 270 */ 271 xlat_table (NOLOAD) : { 272 *(xlat_table) 273 } >RAM 274 275#if USE_COHERENT_MEM 276 /* 277 * The base address of the coherent memory section must be page-aligned (4K) 278 * to guarantee that the coherent data are stored on their own pages and 279 * are not mixed with normal data. This is required to set up the correct 280 * memory attributes for the coherent data page tables. 281 */ 282 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 283 __COHERENT_RAM_START__ = .; 284 /* 285 * Bakery locks are stored in coherent memory 286 * 287 * Each lock's data is contiguous and fully allocated by the compiler 288 */ 289 *(bakery_lock) 290 *(tzfw_coherent_mem) 291 __COHERENT_RAM_END_UNALIGNED__ = .; 292 /* 293 * Memory page(s) mapped to this section will be marked 294 * as device memory. No other unexpected data must creep in. 295 * Ensure the rest of the current memory page is unused. 296 */ 297 . = ALIGN(PAGE_SIZE); 298 __COHERENT_RAM_END__ = .; 299 } >RAM 300#endif 301 302 /* 303 * Define a linker symbol to mark end of the RW memory area for this 304 * image. 305 */ 306 __RW_END__ = .; 307 __BL31_END__ = .; 308 309 ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") 310} 311