1/* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 10OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 11ENTRY(bl31_entrypoint) 12 13 14MEMORY { 15 RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE 16} 17 18#ifdef PLAT_EXTRA_LD_SCRIPT 19#include <plat.ld.S> 20#endif 21 22SECTIONS 23{ 24 . = BL31_BASE; 25 ASSERT(. == ALIGN(4096), 26 "BL31_BASE address is not aligned on a page boundary.") 27 28#if SEPARATE_CODE_AND_RODATA 29 .text . : { 30 __TEXT_START__ = .; 31 *bl31_entrypoint.o(.text*) 32 *(.text*) 33 *(.vectors) 34 . = NEXT(4096); 35 __TEXT_END__ = .; 36 } >RAM 37 38 .rodata . : { 39 __RODATA_START__ = .; 40 *(.rodata*) 41 42 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 43 . = ALIGN(8); 44 __RT_SVC_DESCS_START__ = .; 45 KEEP(*(rt_svc_descs)) 46 __RT_SVC_DESCS_END__ = .; 47 48#if ENABLE_PMF 49 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 50 . = ALIGN(8); 51 __PMF_SVC_DESCS_START__ = .; 52 KEEP(*(pmf_svc_descs)) 53 __PMF_SVC_DESCS_END__ = .; 54#endif /* ENABLE_PMF */ 55 56 /* 57 * Ensure 8-byte alignment for cpu_ops so that its fields are also 58 * aligned. Also ensure cpu_ops inclusion. 59 */ 60 . = ALIGN(8); 61 __CPU_OPS_START__ = .; 62 KEEP(*(cpu_ops)) 63 __CPU_OPS_END__ = .; 64 65 /* Place pubsub sections for events */ 66 . = ALIGN(8); 67#include <pubsub_events.h> 68 69 . = NEXT(4096); 70 __RODATA_END__ = .; 71 } >RAM 72#else 73 ro . : { 74 __RO_START__ = .; 75 *bl31_entrypoint.o(.text*) 76 *(.text*) 77 *(.rodata*) 78 79 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 80 . = ALIGN(8); 81 __RT_SVC_DESCS_START__ = .; 82 KEEP(*(rt_svc_descs)) 83 __RT_SVC_DESCS_END__ = .; 84 85#if ENABLE_PMF 86 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 87 . = ALIGN(8); 88 __PMF_SVC_DESCS_START__ = .; 89 KEEP(*(pmf_svc_descs)) 90 __PMF_SVC_DESCS_END__ = .; 91#endif /* ENABLE_PMF */ 92 93 /* 94 * Ensure 8-byte alignment for cpu_ops so that its fields are also 95 * aligned. Also ensure cpu_ops inclusion. 96 */ 97 . = ALIGN(8); 98 __CPU_OPS_START__ = .; 99 KEEP(*(cpu_ops)) 100 __CPU_OPS_END__ = .; 101 102 /* Place pubsub sections for events */ 103 . = ALIGN(8); 104#include <pubsub_events.h> 105 106 *(.vectors) 107 __RO_END_UNALIGNED__ = .; 108 /* 109 * Memory page(s) mapped to this section will be marked as read-only, 110 * executable. No RW data from the next section must creep in. 111 * Ensure the rest of the current memory page is unused. 112 */ 113 . = NEXT(4096); 114 __RO_END__ = .; 115 } >RAM 116#endif 117 118 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 119 "cpu_ops not defined for this platform.") 120 121#if ENABLE_SPM 122 /* 123 * Exception vectors of the SPM shim layer. They must be aligned to a 2K 124 * address, but we need to place them in a separate page so that we can set 125 * individual permissions to them, so the actual alignment needed is 4K. 126 * 127 * There's no need to include this into the RO section of BL31 because it 128 * doesn't need to be accessed by BL31. 129 */ 130 spm_shim_exceptions : ALIGN(4096) { 131 __SPM_SHIM_EXCEPTIONS_START__ = .; 132 *(.spm_shim_exceptions) 133 . = NEXT(4096); 134 __SPM_SHIM_EXCEPTIONS_END__ = .; 135 } >RAM 136#endif 137 138 /* 139 * Define a linker symbol to mark start of the RW memory area for this 140 * image. 141 */ 142 __RW_START__ = . ; 143 144 /* 145 * .data must be placed at a lower address than the stacks if the stack 146 * protector is enabled. Alternatively, the .data.stack_protector_canary 147 * section can be placed independently of the main .data section. 148 */ 149 .data . : { 150 __DATA_START__ = .; 151 *(.data*) 152 __DATA_END__ = .; 153 } >RAM 154 155#ifdef BL31_PROGBITS_LIMIT 156 ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.") 157#endif 158 159 stacks (NOLOAD) : { 160 __STACKS_START__ = .; 161 *(tzfw_normal_stacks) 162 __STACKS_END__ = .; 163 } >RAM 164 165 /* 166 * The .bss section gets initialised to 0 at runtime. 167 * Its base address should be 16-byte aligned for better performance of the 168 * zero-initialization code. 169 */ 170 .bss (NOLOAD) : ALIGN(16) { 171 __BSS_START__ = .; 172 *(.bss*) 173 *(COMMON) 174#if !USE_COHERENT_MEM 175 /* 176 * Bakery locks are stored in normal .bss memory 177 * 178 * Each lock's data is spread across multiple cache lines, one per CPU, 179 * but multiple locks can share the same cache line. 180 * The compiler will allocate enough memory for one CPU's bakery locks, 181 * the remaining cache lines are allocated by the linker script 182 */ 183 . = ALIGN(CACHE_WRITEBACK_GRANULE); 184 __BAKERY_LOCK_START__ = .; 185 *(bakery_lock) 186 . = ALIGN(CACHE_WRITEBACK_GRANULE); 187 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__); 188 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 189 __BAKERY_LOCK_END__ = .; 190#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 191 ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, 192 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); 193#endif 194#endif 195 196#if ENABLE_PMF 197 /* 198 * Time-stamps are stored in normal .bss memory 199 * 200 * The compiler will allocate enough memory for one CPU's time-stamps, 201 * the remaining memory for other CPU's is allocated by the 202 * linker script 203 */ 204 . = ALIGN(CACHE_WRITEBACK_GRANULE); 205 __PMF_TIMESTAMP_START__ = .; 206 KEEP(*(pmf_timestamp_array)) 207 . = ALIGN(CACHE_WRITEBACK_GRANULE); 208 __PMF_PERCPU_TIMESTAMP_END__ = .; 209 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); 210 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 211 __PMF_TIMESTAMP_END__ = .; 212#endif /* ENABLE_PMF */ 213 __BSS_END__ = .; 214 } >RAM 215 216 /* 217 * The xlat_table section is for full, aligned page tables (4K). 218 * Removing them from .bss avoids forcing 4K alignment on 219 * the .bss section and eliminates the unecessary zero init 220 */ 221 xlat_table (NOLOAD) : { 222#if ENABLE_SPM 223 __SP_IMAGE_XLAT_TABLES_START__ = .; 224 *secure_partition*.o(xlat_table) 225 /* Make sure that the rest of the page is empty. */ 226 . = NEXT(4096); 227 __SP_IMAGE_XLAT_TABLES_END__ = .; 228#endif 229 *(xlat_table) 230 } >RAM 231 232#if USE_COHERENT_MEM 233 /* 234 * The base address of the coherent memory section must be page-aligned (4K) 235 * to guarantee that the coherent data are stored on their own pages and 236 * are not mixed with normal data. This is required to set up the correct 237 * memory attributes for the coherent data page tables. 238 */ 239 coherent_ram (NOLOAD) : ALIGN(4096) { 240 __COHERENT_RAM_START__ = .; 241 /* 242 * Bakery locks are stored in coherent memory 243 * 244 * Each lock's data is contiguous and fully allocated by the compiler 245 */ 246 *(bakery_lock) 247 *(tzfw_coherent_mem) 248 __COHERENT_RAM_END_UNALIGNED__ = .; 249 /* 250 * Memory page(s) mapped to this section will be marked 251 * as device memory. No other unexpected data must creep in. 252 * Ensure the rest of the current memory page is unused. 253 */ 254 . = NEXT(4096); 255 __COHERENT_RAM_END__ = .; 256 } >RAM 257#endif 258 259 /* 260 * Define a linker symbol to mark end of the RW memory area for this 261 * image. 262 */ 263 __RW_END__ = .; 264 __BL31_END__ = .; 265 266 __BSS_SIZE__ = SIZEOF(.bss); 267#if USE_COHERENT_MEM 268 __COHERENT_RAM_UNALIGNED_SIZE__ = 269 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 270#endif 271 272 ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") 273} 274