1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <platform.h> 32 33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 34OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 35 36 37MEMORY { 38 RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE 39} 40 41 42SECTIONS 43{ 44 . = BL31_BASE; 45 ASSERT(. == ALIGN(4096), 46 "BL31_BASE address is not aligned on a page boundary.") 47 48 ro . : { 49 __RO_START__ = .; 50 *bl31_entrypoint.o(.text) 51 *(.text) 52 *(.rodata*) 53 54 /* Ensure 8-byte alignment for descriptors */ 55 . = ALIGN(8); 56 __RT_SVC_DESCS_START__ = .; 57 *(rt_svc_descs) 58 __RT_SVC_DESCS_END__ = .; 59 60 *(.vectors) 61 __RO_END_UNALIGNED__ = .; 62 /* 63 * Memory page(s) mapped to this section will be marked as read-only, 64 * executable. No RW data from the next section must creep in. 65 * Ensure the rest of the current memory page is unused. 66 */ 67 . = NEXT(4096); 68 __RO_END__ = .; 69 } >RAM 70 71 .data . : { 72 __DATA_START__ = .; 73 *(.data) 74 __DATA_END__ = .; 75 } >RAM 76 77 stacks (NOLOAD) : { 78 __STACKS_START__ = .; 79 *(tzfw_normal_stacks) 80 __STACKS_END__ = .; 81 } >RAM 82 83 /* 84 * The .bss section gets initialised to 0 at runtime. 85 * Its base address must be 16-byte aligned. 86 */ 87 .bss : ALIGN(16) { 88 __BSS_START__ = .; 89 *(.bss) 90 *(COMMON) 91 __BSS_END__ = .; 92 } >RAM 93 94 /* 95 * The xlat_table section is for full, aligned page tables (4K). 96 * Removing them from .bss avoids forcing 4K alignment on 97 * the .bss section and eliminates the unecessary zero init 98 */ 99 xlat_table (NOLOAD) : { 100 *(xlat_table) 101 } >RAM 102 103 /* 104 * The base address of the coherent memory section must be page-aligned (4K) 105 * to guarantee that the coherent data are stored on their own pages and 106 * are not mixed with normal data. This is required to set up the correct 107 * memory attributes for the coherent data page tables. 108 */ 109 coherent_ram (NOLOAD) : ALIGN(4096) { 110 __COHERENT_RAM_START__ = .; 111 *(tzfw_coherent_mem) 112 __COHERENT_RAM_END_UNALIGNED__ = .; 113 /* 114 * Memory page(s) mapped to this section will be marked 115 * as device memory. No other unexpected data must creep in. 116 * Ensure the rest of the current memory page is unused. 117 */ 118 . = NEXT(4096); 119 __COHERENT_RAM_END__ = .; 120 } >RAM 121 122 __BL31_END__ = .; 123 124 __BSS_SIZE__ = SIZEOF(.bss); 125 __COHERENT_RAM_UNALIGNED_SIZE__ = 126 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 127 128 ASSERT(. <= BL2_BASE, "BL31 image overlaps BL2 image.") 129} 130