1/* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <platform_def.h> 32 33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 34OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 35ENTRY(bl31_entrypoint) 36 37 38MEMORY { 39 RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE 40} 41 42 43SECTIONS 44{ 45 . = BL31_BASE; 46 ASSERT(. == ALIGN(4096), 47 "BL31_BASE address is not aligned on a page boundary.") 48 49#if SEPARATE_CODE_AND_RODATA 50 .text . : { 51 __TEXT_START__ = .; 52 *bl31_entrypoint.o(.text*) 53 *(.text*) 54 *(.vectors) 55 . = NEXT(4096); 56 __TEXT_END__ = .; 57 } >RAM 58 59 .rodata . : { 60 __RODATA_START__ = .; 61 *(.rodata*) 62 63 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 64 . = ALIGN(8); 65 __RT_SVC_DESCS_START__ = .; 66 KEEP(*(rt_svc_descs)) 67 __RT_SVC_DESCS_END__ = .; 68 69#if ENABLE_PMF 70 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 71 . = ALIGN(8); 72 __PMF_SVC_DESCS_START__ = .; 73 KEEP(*(pmf_svc_descs)) 74 __PMF_SVC_DESCS_END__ = .; 75#endif /* ENABLE_PMF */ 76 77 /* 78 * Ensure 8-byte alignment for cpu_ops so that its fields are also 79 * aligned. Also ensure cpu_ops inclusion. 80 */ 81 . = ALIGN(8); 82 __CPU_OPS_START__ = .; 83 KEEP(*(cpu_ops)) 84 __CPU_OPS_END__ = .; 85 86 . = NEXT(4096); 87 __RODATA_END__ = .; 88 } >RAM 89#else 90 ro . : { 91 __RO_START__ = .; 92 *bl31_entrypoint.o(.text*) 93 *(.text*) 94 *(.rodata*) 95 96 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 97 . = ALIGN(8); 98 __RT_SVC_DESCS_START__ = .; 99 KEEP(*(rt_svc_descs)) 100 __RT_SVC_DESCS_END__ = .; 101 102#if ENABLE_PMF 103 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 104 . = ALIGN(8); 105 __PMF_SVC_DESCS_START__ = .; 106 KEEP(*(pmf_svc_descs)) 107 __PMF_SVC_DESCS_END__ = .; 108#endif /* ENABLE_PMF */ 109 110 /* 111 * Ensure 8-byte alignment for cpu_ops so that its fields are also 112 * aligned. Also ensure cpu_ops inclusion. 113 */ 114 . = ALIGN(8); 115 __CPU_OPS_START__ = .; 116 KEEP(*(cpu_ops)) 117 __CPU_OPS_END__ = .; 118 119 *(.vectors) 120 __RO_END_UNALIGNED__ = .; 121 /* 122 * Memory page(s) mapped to this section will be marked as read-only, 123 * executable. No RW data from the next section must creep in. 124 * Ensure the rest of the current memory page is unused. 125 */ 126 . = NEXT(4096); 127 __RO_END__ = .; 128 } >RAM 129#endif 130 131 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 132 "cpu_ops not defined for this platform.") 133 134 /* 135 * Define a linker symbol to mark start of the RW memory area for this 136 * image. 137 */ 138 __RW_START__ = . ; 139 140 .data . : { 141 __DATA_START__ = .; 142 *(.data*) 143 __DATA_END__ = .; 144 } >RAM 145 146#ifdef BL31_PROGBITS_LIMIT 147 ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.") 148#endif 149 150 stacks (NOLOAD) : { 151 __STACKS_START__ = .; 152 *(tzfw_normal_stacks) 153 __STACKS_END__ = .; 154 } >RAM 155 156 /* 157 * The .bss section gets initialised to 0 at runtime. 158 * Its base address must be 16-byte aligned. 159 */ 160 .bss (NOLOAD) : ALIGN(16) { 161 __BSS_START__ = .; 162 *(.bss*) 163 *(COMMON) 164#if !USE_COHERENT_MEM 165 /* 166 * Bakery locks are stored in normal .bss memory 167 * 168 * Each lock's data is spread across multiple cache lines, one per CPU, 169 * but multiple locks can share the same cache line. 170 * The compiler will allocate enough memory for one CPU's bakery locks, 171 * the remaining cache lines are allocated by the linker script 172 */ 173 . = ALIGN(CACHE_WRITEBACK_GRANULE); 174 __BAKERY_LOCK_START__ = .; 175 *(bakery_lock) 176 . = ALIGN(CACHE_WRITEBACK_GRANULE); 177 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__); 178 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 179 __BAKERY_LOCK_END__ = .; 180#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 181 ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, 182 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); 183#endif 184#endif 185 186#if ENABLE_PMF 187 /* 188 * Time-stamps are stored in normal .bss memory 189 * 190 * The compiler will allocate enough memory for one CPU's time-stamps, 191 * the remaining memory for other CPU's is allocated by the 192 * linker script 193 */ 194 . = ALIGN(CACHE_WRITEBACK_GRANULE); 195 __PMF_TIMESTAMP_START__ = .; 196 KEEP(*(pmf_timestamp_array)) 197 . = ALIGN(CACHE_WRITEBACK_GRANULE); 198 __PMF_PERCPU_TIMESTAMP_END__ = .; 199 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); 200 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 201 __PMF_TIMESTAMP_END__ = .; 202#endif /* ENABLE_PMF */ 203 __BSS_END__ = .; 204 } >RAM 205 206 /* 207 * The xlat_table section is for full, aligned page tables (4K). 208 * Removing them from .bss avoids forcing 4K alignment on 209 * the .bss section and eliminates the unecessary zero init 210 */ 211 xlat_table (NOLOAD) : { 212 *(xlat_table) 213 } >RAM 214 215#if USE_COHERENT_MEM 216 /* 217 * The base address of the coherent memory section must be page-aligned (4K) 218 * to guarantee that the coherent data are stored on their own pages and 219 * are not mixed with normal data. This is required to set up the correct 220 * memory attributes for the coherent data page tables. 221 */ 222 coherent_ram (NOLOAD) : ALIGN(4096) { 223 __COHERENT_RAM_START__ = .; 224 /* 225 * Bakery locks are stored in coherent memory 226 * 227 * Each lock's data is contiguous and fully allocated by the compiler 228 */ 229 *(bakery_lock) 230 *(tzfw_coherent_mem) 231 __COHERENT_RAM_END_UNALIGNED__ = .; 232 /* 233 * Memory page(s) mapped to this section will be marked 234 * as device memory. No other unexpected data must creep in. 235 * Ensure the rest of the current memory page is unused. 236 */ 237 . = NEXT(4096); 238 __COHERENT_RAM_END__ = .; 239 } >RAM 240#endif 241 242 /* 243 * Define a linker symbol to mark end of the RW memory area for this 244 * image. 245 */ 246 __RW_END__ = .; 247 __BL31_END__ = .; 248 249 __BSS_SIZE__ = SIZEOF(.bss); 250#if USE_COHERENT_MEM 251 __COHERENT_RAM_UNALIGNED_SIZE__ = 252 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 253#endif 254 255 ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") 256} 257