1/* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <platform_def.h> 32 33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 34OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 35ENTRY(bl31_entrypoint) 36 37 38MEMORY { 39 RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE 40} 41 42#ifdef PLAT_EXTRA_LD_SCRIPT 43#include <plat.ld.S> 44#endif 45 46SECTIONS 47{ 48 . = BL31_BASE; 49 ASSERT(. == ALIGN(4096), 50 "BL31_BASE address is not aligned on a page boundary.") 51 52#if SEPARATE_CODE_AND_RODATA 53 .text . : { 54 __TEXT_START__ = .; 55 *bl31_entrypoint.o(.text*) 56 *(.text*) 57 *(.vectors) 58 . = NEXT(4096); 59 __TEXT_END__ = .; 60 } >RAM 61 62 .rodata . : { 63 __RODATA_START__ = .; 64 *(.rodata*) 65 66 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 67 . = ALIGN(8); 68 __RT_SVC_DESCS_START__ = .; 69 KEEP(*(rt_svc_descs)) 70 __RT_SVC_DESCS_END__ = .; 71 72#if ENABLE_PMF 73 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 74 . = ALIGN(8); 75 __PMF_SVC_DESCS_START__ = .; 76 KEEP(*(pmf_svc_descs)) 77 __PMF_SVC_DESCS_END__ = .; 78#endif /* ENABLE_PMF */ 79 80 /* 81 * Ensure 8-byte alignment for cpu_ops so that its fields are also 82 * aligned. Also ensure cpu_ops inclusion. 83 */ 84 . = ALIGN(8); 85 __CPU_OPS_START__ = .; 86 KEEP(*(cpu_ops)) 87 __CPU_OPS_END__ = .; 88 89 . = NEXT(4096); 90 __RODATA_END__ = .; 91 } >RAM 92#else 93 ro . : { 94 __RO_START__ = .; 95 *bl31_entrypoint.o(.text*) 96 *(.text*) 97 *(.rodata*) 98 99 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 100 . = ALIGN(8); 101 __RT_SVC_DESCS_START__ = .; 102 KEEP(*(rt_svc_descs)) 103 __RT_SVC_DESCS_END__ = .; 104 105#if ENABLE_PMF 106 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 107 . = ALIGN(8); 108 __PMF_SVC_DESCS_START__ = .; 109 KEEP(*(pmf_svc_descs)) 110 __PMF_SVC_DESCS_END__ = .; 111#endif /* ENABLE_PMF */ 112 113 /* 114 * Ensure 8-byte alignment for cpu_ops so that its fields are also 115 * aligned. Also ensure cpu_ops inclusion. 116 */ 117 . = ALIGN(8); 118 __CPU_OPS_START__ = .; 119 KEEP(*(cpu_ops)) 120 __CPU_OPS_END__ = .; 121 122 *(.vectors) 123 __RO_END_UNALIGNED__ = .; 124 /* 125 * Memory page(s) mapped to this section will be marked as read-only, 126 * executable. No RW data from the next section must creep in. 127 * Ensure the rest of the current memory page is unused. 128 */ 129 . = NEXT(4096); 130 __RO_END__ = .; 131 } >RAM 132#endif 133 134 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 135 "cpu_ops not defined for this platform.") 136 137 /* 138 * Define a linker symbol to mark start of the RW memory area for this 139 * image. 140 */ 141 __RW_START__ = . ; 142 143 .data . : { 144 __DATA_START__ = .; 145 *(.data*) 146 __DATA_END__ = .; 147 } >RAM 148 149#ifdef BL31_PROGBITS_LIMIT 150 ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.") 151#endif 152 153 stacks (NOLOAD) : { 154 __STACKS_START__ = .; 155 *(tzfw_normal_stacks) 156 __STACKS_END__ = .; 157 } >RAM 158 159 /* 160 * The .bss section gets initialised to 0 at runtime. 161 * Its base address should be 16-byte aligned for better performance of the 162 * zero-initialization code. 163 */ 164 .bss (NOLOAD) : ALIGN(16) { 165 __BSS_START__ = .; 166 *(.bss*) 167 *(COMMON) 168#if !USE_COHERENT_MEM 169 /* 170 * Bakery locks are stored in normal .bss memory 171 * 172 * Each lock's data is spread across multiple cache lines, one per CPU, 173 * but multiple locks can share the same cache line. 174 * The compiler will allocate enough memory for one CPU's bakery locks, 175 * the remaining cache lines are allocated by the linker script 176 */ 177 . = ALIGN(CACHE_WRITEBACK_GRANULE); 178 __BAKERY_LOCK_START__ = .; 179 *(bakery_lock) 180 . = ALIGN(CACHE_WRITEBACK_GRANULE); 181 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__); 182 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 183 __BAKERY_LOCK_END__ = .; 184#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 185 ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, 186 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); 187#endif 188#endif 189 190#if ENABLE_PMF 191 /* 192 * Time-stamps are stored in normal .bss memory 193 * 194 * The compiler will allocate enough memory for one CPU's time-stamps, 195 * the remaining memory for other CPU's is allocated by the 196 * linker script 197 */ 198 . = ALIGN(CACHE_WRITEBACK_GRANULE); 199 __PMF_TIMESTAMP_START__ = .; 200 KEEP(*(pmf_timestamp_array)) 201 . = ALIGN(CACHE_WRITEBACK_GRANULE); 202 __PMF_PERCPU_TIMESTAMP_END__ = .; 203 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); 204 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 205 __PMF_TIMESTAMP_END__ = .; 206#endif /* ENABLE_PMF */ 207 __BSS_END__ = .; 208 } >RAM 209 210 /* 211 * The xlat_table section is for full, aligned page tables (4K). 212 * Removing them from .bss avoids forcing 4K alignment on 213 * the .bss section and eliminates the unecessary zero init 214 */ 215 xlat_table (NOLOAD) : { 216 *(xlat_table) 217 } >RAM 218 219#if USE_COHERENT_MEM 220 /* 221 * The base address of the coherent memory section must be page-aligned (4K) 222 * to guarantee that the coherent data are stored on their own pages and 223 * are not mixed with normal data. This is required to set up the correct 224 * memory attributes for the coherent data page tables. 225 */ 226 coherent_ram (NOLOAD) : ALIGN(4096) { 227 __COHERENT_RAM_START__ = .; 228 /* 229 * Bakery locks are stored in coherent memory 230 * 231 * Each lock's data is contiguous and fully allocated by the compiler 232 */ 233 *(bakery_lock) 234 *(tzfw_coherent_mem) 235 __COHERENT_RAM_END_UNALIGNED__ = .; 236 /* 237 * Memory page(s) mapped to this section will be marked 238 * as device memory. No other unexpected data must creep in. 239 * Ensure the rest of the current memory page is unused. 240 */ 241 . = NEXT(4096); 242 __COHERENT_RAM_END__ = .; 243 } >RAM 244#endif 245 246 /* 247 * Define a linker symbol to mark end of the RW memory area for this 248 * image. 249 */ 250 __RW_END__ = .; 251 __BL31_END__ = .; 252 253 __BSS_SIZE__ = SIZEOF(.bss); 254#if USE_COHERENT_MEM 255 __COHERENT_RAM_UNALIGNED_SIZE__ = 256 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 257#endif 258 259 ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") 260} 261