14f6ad66aSAchin Gupta/* 2c367b75eSMadhukar Pappireddy * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 34f6ad66aSAchin Gupta * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 54f6ad66aSAchin Gupta */ 64f6ad66aSAchin Gupta 7665e71b8SMasahiro Yamada#include <common/bl_common.ld.h> 809d40e0eSAntonio Nino Diaz#include <lib/xlat_tables/xlat_tables_defs.h> 94f6ad66aSAchin Gupta 104f6ad66aSAchin GuptaOUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 114f6ad66aSAchin GuptaOUTPUT_ARCH(PLATFORM_LINKER_ARCH) 129f98aa1aSJeenu ViswambharanENTRY(bl31_entrypoint) 134f6ad66aSAchin Gupta 144f6ad66aSAchin Gupta 154f6ad66aSAchin GuptaMEMORY { 16d7fbf132SJuan Castillo RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE 17f8578e64SSamuel Holland#if SEPARATE_NOBITS_REGION 18f8578e64SSamuel Holland NOBITS (rw!a): ORIGIN = BL31_NOBITS_BASE, LENGTH = BL31_NOBITS_LIMIT - BL31_NOBITS_BASE 19f8578e64SSamuel Holland#else 20f8578e64SSamuel Holland#define NOBITS RAM 21f8578e64SSamuel Holland#endif 224f6ad66aSAchin Gupta} 234f6ad66aSAchin Gupta 24ec693569SCaesar Wang#ifdef PLAT_EXTRA_LD_SCRIPT 25ec693569SCaesar Wang#include <plat.ld.S> 26ec693569SCaesar Wang#endif 274f6ad66aSAchin Gupta 284f6ad66aSAchin GuptaSECTIONS 294f6ad66aSAchin Gupta{ 304f6ad66aSAchin Gupta . = BL31_BASE; 31a2aedac2SAntonio Nino Diaz ASSERT(. == ALIGN(PAGE_SIZE), 328d69a03fSSandrine Bailleux "BL31_BASE address is not aligned on a page boundary.") 334f6ad66aSAchin Gupta 34931f7c61SSoby Mathew __BL31_START__ = .; 35931f7c61SSoby Mathew 365d1c104fSSandrine Bailleux#if SEPARATE_CODE_AND_RODATA 375d1c104fSSandrine Bailleux .text . : { 385d1c104fSSandrine Bailleux __TEXT_START__ = .; 395d1c104fSSandrine Bailleux *bl31_entrypoint.o(.text*) 40ebd6efaeSSamuel Holland *(SORT_BY_ALIGNMENT(.text*)) 415d1c104fSSandrine Bailleux *(.vectors) 425629b2b1SRoberto Vargas . = ALIGN(PAGE_SIZE); 435d1c104fSSandrine Bailleux __TEXT_END__ = .; 445d1c104fSSandrine Bailleux } >RAM 455d1c104fSSandrine Bailleux 465d1c104fSSandrine Bailleux .rodata . : { 475d1c104fSSandrine Bailleux __RODATA_START__ = .; 48ebd6efaeSSamuel Holland *(SORT_BY_ALIGNMENT(.rodata*)) 495d1c104fSSandrine Bailleux 50*9fb288a0SMasahiro Yamada RT_SVC_DESCS 51*9fb288a0SMasahiro Yamada FCONF_POPULATOR 52*9fb288a0SMasahiro Yamada PMF_SVC_DESCS 53*9fb288a0SMasahiro Yamada CPU_OPS 54*9fb288a0SMasahiro Yamada GOT 55931f7c61SSoby Mathew 568e743bcdSJeenu Viswambharan /* Place pubsub sections for events */ 578e743bcdSJeenu Viswambharan . = ALIGN(8); 5809d40e0eSAntonio Nino Diaz#include <lib/el3_runtime/pubsub_events.h> 598e743bcdSJeenu Viswambharan 605629b2b1SRoberto Vargas . = ALIGN(PAGE_SIZE); 615d1c104fSSandrine Bailleux __RODATA_END__ = .; 625d1c104fSSandrine Bailleux } >RAM 635d1c104fSSandrine Bailleux#else 648d69a03fSSandrine Bailleux ro . : { 658d69a03fSSandrine Bailleux __RO_START__ = .; 66dccc537aSAndrew Thoelke *bl31_entrypoint.o(.text*) 67ebd6efaeSSamuel Holland *(SORT_BY_ALIGNMENT(.text*)) 68ebd6efaeSSamuel Holland *(SORT_BY_ALIGNMENT(.rodata*)) 697421b465SAchin Gupta 70*9fb288a0SMasahiro Yamada RT_SVC_DESCS 71*9fb288a0SMasahiro Yamada FCONF_POPULATOR 72*9fb288a0SMasahiro Yamada PMF_SVC_DESCS 73*9fb288a0SMasahiro Yamada CPU_OPS 74*9fb288a0SMasahiro Yamada GOT 755bfac4fcSSoby Mathew 768e743bcdSJeenu Viswambharan /* Place pubsub sections for events */ 778e743bcdSJeenu Viswambharan . = ALIGN(8); 7809d40e0eSAntonio Nino Diaz#include <lib/el3_runtime/pubsub_events.h> 798e743bcdSJeenu Viswambharan 80b739f22aSAchin Gupta *(.vectors) 818d69a03fSSandrine Bailleux __RO_END_UNALIGNED__ = .; 828d69a03fSSandrine Bailleux /* 838d69a03fSSandrine Bailleux * Memory page(s) mapped to this section will be marked as read-only, 848d69a03fSSandrine Bailleux * executable. No RW data from the next section must creep in. 858d69a03fSSandrine Bailleux * Ensure the rest of the current memory page is unused. 868d69a03fSSandrine Bailleux */ 875629b2b1SRoberto Vargas . = ALIGN(PAGE_SIZE); 888d69a03fSSandrine Bailleux __RO_END__ = .; 894f6ad66aSAchin Gupta } >RAM 905d1c104fSSandrine Bailleux#endif 914f6ad66aSAchin Gupta 929b476841SSoby Mathew ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 939b476841SSoby Mathew "cpu_ops not defined for this platform.") 949b476841SSoby Mathew 95538b0020SPaul Beesley#if SPM_MM 9632e83537SArd Biesheuvel#ifndef SPM_SHIM_EXCEPTIONS_VMA 9732e83537SArd Biesheuvel#define SPM_SHIM_EXCEPTIONS_VMA RAM 9832e83537SArd Biesheuvel#endif 9932e83537SArd Biesheuvel 1002fccb228SAntonio Nino Diaz /* 1012fccb228SAntonio Nino Diaz * Exception vectors of the SPM shim layer. They must be aligned to a 2K 1022fccb228SAntonio Nino Diaz * address, but we need to place them in a separate page so that we can set 1032fccb228SAntonio Nino Diaz * individual permissions to them, so the actual alignment needed is 4K. 1042fccb228SAntonio Nino Diaz * 1052fccb228SAntonio Nino Diaz * There's no need to include this into the RO section of BL31 because it 1062fccb228SAntonio Nino Diaz * doesn't need to be accessed by BL31. 1072fccb228SAntonio Nino Diaz */ 108a2aedac2SAntonio Nino Diaz spm_shim_exceptions : ALIGN(PAGE_SIZE) { 1092fccb228SAntonio Nino Diaz __SPM_SHIM_EXCEPTIONS_START__ = .; 1102fccb228SAntonio Nino Diaz *(.spm_shim_exceptions) 1115629b2b1SRoberto Vargas . = ALIGN(PAGE_SIZE); 1122fccb228SAntonio Nino Diaz __SPM_SHIM_EXCEPTIONS_END__ = .; 11332e83537SArd Biesheuvel } >SPM_SHIM_EXCEPTIONS_VMA AT>RAM 11432e83537SArd Biesheuvel 11532e83537SArd Biesheuvel PROVIDE(__SPM_SHIM_EXCEPTIONS_LMA__ = LOADADDR(spm_shim_exceptions)); 11632e83537SArd Biesheuvel . = LOADADDR(spm_shim_exceptions) + SIZEOF(spm_shim_exceptions); 1172fccb228SAntonio Nino Diaz#endif 1182fccb228SAntonio Nino Diaz 11954dc71e7SAchin Gupta /* 12054dc71e7SAchin Gupta * Define a linker symbol to mark start of the RW memory area for this 12154dc71e7SAchin Gupta * image. 12254dc71e7SAchin Gupta */ 12354dc71e7SAchin Gupta __RW_START__ = . ; 12454dc71e7SAchin Gupta 12551faada7SDouglas Raillard /* 12651faada7SDouglas Raillard * .data must be placed at a lower address than the stacks if the stack 12751faada7SDouglas Raillard * protector is enabled. Alternatively, the .data.stack_protector_canary 12851faada7SDouglas Raillard * section can be placed independently of the main .data section. 12951faada7SDouglas Raillard */ 1308d69a03fSSandrine Bailleux .data . : { 1318d69a03fSSandrine Bailleux __DATA_START__ = .; 132ebd6efaeSSamuel Holland *(SORT_BY_ALIGNMENT(.data*)) 1338d69a03fSSandrine Bailleux __DATA_END__ = .; 1348d69a03fSSandrine Bailleux } >RAM 1358d69a03fSSandrine Bailleux 136931f7c61SSoby Mathew /* 137931f7c61SSoby Mathew * .rela.dyn needs to come after .data for the read-elf utility to parse 1385bfac4fcSSoby Mathew * this section correctly. Ensure 8-byte alignment so that the fields of 1395bfac4fcSSoby Mathew * RELA data structure are aligned. 140931f7c61SSoby Mathew */ 1415bfac4fcSSoby Mathew . = ALIGN(8); 142931f7c61SSoby Mathew __RELA_START__ = .; 143931f7c61SSoby Mathew .rela.dyn . : { 144931f7c61SSoby Mathew } >RAM 145931f7c61SSoby Mathew __RELA_END__ = .; 146931f7c61SSoby Mathew 147a1b6db6cSSandrine Bailleux#ifdef BL31_PROGBITS_LIMIT 148d178637dSJuan Castillo ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.") 149a1b6db6cSSandrine Bailleux#endif 150a1b6db6cSSandrine Bailleux 151f8578e64SSamuel Holland#if SEPARATE_NOBITS_REGION 152f8578e64SSamuel Holland /* 153f8578e64SSamuel Holland * Define a linker symbol to mark end of the RW memory area for this 154f8578e64SSamuel Holland * image. 155f8578e64SSamuel Holland */ 156c367b75eSMadhukar Pappireddy . = ALIGN(PAGE_SIZE); 157f8578e64SSamuel Holland __RW_END__ = .; 158f8578e64SSamuel Holland __BL31_END__ = .; 159f8578e64SSamuel Holland 160f8578e64SSamuel Holland ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") 161f8578e64SSamuel Holland 162f8578e64SSamuel Holland . = BL31_NOBITS_BASE; 163f8578e64SSamuel Holland ASSERT(. == ALIGN(PAGE_SIZE), 164f8578e64SSamuel Holland "BL31 NOBITS base address is not aligned on a page boundary.") 165f8578e64SSamuel Holland 166f8578e64SSamuel Holland __NOBITS_START__ = .; 167f8578e64SSamuel Holland#endif 168f8578e64SSamuel Holland 1698d69a03fSSandrine Bailleux stacks (NOLOAD) : { 1708d69a03fSSandrine Bailleux __STACKS_START__ = .; 1714f6ad66aSAchin Gupta *(tzfw_normal_stacks) 1728d69a03fSSandrine Bailleux __STACKS_END__ = .; 173f8578e64SSamuel Holland } >NOBITS 1744f6ad66aSAchin Gupta 1758d69a03fSSandrine Bailleux /* 1768d69a03fSSandrine Bailleux * The .bss section gets initialised to 0 at runtime. 177308d359bSDouglas Raillard * Its base address should be 16-byte aligned for better performance of the 178308d359bSDouglas Raillard * zero-initialization code. 1798d69a03fSSandrine Bailleux */ 180ee7b35c4SAndrew Thoelke .bss (NOLOAD) : ALIGN(16) { 1818d69a03fSSandrine Bailleux __BSS_START__ = .; 182ebd6efaeSSamuel Holland *(SORT_BY_ALIGNMENT(.bss*)) 1834f6ad66aSAchin Gupta *(COMMON) 184*9fb288a0SMasahiro Yamada BAKERY_LOCK_NORMAL 185*9fb288a0SMasahiro Yamada PMF_TIMESTAMP 1868d69a03fSSandrine Bailleux __BSS_END__ = .; 187f8578e64SSamuel Holland } >NOBITS 1884f6ad66aSAchin Gupta 189665e71b8SMasahiro Yamada XLAT_TABLE_SECTION >NOBITS 190a0cd989dSAchin Gupta 191ab8707e6SSoby Mathew#if USE_COHERENT_MEM 192a0cd989dSAchin Gupta /* 1938d69a03fSSandrine Bailleux * The base address of the coherent memory section must be page-aligned (4K) 1948d69a03fSSandrine Bailleux * to guarantee that the coherent data are stored on their own pages and 1958d69a03fSSandrine Bailleux * are not mixed with normal data. This is required to set up the correct 1968d69a03fSSandrine Bailleux * memory attributes for the coherent data page tables. 1978d69a03fSSandrine Bailleux */ 198a2aedac2SAntonio Nino Diaz coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 1998d69a03fSSandrine Bailleux __COHERENT_RAM_START__ = .; 200ee7b35c4SAndrew Thoelke /* 201ee7b35c4SAndrew Thoelke * Bakery locks are stored in coherent memory 202ee7b35c4SAndrew Thoelke * 203ee7b35c4SAndrew Thoelke * Each lock's data is contiguous and fully allocated by the compiler 204ee7b35c4SAndrew Thoelke */ 205ee7b35c4SAndrew Thoelke *(bakery_lock) 2068d69a03fSSandrine Bailleux *(tzfw_coherent_mem) 2078d69a03fSSandrine Bailleux __COHERENT_RAM_END_UNALIGNED__ = .; 2088d69a03fSSandrine Bailleux /* 2098d69a03fSSandrine Bailleux * Memory page(s) mapped to this section will be marked 2108d69a03fSSandrine Bailleux * as device memory. No other unexpected data must creep in. 2118d69a03fSSandrine Bailleux * Ensure the rest of the current memory page is unused. 2128d69a03fSSandrine Bailleux */ 2135629b2b1SRoberto Vargas . = ALIGN(PAGE_SIZE); 2148d69a03fSSandrine Bailleux __COHERENT_RAM_END__ = .; 215f8578e64SSamuel Holland } >NOBITS 216ab8707e6SSoby Mathew#endif 2174f6ad66aSAchin Gupta 218f8578e64SSamuel Holland#if SEPARATE_NOBITS_REGION 219f8578e64SSamuel Holland /* 220f8578e64SSamuel Holland * Define a linker symbol to mark end of the NOBITS memory area for this 221f8578e64SSamuel Holland * image. 222f8578e64SSamuel Holland */ 223f8578e64SSamuel Holland __NOBITS_END__ = .; 224f8578e64SSamuel Holland 225f8578e64SSamuel Holland ASSERT(. <= BL31_NOBITS_LIMIT, "BL31 NOBITS region has exceeded its limit.") 226f8578e64SSamuel Holland#else 22754dc71e7SAchin Gupta /* 22854dc71e7SAchin Gupta * Define a linker symbol to mark end of the RW memory area for this 22954dc71e7SAchin Gupta * image. 23054dc71e7SAchin Gupta */ 23154dc71e7SAchin Gupta __RW_END__ = .; 2328d69a03fSSandrine Bailleux __BL31_END__ = .; 2334f6ad66aSAchin Gupta 234511046eaSMasahiro Yamada /DISCARD/ : { 235511046eaSMasahiro Yamada *(.dynsym .dynstr .hash .gnu.hash) 236511046eaSMasahiro Yamada } 237511046eaSMasahiro Yamada 238d178637dSJuan Castillo ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") 239f8578e64SSamuel Holland#endif 2404f6ad66aSAchin Gupta} 241